518 results on '"Juha Plosila"'
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102. Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
103. Implementation and evaluation of configuration scrubbing on CGRAs: A case study.
104. MD: Minimal path-based fault-tolerant routing in on-Chip Networks.
105. LiRCUP: Linear Regression Based CPU Usage Prediction Algorithm for Live Migration of Virtual Machines in Data Centers.
106. MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration.
107. Optimized multicore architectures for data parallel fast Fourier transform.
108. CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems.
109. Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy.
110. Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.
111. OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access.
112. PDNOC: An Efficient Partially Diagonal Network-on-Chip Design.
113. Smart hill climbing for agile dynamic mapping in many-core systems.
114. HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.
115. Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures.
116. Adaptive reinforcement learning method for networks-on-chip.
117. Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips.
118. Exploration of heuristic scheduling algorithms for 3D multicore processors.
119. LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.
120. An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture.
121. A high-efficiency low-cost heterogeneous 3D network-on-chip design.
122. An efficient history-based routing algorithm for interconnection networks.
123. Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication.
124. Vertical and horizontal integration towards collective adaptive system: a visionary approach.
125. Dual Congestion Awareness scheme in On-Chip Networks.
126. Optimized Q-learning model for distributing traffic in on-Chip Networks.
127. Parameter-Optimized Simulated Annealing for Application Mapping on Networks-on-Chip.
128. Transport layer aware design of network interface in many-core systems.
129. GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks.
130. HLS-DoNoC: High-level simulator for dynamically organizational NoCs.
131. CoNA: Dynamic application mapping for congestion reduction in many-core systems.
132. MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip.
133. Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes.
134. Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm.
135. Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs.
136. Analysis of Power Management Strategies for a Single-Chip Cloud Computer.
137. ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures.
138. CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.
139. t(k)-SA: accelerated simulated annealing algorithm for application mapping on networks-on-chip.
140. Remote Run-Time Failure Detection and Recovery Control For Quadcopters
141. Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.
142. Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.
143. Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures.
144. Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.
145. Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels.
146. A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication.
147. Agent-based on-chip network using efficient selection method.
148. Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems.
149. Analysis of Status Data Update in Dynamically Clustered Network-on-chip Monitoring.
150. Q-learning based congestion-aware routing algorithm for on-chip network.
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