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Quantum computers are becoming a reality today due to the rapid progress made by researchers in the last years. In the process of building quantum computers, IBM has developed several versions—starting from 5-qubit architectures like IBM QX2 and IBM QX4 to larger 16- or 20-qubit architectures. These architectures support arbitrary rotations of a single qubit and a controlled negation (CNOT) involving two qubits. The two qubit operations come with added coupling-map restrictions that only allow specific physical qubits to be the control and target qubits of the operation. In order to execute a quantum circuit on the IBM QX architecture, CNOT gates must satisfy the so-called coupling constraints of the architecture. Previous works addressed this issue with the objective of reducing the number of gates and the circuit depth. However, in this article, we show that further improvements are possible. To this end, we present a general approach for further improving the number of gate operations and depth of the mapped circuit. The proposed approach encompasses the selection of physical qubits, determining initial and local permutations efficiently to obtain the final circuit mapped to the given IBM QX architecture. Through experiments, improvements are observed over existing methods in terms of the number of gates and circuit depth.

In this paper we present a sequential hypothesis test for the detection of general jump size distrubution. Infinitesimal generators for the corresponding log-likelihood ratios are presented and analyzed. Bounds for infinitesimal generators in terms of super-solutions and sub-solutions are computed. This is shown to be implementable in relation to various classification problems for a crude oil price data set. Machine and deep learning algorithms are implemented to extract a specific deterministic component from the crude oil data set, and the deterministic component is implemented to improve the Barndorff-Nielsen and Shephard model, a commonly used stochastic model for derivative and commodity market analysis., Comment: 24 pages, 7 figures

The challenge of maintaining confidentiality of stored data in cloud is of utmost importance to realize the potential of cloud computing as an emerging storage solution service. Storing data in encrypted form may solve the problem, but exposes data to an adversary for each required computation. This repeated encryption decryption also diminishes the essence of cloud for storing encrypted database and huge computation power of cloud remains unused. Fully homomorphic encryption (FHE) is an effective scheme to support arbitrary operations directly on encrypted data, but has serious performance issues. In this paper, we have considered sorting on encrypted data, which is a frequently required database operation. We have investigated the feasibility of performing comparison as well as partition based sort on CPA resistant FHE data and highlight an important observation that time requirement of partition based sort on FHE data is no better than comparison based sort owing to the underlying security of the cryptosystem. We identify the recrypt operation, which is the denoising step of FHE as the main reason of costly timing requirement of such operations. We propose a FHE specific two stage sorting technique termed as $\sf {Lazy sort}$ Lazy sort with reduced recrypt operation, which proves to be better in terms of performance on FHE data in comparison to partition as well as comparison sort. Finally, we provide some multi-core implementation results to show that with proper implementation tricks performance of FHE computations can be improved further.

A commonly used stochastic model for derivative and commodity market analysis is the Barndorff-Nielsen and Shephard (BN-S) model. Though this model is very efficient and analytically tractable, it suffers from the absence of long range dependence and many other issues. For this paper, the analysis is restricted to crude oil price dynamics. A simple way of improving the BN-S model with the implementation of various machine learning algorithms is proposed. This refined BN-S model is more efficient and has fewer parameters than other models which are used in practice as improvements of the BN-S model. The procedure and the model show the application of data science for extracting a "deterministic component" out of processes that are usually considered to be completely stochastic. Empirical applications validate the efficacy of the proposed model for long range dependence.

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions. This work was supported fully by the Department of Science and Technology, Government of India, for the project “Development of CAD Tools for Synthesis, Optimization and Verification of Digital Circuits using Memristors” (Grant No. INT/AUSTRIA/BMWF/P-02/2017), and by the Austrian Agency for International Cooperation in Education and Research (OeAD, Grant No. IN 08/2017).

This paper proposes a Finite State Machine (FSM) testing technique based on deep neural network (DNN). This technique verifies the correctness of an implementation FSM-B of a specification FSM-A. Using the back-propagation algorithm, a deep neural network is trained with the input–output patterns for a given set of transition functions that specify an FSM. Initially, for FSM-A, the input patterns and the corresponding output patterns (I/O pairs) are generated. Then most of the patterns are used to train the DNN. Once the training is over, the DNN is validated with the remaining I/O pairs (around 20%). The model can be used for verifying the correctness of FSM-B after training and validation of the DNN. Some inputs are applied to FSM-B and the generated output patterns are compared with the predicted values of the proposed DNN. The difference of accuracy percentages between FSM-A and FSM-B is recorded and zero difference between them indicates the fault-free condition of the implementation FSM-B. To check the effectiveness of the scheme, the output- and state-type faults are injected to derive mutant FSMs. Experimental results performed on the MCNC FSM benchmarks prove the efficacy of the proposed method. Only a few numbers of tests are needed to detect the presence of anomaly, if any. Hence, the test time reduces significantly — resulting in an average test time reduction of 85.67% compared to the conventional techniques. To the best of our knowledge, for the first time a DNN-driven testing scheme is being proposed.

This paper models stochastic process of price time series of $ CSI $ $ 300 $ index in Chinese financial market, analyzes volatility characteristics of intraday high-frequency price data. In the new generalized Barndorff-Nielsen and Shephard model, the lag caused by asynchrony of market information and market microstructure noises are considered, and the problem of lack of long-term dependence is solved. To speed up the valuation process, several machine learning and deep learning algorithms are used to estimate parameter and evaluate forecast results. Tracking historical jumps of different magnitudes offers promising avenues for simulating dynamic price processes and predicting future jumps. Numerical results show that the deterministic component of stochastic volatility processes would always be captured over short and longer-term windows. Research finding could be suitable for influence investors and regulators interested in predicting market dynamics based on high-frequency realized volatility.

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45[Formula: see text]nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods.

Next-generation devices are expected to have higher mobility, which forces the device packaging to be small. Small devices enforce stringent power requirements for the embedded VLSI circuits. In the test mode, these circuits dissipate more power compared to the normal mode of operation. The proposed framework in this paper provides an improved solution to reduce the test power by maintaining a proper ordering of the input test patterns. A modified Kernighan-Lin (KL) graph partitioning algorithm has been used for the reordering problem. This technique assumes the circuit under test (CUT) to be a combinational or full scan sequential circuit. When tested against ISCAS'89 benchmark circuits, our framework can reduce the power dissipation better than greedy heuristics as well as some previously reported works without affecting the fault coverage. This framework also takes care of the factors that may affect the quality of the end solution.

In recent years, microfluidic biochips are being dominantly used for implementing a wide range of biochemical laboratory protocols (bioprotocols) on hand-held devices. Accurate preparation of fluid-samples is a fundamental preprocessing step that is needed in many bioprotocols. Oftentimes, for point-of-service microfluidic devices, the number of reservoirs built on-chip may be far less than that of the reactant fluids to be used in an assay. Hence, during the execution of an assay, several fluids are to be unloaded from the reservoirs to make room for loading new fluids stored off-line. Such unload-wash-load steps (switching) may be required several times, and these steps, being manual, significantly impact assay-completion time. In this paper, we address the problem of biochemical mixture preparation and propose Reservoir- and Mixer-constrained Scheduling (RMS) algorithm that executes a given mixing tree aiming to minimize the number of reactant-switching from input reservoirs. We also consider certain constraints on the availability of concurrent mixing modules. The proposed scheduling scheme can not only be applied to a number of mixture preparation algorithms but also to a general class of microfluidic devices such as digital, paper-based, and flow-based biochips. Simulation results over a large number of target ratios show that given the mixing trees obtained by standard mixing algorithms such as MinMix/RMA/CoDOS, RMS reduces switching steps (on average by 40.3%/41.9%/33%) at the cost of increasing mixing time (by only 3.5%/6.2%/4.8%), compared to an existing scheduling scheme invoked with reservoir constraints.

Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-switched architecture, Network-on-Chip (NoC), is commonly used for communication among the cores. However, technology scaling has also increased the susceptibility to internal defects in such systems. So, manufacturing tests of such multicore systems is crucial and this is a complex and time-consuming process. Due to stress on time-to-market, test engineers focus on the reduction of testtime and perform parallel tests of cores. Due to aggressive technology scaling into the nanometer regime, power consumption is also becoming a significant burden. Moreover, power consumption during manufacturing tests is more as compared to normal operation. In addition, peak power consumption is often significantly higher than the average power values. The consumed power leads to high temperature and creates hotspots, which in turn leads to failure of good parts, resulting in yield loss. Thermal safety during testing is an utmost challenging problem in NoC-based multicore systems, including three-dimensional NoC-based (3D NoC) multicore systems due to stacking of layers. This work proposes a preemptive test scheduling technique for NoC-based multicore systems to reduce the testtime by minimizing conflicts of resource usage. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). In this article, authors have also presented a thermal-aware test scheduling technique to test cores in 2D as well as 3D stacked NoC-based multicore systems using a Particle Swarm Optimization (PSO) based approach. To improve the solution further, several innovative augmentation techniques have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime and peak temperature under the power constraints and achieve a tradeoff between testtime and peak temperature.

In this paper, a refined Barndorff-Nielsen and Shephard (BN-S) model is implemented to find an optimal hedging strategy for commodity markets. The refinement of the BN-S model is obtained with various machine and deep learning algorithms. The refinement leads to the extraction of a deterministic parameter from the empirical data set. The problem is transformed to an appropriate classification problem with a couple of different approaches: the volatility approach and the duration approach. The analysis is implemented to the Bakken crude oil data and the aforementioned deterministic parameter is obtained for a wide range of data sets. With the implementation of this parameter in the refined model, the resulting model performs much better than the classical BN-S model., Comment: 27 pages, 9 figures. arXiv admin note: text overlap with arXiv:1911.13300

Finite-State Machines (FSMs) lie at the heart of every digital system and verifying whether a given circuit implementation (B) of an FSM (A) conforms to its specification is an important task in the design cycle. In this work, a deep neural network (DNN) based technique for testing FSMs is developed. Given a set of transition functions that specify an FSM, a DNN is trained with the input-output sequences using the back-propagation algorithm. First, the input sequences and the corresponding output sequences (I/O-pairs) for A are constructed, and some of them are utilized to train the DNN. After training, the proposed DNN is validated with the rest of the I/O-pairs. Once the training and validation of the DNN is completed, it can be used for checking the correctness of its implementation (B) very quickly. Some inputs are applied to B and the observed output sequences are compared with those predicted by the proposed DNN. Based on the similarities between them, B is either declared as correct implementation of A, else it is declared as faulty implementation. The experiments are performed on the MCNC FSM benchmarks and certain faults are injected to form mutant FSMs. Experimental results reveal the efficacy of the proposed technique. Only a few tests are required to detect the presence of anomaly, if any. Hence, the test time is very less resulting in an average test time reduction of 85.66% compared to existing method. It is observed from the earlier works that this type of DNN based FSM testing method is presented first time.

In this paper, we consider the portfolio optimization problem in a financial market under a general utility function. Empirical results suggest that if a significant market fluctuation occurs, invested wealth tends to have a notable change from its current value. We consider an incomplete stochastic volatility market model, that is driven by both a Brownian motion and a jump process. At first, we obtain a closed-form formula for an approximation to the optimal portfolio in a small-time horizon. This is obtained by finding the associated Hamilton-Jacobi-Bellman integro-differential equation and then approximating the value function by constructing appropriate super-solution and sub-solution. It is shown that the true value function can be obtained by sandwiching the constructed super-solution and sub-solution. We also prove the accuracy of the approximation formulas. Finally, we provide a procedure for generating a close-to-optimal portfolio for a finite time horizon.

This paper entails a novel approach of analysis of strategic market management based on renewal reward stochastic process. The paper has also pointed out a discovered fact that clearly infers realization of cost analysis of product revalidation in light of Brownian motion with drift. The paper indicates a rare and new concept of how can compound stochastic process be applied to sense business cost analysis. In demand–supply analysis, there lies the essence of realization of alternating renewal theory-based customer satisfaction. Furthermore, the paper also shows a novel analysis of product upgradation in light of conditional expectation and simple random walk. Facts related to recurrence relation, Abelian group and expectation indicate a non-conventional approach of business gain prediction.

Encoding of quantum information and carrying out computation on encoded state is an essential requirement for improving the reliability of a quantum computer. Resource limitation in today’s noisy intermediate scale quantum (NISQ) processors further restricts carrying out fault-tolerant quantum gate operations on such systems. Recent experiments conducted on physical qubits of superconducting transmon type and trapped atomic ions using the fault-tolerant scheme based on [[4, 2, 2]] code have shown a systematic improvement in the fidelity of all logical quantum gate operations except the logical controlled-NOT (CNOT) operation that requires 3 physical SWAP operations for fault-tolerant realization.In this present work we propose an optimal realization of logical CNOT operations on a single or two separate [[4, 2, 2]] code-words using 4 physical CNOT operations and an additional qubit. We further introduce logical two-qubit positive and negative controlled-phase operations with varying rotation angle, and also propose the fault-tolerant realization of logical 2-controlled-phase $(C^{2}Z)$ and 2-controlled-NOT (C2 NOT) operations that are required for universal computation using [[4, 2, 2]] encoding. The implementation requires less number of encoded operations and one additional qubit. Through experiments conducted on the 15-qubit IBM Quantum Experience processor and QASM simulator the fidelity and validity of all these proposed gate operations have been verified.

One major operation in neuromorphic computing is vector-matrix multiplication (VMM), which is required during training and inference phases, and is expensive in terms of power consumption and latency. Hardware accelerators using emerging technologies like memristor crossbars can be used to speed up the process. Various faults in the crossbar can introduce errors in VMM computation. Existing methods to handle faults using retraining and remapping incur overheads in terms of hardware, power and delay. In this paper the impact of faults on memristor-based crossbars are explored to analyze the overall accuracy of VMM operations. It has been observed that in presence of limited number of faults, the accuracy is not significantly affected. However, as the number of faults increases, the error in computation also increases. The proposed approach works in two phases, high-level fault detection and low-level fault detection. In the first phase, the percentage of stuck-at faults in the crossbar is identified, and if it lies below a threshold the second phase is skipped. In the second phase, an efficient method to identify the exact location of the faults is used. The approach required less number of read/write operations as compared to existing works in the literature.

In this paper, an approximate version of the Barndorff-Nielsen and Shephard model, driven by a Brownian motion and a L��vy subordinator, is formulated. The first-exit time of the log-return process for this model is analyzed. It is shown that with certain probability, the first-exit time process of the log-return is decomposable into the sum of the first exit time of the Brownian motion with drift, and the first exit time of a L��vy subordinator with drift. Subsequently, the probability density functions of the first exit time of some specific L��vy subordinators, connected to stationary, self-decomposable variance processes, are studied. Analytical expressions of the probability density function of the first-exit time of three such L��vy subordinators are obtained in terms of various special functions. The results are implemented to empirical S&P 500 dataset., 27 pages, 7 figures

During test mode, switching activity in scan-chain integrated circuits increase. As a result, the peak and average power dissipation in test mode often become higher than the normal mode. This can result in yield loss, heat damage to the circuit under test (CUT), and structural damage as well. In this paper, a new technique has been proposed that can efficiently reorder the test vectors targeting low switching activity in the scan chain. The technique has been verified with ISCAS’89 benchmark circuits. The achieved reduction in switching activity goes up to 12% when compared to the pattern order generated by an automatic test pattern generator (ATPG) tools like ATALANTA.

In this paper, we derive closed-form formulas for moments of the asset price in the Barndorff-Nielsen and Shephard (BN–S) stochastic volatility model. We also present similar results where the market is driven by a BN–S-type stochastic process. It is shown that in both cases the results depend on the cumulant transform of the background driving Levy process for the models. In this paper, we have also obtain various approximate expressions for the expected value of the square-root process for the shifted asset price with respect to the BN–S model.

Conventional pseudo-random testing in Built-InSelf-Test (BIST) usually requires a huge amount of testing time. This issue can be addressed with a Weighted Random Pattern generation that can produce test patterns in order to achieve high fault coverage with the fewer number of test vectors. Determining such input weights for a particular circuit is an NP-hard problem. In this paper, we have proposed a technique to converge to a high-quality input weight vector using a Particle Swarm Optimizer (PSO) with the help of a Deep Neural Network (DNN). The DNN prediction of fault coverage value as well as the parallel training of the DNN along with the evolution of the PSO makes this significantly fast. The technique has been tested with ISCAS'85 and ISCAS'89 benchmark circuits. The result shows that the DNN gets capable of predicting the fault coverage values accurately for weight assignments suggested by the particles in PSO. Also, it is observed that the proposed approach is very efficient in covering a large number of faults with less test vectors in self-testing circuits.

In this paper the Barndorff-Nielsen and Shephard (BN-S) model is implemented to find an optimal hedging strategy for the oil commodity from the Bakken, a new region of oil extraction that is benefiting from fracking technology. The model is analyzed in connection to the quadratic hedging problem and some related analytical results are developed. The results indicate that oil can be optimally hedged with the use of a combination of options and variance swaps. Theoretical results related to the variance process are established and implemented for the analysis of the variance swap. In this paper we also determined the optimal amount of the underlying oil commodity that has to be held for minimizing the hedging error. The model and analysis are used to numerically analyze hedging decisions for managing price risk in Bakken oil commodities. From the numerical results, a number of important features of the usefulness of the Barndorff-Nielsen and Shephard model are illustrated.

Rapid progress in technology scaling makes transistors smaller and faster over successive generations, and consequently core count in a system gets increased. However, transistor power consumption no longer scales commensurately. Increased power density calls for better thermal safety of the multi-core systems, in which a flexible and scalable packet-switched architecture — Network-on-Chip (NoC) — is commonly used for communication among the cores. This paper proposes a strategy to increase the thermal safety of NoC-based systems by a graceful decrease in communication cost and an Integer Linear Programming (ILP) formulation to deal with the problem. To overcome huge computational overhead of ILP, another solution strategy, based on meta-heuristic technique, Particle Swarm Optimization (PSO) is also proposed. Several innovative augmentations have been introduced into the basic PSO to generate better quality solutions. A thermal-aware mapping heuristic is proposed to generate some intelligent solutions, which become a part of the initial population in the PSO. A trade-off has been established between communication cost and peak temperature of the die. Experiments on Big data and Graph analytical workloads are reported. The results obtained are better than those of many contemporary approaches, reported in the literature.

Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT and NOR) is significantly higher than that using CMOS technology.

Cloud provides large shared resources where users (or foundations) can enjoy the facility of storing data or executing applications. In spite of gaining convenience of large resources, storing critical data in cloud is not secured. Hence, cloud security is an important issue to make cloud useful at the enterprise level. Data encryption is a primary solution for providing confidentiality to sensitive data. However, processing of encrypted data requires extra overhead, since repeated encryption-decryption need to be performed for every simple processing on encrypted data. Hence, direct processing on encrypted cloud data is advantageous, which is supported by homomorphic encryption schemes. Fully Homomorphic Encryption (FHE) provides a method of performing arbitrary operations directly on encrypted data. This seemingly magical idea is a welcome to cloud computing. However, there are several challenges to overcome for making the technology viable in practical applications. In this paper, we make an initial effort to highlight the problem of translating algorithms that can run on unencrypted or normal data to those which operate on encrypted data. Here, we show that although FHE provides the ability to perform arbitrary computations, its complete benefit can only be obtained if they also allow to execute arbitrary algorithms on encrypted data. In this pursuit, we provide techniques to translate basic operators (like bitwise, arithmetic and relational operators), which are used for implementation of algorithms in any high level language like C. Subsequently, we address decision making and loop handling and related data structures which are vital to realize when the controlling variables are encrypted. Since, termination is a major challenge while handling encrypted data, we propose a method of handling termination by message passing between server and client.

One of the main challenges in quantum computing is to ensure error-free operation of the basic quantum gates. There are various implementation technologies of quantum gates for which the distance between interacting qubits must be kept within a limit for reliable operation. This leads to the so-called requirement of neighborhood arrangements of the interacting qubits, often referred to as nearest neighbor (NN) constraint. This is typically achieved by inserting SWAP gates in the quantum circuits, where a SWAP gate between two qubits exchanges their states. Minimizing the number of SWAP gates to provide NN compliance is an important problem to solve. A number of approaches have been proposed in this regard, based on local and global ordering techniques. In this paper, a generalized approach for combined local and global ordering of qubits have been proposed that is based on an improved heuristic for cost estimation and is also scalable. The approach can be extended to ${N}$ -dimensional arrangement of qubits, for any arbitrary values of ${N}$ . Practical constraints, however, restrict the maximum value of ${N}$ to 3. Extensive experiments on benchmark functions have been carried out to evaluate the performance in terms of SWAP gate requirements. 3-D organization of qubits shows average reductions of 6.7% and 37.4%, respectively, in the number of SWAP gates over 2-D and 1-D organizations. Also compared to the best 2-D and 1-D results reported in the literature, on the average 8.7% and 8.4% reductions, respectively, are observed.

The main goal of this paper is to model variance and volatility swap using superposition of Barndorff-Nielsen and Shephard (BN-S) type models. In particular, in this paper we propose superposition of Levy process driven by Γ(ν,α) and Inverse Gaussian distributions. Model performance is assessed on data not used to build the model (i.e., test data). It is shown that the prediction error rate for the models considered in this paper are much lower compared to those from previous related models. Moreover, it is shown that unlike previous related models which are restricted to stable markets, the present approach can be applied to both stable and unstable markets.

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead. Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.

In this paper a couple of variance dependent instruments in the financial market are studied. Firstly, a number of aspects of the variance swap in connection to the Barndorff-Nielsen and Shephard model are studied. A partial integro-differential equation that describes the dynamics of the arbitrage-free price of the variance swap is formulated. Under appropriate assumptions for the first four cumulants of the driving subordinator, a Veceř-type theorem is proved. The bounds of the arbitrage-free variance swap price are also found. Finally, a price-weighted index modulated by market variance is introduced. The large-basket limit dynamics of the price index and the “error term” are derived. Empirical data driven numerical examples are provided in support of the proposed price index.

In this paper, we present the testing of four hypotheses on two streams of observations that are driven by L\'evy processes. This is applicable for sequential decision making on the state of two-sensor systems. In one case, each sensor receives or does not receive a signal obstructed by noise. In another, each sensor receives data-driven by L\'evy processes with large or small jumps. In either case, these give rise to four possibilities. Infinitesimal generators are presented and analyzed. Bounds for infinitesimal generators in terms of \emph{super-solutions} and \emph{sub-solutions} are computed. An application of this procedure for the stochastic model is also presented in relation to the financial market.

11This work is partially supported by the research project sponsored by the Synopsys Inc., USAWith the recent advancements of FPGA (Field Programmable Gate Array), circuits in AND-XOR plane gets its fair share of advantages due to the high testability feature of the AND-XOR networks and independence of the logic-gate area as well as delays on FPGA. Minimization of the product terms for such networks is an NP-hard problem. In this paper, we have proposed a Binary Particle Swarm Optimization (BPSO) based technique to solve the optimization problem accurately and accelerate the same using a Deep Neural Network. With the proposed technique, after testing it against various MCNC benchmark circuits, the results were very promising in terms of product terms, while utilizing significantly lesser CPU-time.

The identification of the memristor as fourth fundamental circuit element and, eventually, its fabrication in the HP labs provide new capabilities for in-memory computing. While there already exist sophisticated methods for realizing logic gates with memristors, mapping them to crossbar structures (which can easily be fabricated) still constitutes a challenging task. This is particularly the case since several (complementary) design objectives have to be satisfied, e.g. the design method has to be scalable, should yield designs requiring a low number of timesteps and utilized memristors, and a layout should result that is hardly skewed. However, all solutions proposed thus far only focus on one of these objectives and hardly address the other ones. Consequently, rather imperfect solutions are generated by state-of-the-art design methods for memristor-aided logic thus far. In this work, we propose a corresponding automatic design solution which addresses all these design objectives at once. To this end, a staircase structure is utilized which employs an almost square-like layout and remains perfectly scalable while, at the same time, keeps the number of timesteps and utilized memristors close to the minimum. Experimental evaluations confirm that the proposed approach indeed allows to satisfy all design objectives at once.

In this paper, improved reversible comparator designs are investigated using Multiple Control Toffoli(MCT) gates, improving Quantum Cost(QC) and also Nearest Neighbor Cost(NNC) metrics of circuits. The proposed designs are compared with recent works and found to be efficient in terms of cost by making these nearest neighbor compliant using Swap gate insertions.

In this paper, a new design to implement programmable Threshold Logic Gate (TLG) using memristors as weights combined with CMOS circuits for threshold control and comparison has been reported. In this design it is possible to program both weights and threshold of the gate that gives greater flexibility in implementing logic functions with minimum gate count. The operation of the gate has been experimentally verified through simulation by implementing some linear threshold logic functions.

A novel 3D memristive crossbar architecture and Boolean logic computation on it is explored in the paper. The two approaches for 2D crossbar mapping-Compact and Parallel mapping schemes-are extended along with inclusion of possible parallelism between gates and the pipelining between the different layers is explored. The proposed 3D crossbar mapping schemes are compared in terms of tsteps and crossbar size required, and is also compared with the existing works on 2D crossbars for illustrating the possible advantages of 3D crossbars.