599 results on '"Horiguchi, N."'
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102. The Complementary FET (CFET) for CMOS scaling beyond N3
103. An In-depth Study of High-Performing Strained Germanium Nanowires pFETs
104. Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology
105. Scalability comparison between raised- and embedded-SiGe source/drain structures for Si 0.55 Ge 0.45 implant free quantum well pFET
106. Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality
107. Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations
108. Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies.
109. Comprehensive study of Ga activation in Si, SiGe and Ge with 5 × 10−10 Ω·cm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation
110. Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes
111. Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
112. Use of high order precursors for manufacturing gate all around devices
113. CMOS Integration of Thermally Stable Diffusion and Gate Replacement (D&GR) High-k/Metal Gate Stacks in DRAM Periphery Transistors
114. Single and Double Diffusion Breaks in 14nm FinFET and Beyond
115. On the ballistic ratio in 14nm-Node FinFETs
116. Isolation of nanowires made on bulk wafers by ground plane doping
117. Erratum to Advances on Doping Strategies for Triple-Gate FinFETs and Lateral Gate-All-Around Nanowire FETs and Their Impact on Device Performance [MATSCI 62 (2017) 2–12]
118. Improving the low-frequency noise performance of input/output DRAM peripheral pMOSFETs
119. Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation
120. Advances on doping strategies for triple-gate finFETs and lateral gate-all-around nanowire FETs and their impact on device performance
121. Superior NBTI in High- $k$ SiGe Transistors–Part I: Experimental
122. Superior NBTI in High-k SiGe Transistors–Part II: Theory
123. Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal
124. Gate stack engineering to enhance high-κ/metal gate reliability for DRAM I/O applications
125. Latchup in bulk FinFET technology
126. Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS
127. Efficient physical defect model applied to PBTI in high-κ stacks
128. Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs
129. Mapping of CMOS FET degradation in bias space—Application to dram peripheral devices
130. Processing Technologies for Advanced Ge Devices
131. Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels
132. Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation
133. Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
134. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
135. Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?
136. Statistical model of the NBTI-induced threshold voltage, subthreshold swing, and transconductance degradations in advanced p-FinFETs
137. New understanding of dielectric breakdown in advanced FinFET devices — physical, electrical, statistical and multiphysics study
138. ESD diodes in a bulk Si gate-all-around vertically stacked horizontal nanowire technology
139. Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-κ Gate Stacks.
140. Performance Comparison of ${n}$ –Type Si Nanowires, Nanosheets, and FinFETs by MC Device Simulation.
141. Middle-of-line plasma dry etch challenges for CFET integration.
142. Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond
143. Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
144. Towards high performance sub-10nm finW bulk FinFET technology
145. Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass
146. Zero-thickness multi work function solutions for N7 bulk FinFETs
147. Complete extraction of defect bands responsible for instabilities in n and pFinFETs
148. Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation
149. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
150. Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole
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