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Summary: The main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost‐effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs. [ABSTRACT FROM AUTHOR]

At present, in the new hardware design work of deep learning, memristor as a non-volatile memory with computing power has become a research hotspot. The weights in the deep neural network are the floating-point number. Writing a floating-point value into a memristor will result in a loss of accuracy, and the writing process will take more time. The binarized neural network (BNN) binarizes the weights and activation values that were originally floating-point numbers to +1 and -1. This will greatly reduce the storage space consumption and time consumption of programming the resistance value of the memristor. Furthermore, this will help to simplify the programming of memristors in deep neural network circuits and speed up the inference process. This paper provides a complete solution for implementing memristive BNN. Furthermore, we improved the design of the memristor crossbar by converting the input feature map and kernel before performing the convolution operation that can ensure the sign of the input voltage of each port constant. Therefore, we do not need to determine the sign of the input voltage required by the port in advance which simplifies the process of inputting the feature map elements to each port of the crossbar in the form of voltage. At the same time, in order to ensure that the output of the current convolution layer can be directly used as the input of the next layer, we have added a corresponding processing circuit, which integrates batch-normalization and binarization operations. [ABSTRACT FROM AUTHOR]

In the agile hardware design methodology, a domain specific hardware description language is often used for RTL modeling. This novel situation brings new challenges for design verification. In order to support design verification techniques such as (bounded) model checking and equivalence checkings a symbolic simulator is designed and implemented for PyRTL and its intermediate representations. This paper introduces the design principle, conversion rules and other key technologies of our symbol simulator. The experimental results show the correctness of the implemented symbol simula-tor. [ABSTRACT FROM AUTHOR]

The first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a 1280 × 768 image resolution is achieved which is favorably faster in comparison with other work. [ABSTRACT FROM AUTHOR]

Hardware developers started experimenting with Scrum to accelerate their product development. However, it is not possible to implement Scrum in the same way as it was done for software systems, where the approach is already well established. One of the processes required in Scrum is the estimate of task efforts when creating a backlog for an Agile Sprint. This article presents a pilot validation experiment of a novel Agile framework for the development of hardware systems, including a parametric tool to estimate task effort in a more rigorous way than traditional confidence votes. This article presents the validation of electronic hardware design task estimation and overall project performance. The validation is performed through experimental work with teams of junior engineering students. The validation experiment showed an improvement from a minimum of eight to a maximum of eighteen percent when employing the presented tool during planning phases of the development. [ABSTRACT FROM AUTHOR]

This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high-Vth SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits and async routers to maximize energy efficiency. The neuron compute module achieves low power via an area efficient ALU implementation by using only adder and bitshifter circuits. We describe this LIF neuron model ALU design, and also include key neurocore verification scenarios (i.e., router deadlocks and functional coverage), CPU-neurocore control flow, and asynchronous router performance analysis. Our 16-core fabricated chip in 40 nm CMOS process works down to 0.5V. The measured leakage and average energy efficiency are 0.93 μW/core and 4.8 pJ/SOP respectively (at 0.5V), which is 20% better than state of the art. [ABSTRACT FROM AUTHOR]

3D-HEVC is the state-of-the-art standard to compress three-dimensional videos. One of the 3D-HEVC novel tools is the DIS tool, which is used to efficiently compress smooth and homogeneous areas of depth maps by using four different prediction modes. The decision of which DIS mode will be used is done through the SVDC similarity criterion in the DIS original definition. This article proposes the substitution of the complex SVDC criterion for simpler and more hardware friendly criteria as SATD, SSE, and SAD. These alternative criteria were evaluated in terms of encoding efficiency and hardware impacts in comparison with the SVDC. Dedicated DIS hardware were designed using each one of each criterion and these designs were described in VHDL and synthesized for TSMC 40 nm. The best results were found with SAD criteria, with losses of only 0.2% in coding efficiency and with expressive gains of more than 50 times in power and more than 35 times in area, when compared with SVDC. The reached results showed that the use of a simpler similarity criterion is an important alternative to be used in DIS tool, mainly if an efficient hardware design is required. [ABSTRACT FROM AUTHOR]

Both turbo Hadamard codes and concatenated zigzag Hadamard codes are ultimate-Shannonlimit-approaching channel codes. The former one requires the use of Bahl-Cocke-Jelinek-Raviv (BCJR) in the iterative decoding process, making the decoder structure more complex and limiting its throughput. The latter one, however, does not involve BCJR decoding. Hence its decoder structure can be much simpler and can potentially operate at a much higher throughput. In this paper, we investigate the hardware design of a concatenated zigzag Hadamard encoder/decoder system and implement it onto an FPGA board. We design a decoder capable of decoding multiple codewords at the same time, and the proposed system can operate with a throughput of 1.44 Gbps - an increase of 50% compared with the turbo Hadamard encoder/decoder system. As for the error performance, the encoder/decoder system with a 6-bit quantization achieves a bit error rate of 2 × 10-5 at Eb/N0 = -0.2 dB.

With the recent advances in quantum computing, code-based cryptography is foreseen to be one of the few mathematical solutions to design quantum resistant public-key cryptosystems. The binary polynomial multiplication dominates the computational time of the primitives in such cryptosystems, thus the design of efficient multipliers is crucial to optimize the performance of post-quantum public-key cryptographic solutions. This manuscript presents a flexible template architecture for the hardware implementation of large binary polynomial multipliers. The architecture combines the iterative application of the Karatsuba algorithm, to minimize the number of required partial products, with the Comba algorithm, used to optimize the schedule of their computations. In particular, the proposed multiplier architecture supports operands in the order of dozens of thousands of bits, and it offers a wide range of performance-resources trade-offs that is made independent from the size of the input operands. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt public-key cryptosystem as representative use cases for large-degree binary polynomial multiplications. For each configuration we showed that our template architecture can deliver a performance-optimized multiplier implementation for each FPGA of the Xilinx Artix-7 mid-range family. The experimental validation performed by implementing our multiplier for all the LEDAcrypt configurations on the Artix-7 12 and 200 FPGAs, i.e., the smallest and the largest devices of the Artix-7 family, demonstrated an average performance gain of 3.6x and 33.3x with respect to an optimized software implementation employing the gf2x C library.

Abstract This paper describes a vacuum suction-type end effector for depalletizing robots in distribution centers. The developed end effector has multiple suction pad units to which a bellows pneumatic actuator is applied as the support mechanism. Load-bearing capacity is improved due to a high-strength wire provided inside the bellows, and the contraction force is improved due to ring members placed inside of the ridges of the rubber bellows. The developed end effector is attached to the arm of a linear motion-type depalletizing robot, and its real-world performance is verified. Verification results confirm that the suction pad units tolerate cardboard box inclination and differences in box height by a simple lowering motion of the arm, and multiple cardboard boxes can be simultaneously unloaded. Moreover, as compared with conventional end effectors, the developed end effector achieves large expansion and contraction in a thin structure. The developed end effector is expected to broaden applications for depalletizing robots.

One of the commonly-used feature extraction algorithms in computer vision is the histogram of oriented gradients. Extracting the features from an image using this algorithm requires a large amount of computations. One way to boost the speed is to implement this algorithm on field programmable gate arrays, to benefit from flexible designs such as parallel computing. In this paper, we first, provide a summary of the steps of the histogram of oriented gradients algorithm. We then survey the implementation techniques of the histogram of oriented gradients on field-programmable gate arrays in the past decade. We group the different techniques into four main categories and analyze various enhancement methods in each category. The first group is the optimization of the algorithm computation which involves the steps of input selection, magnitude calculation, orientation and bin assignment, and normalization. The second category is data manipulation techniques which include numerical representation, data flow modification, and memory optimization. The third group contains modified features based on the histogram of oriented gradients and their hardware implementation, and the fourth one is the implementations in hardware-software co-design of the algorithm. We compare the different implementations using a speed metric called pixels per clock cycle, and resource utilization. Finally, we provide design summary tables for efficient implementation with respect to the speed metric, accuracy, and resource utilization.

An application specific integrated design using Quadrature Linear Discriminant Analysis is proposed for automatic detection of normal and epilepsy seizure signals from EEG recordings in epilepsy patients. Five statistical parameters are extracted to form the feature vector for training of the classifier. The statistical parameters are Standardised Moment, Co-efficient of Variance, Range, Root Mean Square Value and Energy. The Intellectual Property Core performs the process of filtering, segmentation, extraction of statistical features and classification of epilepsy seizure and normal signals. The design is implemented in Zynq 7000 Zc706 SoC with average accuracy of 99%, Specificity of 100%, F1 score of 0.99, Sensitivity of 98% and Precision of 100 % with error rate of 0.0013/hr., which is approximately zero false detection.

Aiming to expand the range of applications for parallel grippers, we propose an extension nail mechanism that can be mounted on a parallel gripper. We also propose an extension nail mechanism comprising a stainless steel belt, two transport belts, a triangular nail, and a drive unit. The triangular nail is connected to one end of the stainless steel belt, and the drive unit is connected near the other end. We achieve smooth sliding of the nails underneath objects by arranging the transport belts on either side of the stainless steel belt. By elastically winding one end of the stainless steel belt and each of the transport belts, the nail mechanism can be miniaturized while achieving large expansion and contraction. We achieve stable grasping operations by using the extension nail mechanism of the parallel gripper in accordance with the flexibility of the object. [ABSTRACT FROM AUTHOR]

SAR (Synthetic Aperture Radar), or synthetic aperture radar, is an active earth observation system. In recent years, SAR has gradually developed towards multi-platform, and has appeared on small mobile platforms such as unmanned aerial vehicles and probe vehicles. SAR imaging is an imaging program running on SAR. Due to the emergence of a new special operating environment, it has stricter requirements for low energy consumption and high computing power. How to provide high-performance, low-power application support for a specific platform has become a core point. This paper analyzes the characteristics of SAR imaging calculation and memory access, and specifically optimizes the program and tests the performance of the program on the x86 platform to obtain a reliable performance reference. On this basis, oriented to the hardware structure of the DSP + FFT accelerator, a mathematical model of computing power ratio is constructed to provide a solution for hardware design. [ABSTRACT FROM AUTHOR]

The real-time simulation of modular multilevel converter (MMC) is essential to the evaluation and validation of its control and protection systems. Moreover, the dynamics at both sub-module level and system level are expected from the real-time simulations of MMCs. To achieve this objective, this paper proposes the shifted phasor modeling (SPM) of the MMC by representing each sub-module with a Thevenin equivalent circuit that is derived using shifted phasors with improved accuracy. The efficiency of the SPM is guaranteed by modeling each arm as a switch-dependent Thevenin equivalent circuit. The computational burden remains almost unchanged even when the number of sub-modules increases considerably. The proposed model is materialized using field programmable gate array. And, thus the real-time simulation of MMC-based DC grids can be realized to capture the dynamics at the system level as well as the sub-module level. The effectiveness of this paper has been validated in terms of both accuracy and efficiency on a two-terminal MMC-based low-voltage direct current system.

Human detection, identification, and monitoring are essential for many applications aiming to make smarter the indoor environments, where most people spend much of their time (like home, office, transportation, or public spaces). The capacitive sensors can meet stringent privacy, power, cost, and unobtrusiveness requirements, they do not rely on wearables or specific human interactions, but they may need significant on-board data processing to increase their performance. We comparatively analyze in terms of overall processing time and energy several data processing implementations of multilayer perceptron neural networks (NNs) on board capacitive sensors. The NN architecture, optimized using augmented experimental data, consists of six 17-bit inputs, two hidden layers with eight neurons each, and one four-bit output. For the software (SW) NN implementation, we use two STMicroelectronics STM32low-power ARM microcontrollers (MCUs): one MCU optimized for power and one for performance. For hardware (HW) implementations, we use four ultralow-power field-programmable gate arrays (FPGAs), with different sizes, dedicated computation blocks, and data communication interfaces (one FPGA from the Lattice iCE40 family and three FPGAs from the Microsemi IGLOO family). Our shortest SW implementation latency is 54.4 μs and the lowest energy per inference is 990 nJ, while the shortest HW implementation latency is 1.99 μs and the lowest energy is 39 nJ (including the data transfer between MCU and FPGA). The FPGAs active power ranges between 6.24 and 34.7 mW, while their static power is between 79 and 277 μW. They compare very favorably with the static power consumption of Xilinx and Altera low-power device families, which is around 40 mW. The experimental results show that NN inferences offloaded to external FPGAs have lower latency and energy than SW ones (even when using HW multipliers), and the FPGAs with dedicated computational blocks (multiply-accumulate) perform best.

Copyright of Journal of Henan University of Science & Technology, Natural Science is the property of Editorial Office of Journal of Henan University of Science & Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Compared to traditional hardware development methodologies, high-level synthesis (HLS) offers a faster time-to-market and lower design-cost at the expense of implementation efficiency. Although HLS tools are becoming popular in some applications, such as digital signal processing and neural network classification, their usability on cryptographic applications is largely unexplored. This feasibility is critical especially for cryptosystems that are under development, such as the next-generation public-key cryptosystems needed for quantum-resistance. This letter provides a thorough investigation of HLS on number theoretic transform (NTT)—the core arithmetic function of lattice-based quantum-resistant cryptosystems. We demonstrate a fast yet extensive design space exploration of NTT through the Vivado HLS tool, analyze the shortcomings/challenges of optimized configurations, and quantitatively compare the results to software-based and hand-coded hardware designs. [ABSTRACT FROM AUTHOR]

We propose a robotic finger with an exoskeleton-type structure that bends and extends by the deformation force of flat tubes. Our objective is to realize a disposable robot hand for gripping unsanitary objects. To reduce the cost of disposing of the robotic finger, a commercially available cable carrier chain was used for the exoskeleton component, and the flat tubes used in the pneumatic actuator were prepared by thermal processing of a commercially available tube. The driving joint of the robotic finger consists of a hollow link mechanism and two flat tubes, which are respectively arranged inside the hollow link mechanism and at the joint boundary. The proposed joint structure achieves both smooth drivability and good load-bearing capacity. The developed robotic finger weighs approximately 85 g and generates a fingertip force of approximately 4 N when a pressure of 0.25 MPa is applied. Because the developed robotic finger is pneumatically driven, it conforms to the object shape and is compliant to external force. Verification of the mechanism demonstrated that the developed robotic finger is useful because it was able to grasp six types of assumed objects. [ABSTRACT FROM AUTHOR]

For several years, high development and production costs of humanoid robots restricted researchers interested in working in the field. To overcome this problem, several research groups have opted to work with simulated or smaller robots, whose acquisition costs are significantly lower. However, due to scale differences and imperfect simulation replicability, results may not be directly reproducible on real, adult-sized robots. In this paper, we present the NimbRo-OP2X, a capable and affordable adult-sized humanoid platform aiming to significantly lower the entry barrier for humanoid robot research. With a height of 135 cm and weight of only 19 kg, the robot can interact in an unmodified, human environment without special safety equipment. Modularity in hardware and software allows this platform enough flexibility to operate in different scenarios and applications with minimal effort. The robot is equipped with an on-board computer with GPU, which enables the implementation of state-of-the-art approaches for object detection and human perception demanded by areas such as manipulation and human–robot interaction. Finally, the capabilities of the NimbRo-OP2X, especially in terms of locomotion stability and visual perception, are evaluated. This includes the performance at RoboCup 2018, where NimbRo-OP2X won all possible awards in the AdultSize class. [ABSTRACT FROM AUTHOR]

Copyright of Ordnance Industry Automation is the property of Editorial Board for Ordnance Industry Automation and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A digital microfluidic biochip (DMB) is an attractive platform for automating laboratory procedures in microbiology. To overcome the problem of cross-contamination due to fouling of the electrode surface in traditional DMBs, a contactless liquid-handling biochip technology, referred to as acoustofluidics, has recently been proposed. A major challenge in operating this platform is the need for a control signal of frequency 24 MHz and voltage range ± 10/± 20 V to activate the IDT units in the biochip. In this paper, we present a hardware design that can efficiently activate/de-activated each IDT, and can fully automate an bio-protocol. We also present a fault-tolerant synthesis technique that allows us to automatically map biomolecular protocols to acoustofluidic biochips. We develop and experimentally validate a velocity model, and use it to guide co-optimization for operation scheduling, module placement, and droplet routing in the presence of IDT faults. Simulation results demonstrate the effectiveness of the proposed synthesis method. Our results are expected to open new research directions on design automation of digital acoustofluidic biochips. [ABSTRACT FROM AUTHOR]

In a Eukaryotic gene, identification of exon regions is crucial for protein formation. The periodic‐3 property of exon regions has been used for its identification. An anti‐notch infinite impulse response (IIR) filter is mostly employed to recognise this periodic‐3 property. The lattice structure realisation of anti‐notch IIR filter requires less hardware over direct from‐II structures. In this study, a hardware implementation of IIR anti‐notch filter lattice structure is carried out on Zynq‐series (Zybo board) field programmable gate array (FPGA). The performance of hardware design has been improved using techniques like retiming, pipelining and unfolding and finally assessed on various Eukaryotic genes. The hardware implementation reduces the time frame to analyse the DNA sequence of Eukaryotic genes for protein formation, which plays a significant role in detecting individual diseases from genetic reports. Here, the performance evaluation is carried out in MATLAB simulation environment and the results are found similar. Application‐specific integrated circuit (ASIC) implementation of the anti‐notch filter lattice structure is also carried out on CADENCE‐RTL compiler. It is observed that the FPGA implementation is 31 to 34 times faster and ASIC implementation is 58 to 64 times faster compared to the results generated by MATLAB platform with similar prediction accuracy. [ABSTRACT FROM AUTHOR]

This brief presents the Six Wedgelets and six Refinements (6WR), a hardware friendly algorithm targeting the Depth Modeling Mode 1 (DMM-1) encoding tool of the 3D-High Efficiency Video Coding (3D-HEVC) standard. This brief also presents the high-throughput and energy-aware hardware design for the 6WR. The 6WR algorithm reduces 98.5% of the evaluated wedge lets by exploring the edges gradients, with average coding efficiency losses between 1.2% and 2.8%. The hardware design implements the Bresenham algorithm to avoid the use of memory. The synthesis results show that the 6WR architecture can process up to nine views in 3D full HD 1080p videos at 30 frames per second, with a power dissipation of 263.7 mW. When compared with related works, the 6WR architecture reached the highest throughput and the best results of coding efficiency and energy efficiency when the same target throughput is considered. [ABSTRACT FROM AUTHOR]

We introduce the strictly in-order core (SIC), a timing-predictable pipelined processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC's key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC's timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order pipelined processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Fuzhou University is the property of Journal of Fuzhou University, Editorial Department and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

We describe six common misconceptions about platform studies, a family of approaches to digital media focused on the underlying computer systems that support creative work. We respond to these and clarify the platform studies concept.

The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system’s implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications’ meeting their other requirements.

The wideband radar intermediate frequency direct acquisition module is used to acquire, process and transmit data, which is an important part of radar system. Based on the current advanced Virtex-7 FPGA board and high-speed ADC card, this article designs the module from two aspects of hardware design and hardware development, including structure design, data flow design, and FPGA top-level design. Then the article researches on some key technologies involved, including JESD204B protocol configuration, data flow transmission, DDR3 buffer design and clock optimisation. Practice has proved that the design of this article can accomplish the task well in practical engineering.