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A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with good scalability, a small area, and high performance using vertical through-silicon vias (TSV). However, the failure rate of TSV, which is higher than that of horizontal links, causes unpredictable topology variations and requires adaptive routing algorithms to select the available paths dynamically. Most works have aimed at the congestion control for TSV partially 3D NoCs to bypass the TSV reliability issue, while others have focused on the fault tolerance in TSV fully connected 3D NoCs and ignored the performance degradation. In order to adequately improve reliability and performance in TSV fully connected 3D NoC architectures, we propose a TSV-aware Reinforcement Learning Assisted Routing Algorithm (RLARA) for fault-tolerant 3D NoCs. The proposed method can take advantage of both the high throughput of fully connected TSVs and the cost-effective fault tolerance of partially connected TSVs using periodically updated TSV-aware Q table of reinforcement learning. RLARA makes the distributed routing decision with the lowest TSV utilization to avoid the overheating of the TSVs and mitigate the reliability problem. Furthermore, the K-means clustering algorithm is further adopted to compress the routing table of RLARA by exploiting the routing information similarity. To alleviate the inherent deadlock issue of adaptive routing algorithms, the link Q-value from reinforcement learning is combined with the router status based in buffer utilization to predict the congestion and enable RLARA to perform best even under a high traffic load. The experimental results of the ablation study on simulator Garnet 2.0 verify the effectiveness of our proposed RLARA under different fault models, which can perform better than the latest 3D NoC routing algorithms, with up to a 9.04% lower average delay and 8.58% higher successful delivered rate. [ABSTRACT FROM AUTHOR]

Summary: Digital twin network (DTN) is a foremost enabler for efficient optimization in modern networks, as it owns massive real‐time data and requires interaction with the physical network in real‐time. When constructing a DTN, it is necessary to deploy many servers in the physical network for digital models' storage, calculation, and communication. Evolutionary algorithms show outstanding global optimization capabilities compared to the constructive heuristic method in such an optimization problem. However, due to the high dimensionality of the problem and the complicated evaluation of the deployment plan, evolutionary algorithms easily fall into the optimum local at a high computational cost, given that the server placement problem is an NP‐hard combinatorial optimization problem. In this research, we propose an evolutionary framework for server layout optimization that significantly improves the optimization efficiency of evolutionary algorithms and reduces the algorithm's computational cost. An offline‐learning‐based approach is used to reduce the search space, and a self‐examining guided local search method is proposed to improve the search efficiency. Additionally, a look‐up table‐based hybrid approach is used for solution evaluation, reducing computational overhead. Experimental results show that the proposed framework and optimization strategy can significantly improve the evolutionary algorithm search efficiency and achieve excellent convergence performance. [ABSTRACT FROM AUTHOR]