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[ABSTRACT] This work is part of the Information Infrastructure initiative in Telefónica I+D. The initiative focuses on offering support to all the users and corporative services inside the Company, from provisioning both physical and virtual machines, necessary software, required configurations, Sharepoint platforms, mail, storage space, VPN, etc. The main goal of this project will be the study and configuration of a platform to manage all hardware, from servers to Telefónica I+D clients. System Center Configuration Manager 2012 R2 is a Microsoft software that manages that handles the centralized management of both physical and virtual machines. It proposes functionalities for the administration of all operating systems, specially focused on Windows machines. Nowadays, there are many centralized management systems, but for Windows, our main client, is the most compatible and most complete for administration. This software offers many options, like dividing the teams or users into collections so a controlled deployment can be done, distributing updates, applications, OSs and configurations for both PC and servers, reports about the deployments and the incidents, and inventory for both hardware and software, among many others. Once the platform is up and running, it is expected to reduce the resources in the administration of all the hardware of the Company., Este trabajo se enmarca dentro de la iniciativa de infraestructura de la información en la empresa de Telefónica I+D. La iniciativa se centra en dar soporte a todos los usuarios y servicios corporativos dentro de la empresa, desde el aprovisionamiento de máquinas tanto físicas como virtuales, software necesario, configuraciones requeridas, plataforma de Sharepoint, correo, espacio de almacenamiento, VPN, etc. El principal objetivo del proyecto será el estudio y configuración de una plataforma para la gestión centralizada de todos los equipos, tanto servidores como clientes de Telefónica I+D. System Center Configuration Manager 2012 R2, es un software de Microsoft que se encarga de la gestión centralizada de todos los equipos tanto físicos como virtuales. Propone funcionalidades para la administración de todos los sistemas operativos, pero sobre todo se centra en sistemas Windows. En la actualidad existen sistemas de gestión centralizada pero para Windows, que es nuestro principal cliente, es el más compatible y con más funciones para dicha administración. Dispone de muchas funciones, ahora como dividir los equipos o usuarios en colecciones para luego tener un despliegue controlado, distribución de actualizaciones, aplicaciones, sistemas operativos y configuraciones de equipo o servidor, informes detallado de los despliegues e incidencias, inventario tanto de hardware como de software, entre muchas otras cosas. [RESUMEN] Una vez que la plataforma esté operativa y funcionando, lo esperado es reducir recursos en la administración de todos los equipos de la empresa

The increase in the demand for wireless communications from the user-end point of view calls for an infrastructure that is constantly more capable, reliable and efficient. One of the critical nodes in the telecommunications process, from the hardware perspective, is the power amplifier (PA): it is not only the more powerconsuming device in the transmission chain but it also has a highly nonlinear behaviour which can compromise the well-functioning of the communications infrastructure. This thesis addresses the digital predistortion (DPD) technique, whose goal is to reduce the nonlinear influence of the PA in the transmitted signal, and enhances it with two contributions which can allow for a bigger computational and economic efficiency without compromising the effectiveness of DPD. These contributions are the Reduced Observational Bandwidth and the Reduced Model Order. In the former, the observational path required for the implementation of the DPD is redesigned to permit the capture of wideband signals using multiple reduced bandwidth observations. The latter, on the other hand, aims at reducing the number of coefficients needed for DPD by discarding the less contributive modes of the PA behavioural model. Additionally, the technique of reducing the signal PAPR is applied in order to seek a more effective predistortion. The experimental campaign in a real DUT proved that the reduction of the observational bandwidth was feasible and produced similar results when compared to a full spectrum observation.

In this paper, a dual-band outphasing transmitter (able of operating either at 770 MHz or 960 MHz frequency bands) is presented. Two broadband RF power amplifiers (PAs) have been designed over packaged GaN HEMT devices, switching close to the nominal zero-voltage and zerovoltage-derivative class E conditions. A reactive combiner, using transmission lines of appropriate electrical lengths at both bands, together with compensating reactances, allows positioning the drain impedance loci to produce high efficiency and good dynamic range profiles. Average drain efficiency figures over 68% and 38% have been measured for WCDMA signals with a peak-to-average power ratio (PAPR) of 5.1 dB and 8.4 dB, respectively., Peer Reviewed, Postprint (published version)

This paper evaluates the linearity performance in a wideband wireless backhaul transmitter when applying crest factor reduction (CFR) and digital predistortion (DPD) techniques to enhance the transmitted output power, and thus the power efficiency of the overall system, while fulfilling the communications system quality requirements and regulations. The CFR technique applied is the peak cancellation (PC), while the linearizer is based in an adaptive DPD with memory effects compensation. Order reduction techniques are also applied to mitigate the complexity of the DPD structure. The power amplifier is based in a 15 Watts GaN transistor. The test signal follows a multiband 4 channel 1024-QAM configuration (reaching up to 1 Gbps) with 12 dB of PAPR at RF and 112 MHz bandwidth (28 MHz each channel). A testbed for evaluating the PC and DPD linearization performance of the RF subsystem was deployed and experimental results are presented in this paper., Postprint (published version)

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This paper presents a new kind of behavioral model structure for characterizing static nonlinearities in dynamically supplied RF power amplifiers. The proposed architecture is based on the combination of several basic cells and it is focused to simplify the real-time design and implementation of adaptive shaping functions devoted to improve the efficiency in systems controlled by digital signal processors with tight computational capabilities, such is the case of handsets and small-cells., Peer Reviewed, Postprint (published version)

Nowadays, the Unmanned Aerial Vehicle (UAV) become more and more popular in aerial photography, especially in mini and micro size UAV. The UAV used for aerial photography usually use a high power video transfer communication block to send the real time video signal to the ground station, which is high power consuming. It is important to increase the power efficiency of on-board communication system for improving the endurance of small-scale UAVs. The power amplifier (PA) is the most power consuming component among all the units in communication system. Given the nature feature of the PA, it tends to be either linear response or higher power efficiency, but rarely both. The PA with high power efficiency always has a horrible non-linear distortion performance that discards its use. There are several available linearization methods to compensate the non-linear behavior of PA. Among them the digital predistortion (DPD) method is widely used with the development of digital electronic technology. However, the design cost of DPD block itself should be taken into consideration. The DPD linearizer requires a feedback path to monitor the PA behavior and the analog to digital convertor (ADC) is a critical component from the cost and efficiency point of view. The price of ADC makes a prominently contribution to the total cost of DPD linearizer. The price of the ADC is usually proportional to the sampling frequency, which, according to the Nyquist-Shannon sampling theorem, should be higher than twice the bandwidth of the communication's signal. In this thesis, we will present an under sampling method and its supporting algorithm aimed to decrease the frequency rate requirements of the ADC to perform the DPD linearization. In this way, ADC with lower sampling frequency is able to be used in the DPD feedback loop and thus decrease the total cost without compromising the linearization performance. The theoretical analysis will be first presented in this thesis and then experimental

The PA is one of the most important subsystems of the RF transmitter and it is responsible of the main part of the overall transmitter's power consumption. In order to increase the efficiency of the PA, this project proposes designing in a FPGA adaptive filtering techniques to update the coefficient of digital predistortion linearizers. More precisely, the least squares (LS) algorithm is design to be implemented in soft-core processor as the Xilinx MicroBlaze, while the least mean squares (LMS) algorithm is design for real-time operation in the FPGA. The experimental results obtained show a promising performance of the multi look-up table (M-LUT) based digital predistorter (DPD). Good linearity levels are reported. However, an exhaustive study on the required arithmetic resolution has yet to be carried out in order to mitigate the quantization noise and lead to a higher performance of the DPD using these kind of quadratic minimization algorithms.

Los objetivos principales en este proyecto son los análisis matemáticos y prácticos de diferentes generadores de variables Rayleigh, estimadores de canal y estrategias para su implementación de una manera reconfigurable a través de Simulink y FPGA. La diferentes técnicas para generar variables Rayleigh usadas en este proyecto son las siguientes: la suma de sinusoides, la técnica de Smith y el método de Bealieu-Young. El primero se base en la suma de exponenciales complejas mientras los otros dos se basan en la IDFT. De todos estos métodos vemos que el método de Bealieu-Young tiene la mínima complejidad para la misma precisión que los otros métodos. En consecuencia ha sido el escogido para ser implementado en la FPGA Cuando hablamos de estimadores de canal se han considerado dos enfoques diferentes. El primero consiste en introducir los pilotos de manera uniforme a lo largo de la trama, mientras el otro introduce los pilotos al principio de la trama. A la hora de estimar la trama dos estrategias han sido analizadas: el estimador de canal promedio y el estimador de canal por interpolación lineal. La técnica de promediado se puede considerar como un filtro paso bajo. En este caso el estimador por promediado es capaz de eliminar la frecuencias altas que son introducidas por el ruido. Por el contrario el estimador por interpolación lineal, ofrece los mejores resultados cuando el ruido es bajo. En ambos casos hemos calculado la potencia de error en el proceso de estimación. Los resultados prácticos y teóricos obtenidos a través de Matlab y Simulink concuerdan a la perfección. En un escenario co-simulado la FPGA trabaja con Matlab. Los resultados nos dicen que el sistema se ve limitado por el cable que conecta ambos sistemas. Por lo que es crucial para aprovechar al máximo la potencia de la FPGA que el sistema si integre por completo dentro de la FPGA y si no es posible usar conexiones de alta velocidad. English: The main goals of this project are the study from a mathemat

L’amplificador de potència (PA) és l’element de la cadena de transmissió d‘un sistema de comunicacions responsable de dotar al se nyal del nivell de potència necessari abans d’enviar-lo al canal ràdio, i a la vegada el més crític en termes de linealitat i eficiència energètica. Per aquest motiu, un dels objectius centrals de la investigació en el camp de la radiofreqüència és la linealització i la millora en l’eficiència d’aquests dispositius, que són responsables de la major part del consum en els sis temes de transmissió sense fils. Existeixen diverses tècniques de linealització orientades a garantir la linealitat dels amplificadors de potència, la més utilitzada de les quals és la Predistorsió Digital. D’altra banda, de cara a maximitzar l’eficiència de l’etapa d’amplificació s’han proposat diverses arquitectures d’amplificació eficient. Les més utilitzades actualment són les estructures LINC, Doherty i alimentació dinàmica per seguiment d’envoltant (ET). Finalment, per poder transmetre de forma concurrent en dos bandes freqüencials (transmissormulti-estàndard) diferents utilitzant un mateix front-end (sense necessitat d’utilitzar més d’un PA) cal dissenyar amplificadors Dual-Band (DB) optimitzats per aquestes bandes. Aquest projecte té com a objectiu contribuir en la linealització d’amplificadors de potència Dual-Band alimentats de forma dinàmica, és a dir amb ET. Així doncs, en aquest projecte es presentaran models de comportament polinòmics tridimensionals amb memòria (3D-MP) capa ços de modelar i posteriorment linealitzar el comportament no lineal i la dinàmica d’amplificadors de potència DB amb ET. Al llarg del projecte es presentaran diferents models del PA i s’avaluaran les seves prestacions amb diferents configuracions, justificant la necessitat d’aplicar models 3D-MP envers configuracions que no tenen en consideració tots els efectes inherents al PA Dual-Band alimentat amb ET. Posteriorment, es seleccionaran els millors models i es realitzarà un estudi s

This paper presents and discusses two possible real-time digital predistortion (DPD) architectures suitable for envelope tracking (ET) power amplifiers (PAs) oriented at a final computationally efficient implementation in a field programmable gate array (FPGA) device. In ET systems, by using a shaping function is possible to modulate the supply voltage according to different criteria. One possibility is to use slower versions of the original RF signal’s envelope in order to relax the slew-rate (SR) and bandwidth (BW) requirements of the envelope amplifier (EA) or drain modulator. The nonlinear distortion that arises when performing ET with a supply voltage signal that follows both the original and the slow envelope will be presented, as well as the DPD function capable of compensating for these unwanted effects. Finally, two different approaches for efficiently implementing the DPD functions, a polynomial-based and a look-up table-based, will be discussed., Peer Reviewed, Postprint (published version)

This article discusses several different implementations of Volterra seriesmodels, and performs a fair comparison between them using measured data and well known figures of merit. Among the implemented models, an approach that uses sub-sampling techniques together with Volterra series in a parallel cascade structure shows an improved performance compared to the other variations of Volterra seriesmodels.Based on the results, new trends in RF power amplifier behavioral modeling are suggested., Peer Reviewed, Postprint (published version)

This paper presents how to apply order reduction in wide-band digital predistortion (DPD) linearizers using the principal component analysis (PCA) technique. This method is tested in a wireless backhauling transmitter where four 28 MHz adjacent subcarrier transmission of M-QAM signals are considered. The DPD has to counteract not only the PA nonlinear behavior, but also its dynamics. This may results critical when considering wideband signals since the number of coefficients required to model memory effects can grow dramatically. By applying the PCA technique, the number of essential parameters can be significantly reduced. In addition, a strategy to minimize the computational cost of finding the optimal coefficients is also presented. A test-bed for evaluating the DPD linearization performance of the RF subsystem when PCA is applied was deployed and experimental results are presented in this paper, Peer Reviewed, Postprint (published version)

This paper proposes a novel three-dimensional digital predistorter (3D-DPD) suitable for compensating nonlinear distortion in dual-band (DB) envelope tracking (ET) power amplifiers (PAs). By taking into account the cross-band modulation effects (due to DB operation) and the slow-envelope dependent distortion effects (due to ET), the 3D-DPD is design by properly modifying the memory polynomial (MP) behavioral model. In a first approach, the accuracy and reliability of the proposed 3D-MP model are evaluated. Finally, experimental results are shown to validate the linearization performance of the proposed 3D-DPD., Peer Reviewed, Postprint (published version)

This paper presents a study on the trade-off between the envelope’s slew-rate and the drain efficiency when slower envelopes are considered to dynamically supply the power amplifier (PA). This paper discusses a method to limit the slew-rate (and consequently the bandwidth) of the signal’s envelope. Moreover, since the envelope tracking (ET) technique using a slower version of the original envelope introduces nonlinear distortion, slow envelope dependent predistortion has to be also incorporated in the design of ET PAs. Experimental results showed that it is possible to find a compromise between the bandwidth and slew-rate reduction (necessary to cope with the specific envelope amplifier requirements) and the amount of drain efficiency degradation suffered due to the use of a slower version of the original envelope., Peer Reviewed, Postprint (published version)

This paper presents an envelope tracking (ET) Power Amplifier (PA) whose architecture includes an efficient Envelope Amplifier (EA) and a bandwidth reduction algorithm suitable for real time applications. The EA consists of a hybrid amplifier combining switched and linear amplification. A band- width and slew-rate reduction algorithm has been incorporated in order to allow wide-band envelope amplifications. Non-linearities introduced by the Hybrid EA (HEA) and the dynamic supply are compensated with Digital Pre-Distortion. The ET PA has been tested using 64-QAM signals and commercial devices. Results show that non-linearities produced by the HEA are compens- able and that the architecture provides efficiency improvements compared to the conventional linear EA., Peer Reviewed, Postprint (published version)

A Doherty power amplifier (DPA) is an effective structure born in 1936 which, after a scarce revival around year 2000), had been strengthened from 2005 because its capability to combine linear amplification with power efficiency. Despite the conceptual simplicity of its basic operation, a lot of practical drawbacks shrink the theoretical behavior, thus leading a significant number of research works to overcome them. The main objective in DPA research is to increase efficiency while maintaining linearity and filling the specified bandwidth. This paper presents a survey of the state of the art of DPA advanced design aspects. After a short review of the DPA operation principles, aspects regarding improvements for linearity, power efficiency and amplification bandwidth are introduced. Besides, some alternative structures and technologies, as well as practical design aspects and some trade-offs which the designer usually has to face are also presented., Peer Reviewed, Postprint (published version)

A Chireix outphasing transmitter at UHF band is presented in this paper, based on class E RF power amplifiers. As recently proved in [1], properly transforming the load modulation path, imposed by the non-isolated combiner, into fundamental frequency impedan ce values at the device drain terminals as close as possible to those assuring zero voltage switching condition, good efficiency values may be kept along a significant output power range. A lumped element implementation of the amplifiers and the combiner, together with the use of GaN HEMTs, allowed controlling the output power over a 6 dB range with an efficiency value over 60%. Experiments with asymmetrical two tones, conceived as a discrete spectrum signal with a 1:4 envelope variation, have shown the capability of the arch itecture to be linearized using digital predistortion (DPD). In order to reproduce a spectrally efficient communication signal, with nulls in the envelope, a hybrid control strategy was employed, combining the outphasing between branches with amplitude variations of both RF excitation signals for the lower range of the envelope. Average drain efficiency and PAE values of 63% and 60.3% respectively have been measu red, for a 11.8 W and 5.06 dB PAPR WCDMA signal, while m eeting ACPR specifications., Peer Reviewed, Postprint (published version)

This paper presents an Envelope Tracking Pow- er Amplifier whose architecture includes a Hybrid Envelope Amplifier (HEA) and an algorithm to adapt the envelope’s characteristics to the HEA’s limitations. The HEA attempts to combine the high efficiency of a switched amplifier with the wide band capabilities of a linear amplifier. A modified Slew Rate (SR) reduction algorithm cope with the bandwidth and SR limitations of the HEA. On the other hand, the non-linearities introduced by this Envelope Amplifier (EA) and by the dynamic supply are compensated using Digital Pre-Distortion. Results show that these non-linearities are compensable and that the architecture offers higher efficiency figures compared to the conventional linear EA, Peer Reviewed, Postprint (published version)

This letter presents a dynamic slow envelope dependent digital predistorter (SED-DPD) capable of compensating for the nonlinear distortion and memory effects that arise in envelope tracking (ET) power amplifiers (PAs) when using a slow version of the signal's envelope to dynamically supply the PA drain voltage. Moreover, a new DPD architecture based on the combination of several basic predistortion cells (BPCs) is presented to allow the FPGA implementation of the proposed SED-DPD. Finally, results showing the necessity and linearization performance of the proposed dynamic SED-DPD are provided., Peer Reviewed, Postprint (published version)

This paper analyzes the computing resource management implications of SDR base stations implemented as SDR clouds. SDR clouds describe distributed antennas that connect to a data center for digital signal processing. The data center employs cloud computing technology, providing a virtualized computing resource pool. The service area of a single SDR cloud may be a metropolitan area with a high user density. Hence, the data center will execute thousands of SDR applications in parallel, providing wireless communications services to several radio cells. Whenever a user initiates or terminates a wireless communications session, computing resources need to be allocated or deallocated in real time. We therefore propose a hierarchical resource management. This paper justifies such an approach and analyzes different resource management strategies. The results indicate the need for strategies that can dynamically adapt to the given user traffic distribution., Peer Reviewed, Postprint (published version)

This paper analyzes different resource management strategies for SDR base stations implemented as SDR clouds. SDR clouds describe distributed antennas that connect to a data center for digital signal processing. The data center employs cloud computing technology, providing a virtualized computing resource pool. The service area of a single SDR cloud may be a medium sized metropolitan area with a high user density. Hence, the data center will execute thousands of SDR applications—waveforms associated to different radio cells—in parallel. Whenever a user initiates or terminates a wireless communications session, computing resources need to be allocated or deallocated in real time. We therefore propose a hierarchical resource management approach and present simulation results that demonstrate its feasibility, Postprint (published version)

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L'objectiu d'aquest TFC es la implementacio d'un predistorsionador digital (DPD) per a compensar els efectes de no linealitats introduits per un amplificador de potencia (PA) alimentat dinamicament amb la tecnica de seguiment d'envoltant. Aquesta tecnica consisteix en substituir l'alimentacio estatica (nivell de tensio d'alimentacio constant), per un sistema d'alimentacio variable depenent de l'envoltant del senyal d'entrada. Per poder realitzar l'alimentacio dinamica del PA cal que el sistema d'alimentacio del PA pugui seguir correctament les variacions de l'envoltant del senyal. Per tant, existeix una limitacio en l'amplada de banda i slew rate utilitzat. Per aquest motiu l'alimentacio utilitzada no sera l'envoltant del senyal d'entrada sino una versio reduida d'aquest, amb variacions temporals mes lentes i una amplada de banda menor que l'original. En aquest projecte, primerament es creara un model del PA alimentat amb la tecnica de seguiment de l'envoltant lenta. Aquest model esta basat en un desenvolupament polinomic de les dues variables d'entrada de les quals consta: el senyal a amplificar i la seva envoltant lenta. Posteriorment, es dissenyara un predistorsionador capac de corregir els efectes de distorsio introduits pel PA. Es proposen dues estructures de DPD basades en una arquitectura multitaula. Aquesta arquitectura consisteix en obtenir els guanys de la funcio de predistorsio a partir de diverses taules de memoria que treballen en paral?lel. La posicio de la taula a la que cal accedir s'obte a partir del valor absolut del senyal d'entrada a cada cel?la basica de predistorsio (BPC). Les dues tecniques de predistorsio proposades son, primerament, una separacio del senyal d'entrada en diferents BPC en funcio del nivell de l'envoltant lenta, i una estructura basada en un desenvolupament polinomic de l'envoltant. Finalment, es presentaran els resultats obtinguts, les conclusions que se'n deriven i es discutiran linies futures de treball.

This paper focuses on the software-defined radio (SDR) educational aspects. We describe a few recent SDR projects and tools that were developed as part of a graduate electrical engineering course at the School on Telecommunication and Aerospace Engineering (EETAC) in Castelldefels, Barcelona. EETAC is part of the Polytechnic University of Catalonia (UPC). It applies the project based learning (PBL) concept and offers technical and scientific courses in Telecommunication and Aerospace Science and Technology (BSc, MSc, and PhD). The tools we describe here offer hands-on experience on several basic and advanced SDR principles. We describe our experience and the lessons learned., Postprint (published version)

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This paper presents behavioral modeling of an envelope tracking (ET) power amplifier (PA) excited by an slewrate limited envelope. In order to relax the slew-rate requirements of current efficient envelope amplifiers (EA), we can drive the ET PA with a slower version of the signal’s envelope. However, the resulting amplified signal suffers from nonlinear distortion due to the time-variant gain effects that arise when using the slower version of the signal’s envelope. In this paper this time-variant effects are presented and characterized. A new envelope-dependent (ED) behavioral model is presented and compared with a simpler static AM-AM and AM-PM modeling. Experimental results showing the performance of the proposed ED model were obtained with an ET PA based on a GaN transistor., Postprint (published version)

This paper presents a practical application of a method for generating slew-rate limited envelopes in order to drive the dynamic supply of envelope tracking (ET) power amplifiers (PAs). The proposed method results useful to generate slower versions of the transmitted signal’s envelope to cope with the slew-rate and bandwidth limitations of envelope amplifiers. Moreover, this paper shows experimental results comparing the performance of ET when exciting the drain of a PA (based in a GaN transistor) with both the envelope of the signal and the slew-rate limited version of the envelope., Postprint (published version)

This paper presents a new Digital Predistorter (DPD) to compensate for nonlinear distortion that arises in Envelope Tracking (ET) Power Amplifiers (PAs) driven by slew-rate limited versions of the real signal's envelope. The slower version of the transmitted signal's envelope is used to cope with the slew-rate and bandwidth limitations of Envelope Amplifiers (EAs). Unfortunately, the use of slower versions of the real signal's envelope as the drain modulator generates a special kind of nonlinear memory effects. This paper shows experimental results that prove that is possible to compensate for these nonlinear memory effects that appear when exciting the supply of a RF linear PA with a slew-rate limited version of the envelope., Peer Reviewed, Postprint (published version)

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Caldrà dissenyar i implementar un transmissor LINC (LInear Amplification with Nonlinear Components) en una FPGA. L'estudiant haurà de fer un recerca bibliogràfica del que és un transmissor basat en una arquitectura LINC així com la manera d'implementar-lo en un FPGA mitjançant el programa System Generator.

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El objeto de este proyecto es establecer las bases de diseño que permitan la realización de la instalación de seguridad y protección de las instalaciones de una "Huerta Solar" teniendo en cuenta las necesidades funcionales de dicho tipo de instalaciones. Para ello se definirán los diferentes elementos que compondrán la instalación, su conexionado y la infraestructura necesaria para el mismo (cableado, tubo, etc.). Los diferentes elementos que compondrán la instalación serán, medios físicos o pasivos (como son vallado exterior, muros, rejas), medios activos, en este caso electrónicos, que serán los elementos de detección (barreras de microondas, cable sensor enterrado y cámaras de televisión) y los elementos de control (centralización de las señales de intrusión en una central de intrusión y video grabador digital).

Aquest TFC consisteix en l'estudi i desenvolupament en matlab d'algunes de les tècniques de reducció de la potència de pic dels senyals OFDM. L'objectiu és la reducció del peak-to-average power ratio (PAPR)dels senyals a fi d'obtenir una amplificació en el transmissor que sigui, no tant sols lineal, sinó que també el més energèticament eficient possible.

El objetivo de este proyecto consiste en el desarrollo de un sistema de transmisión y recepción de señales multiportadora como la Orthogonal Frequency Division Multiplexing (OFDM). Este sistema OFDM es capaz de soportar diversas modulaciones M-QAM y está implementado en un procesador digital (DSP-FPGA). Para la implementación del sistema y llevar a cabo la programación de la FPGA se ha utilizado el System Generator corriendo sobre Matlab/Simulink o bien el programa Xilinx ISE que utiliza el lenguaje de programación VHDL. Este proyecto está dividido en cuatro capítulos, cada uno de ellos con un objetivo concreto. El primer capítulo es una breve introducción al tipo de procesador digital utilizado (field-programmable gate array -FPGA) y el lenguaje de programación VHDL. El segundo capítulo es una introducción de qué es OFDM, sus ventajas y desventajas frente a sistemas empleados anteriormente, y finalmente una introducción a los diferentes bloques que componen un sistema básico de transmisión y recepción OFDM. El capítulo tres presenta cómo se han implementado cada uno de los diferentes bloques del sistema y además incluye una breve introducción a la teoría que hay detrás de cada de uno de estos bloques para comprender mejor de qué forma se han implementado. El cuarto capítulo se centra por un lado en mostrar los resultados de las simulaciones hechas en Matlab/Simulink, y por el otro lado también muestra los resultados de las pruebas hechas con la FPGA en banda base y a la frecuencia de 3,5 GHz utilizando el material disponible en el laboratorio. Finalmente se presentan las conclusiones a las que se han llegado tras el desarrollo del proyecto.

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