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This study presents a high-efficiency low-noise pulse-width modulation (PWM) DC-DC buck converter based on multi-partition switching for mobile system-on-a-chip applications. A multi-partition switching technique is employed for the control of large current driving switches to minimise the switching noise. In addition, a PWM control with a switching frequency of 2 MHz is applied for the driving of output stage with a heavy load to optimise the power efficiency. The prototype DC-DC buck converter with an active die area of 0.28 mm2 was implemented using a 0.18 µm bipolar-CMOS-DMOS (BCD) process. The peak power efficiency is 93%, while supplying an output current of 200 mA and an output voltage of 1.8 V. [ABSTRACT FROM AUTHOR]

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 ඵm CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation. [ABSTRACT FROM AUTHOR]

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 µm CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm². [ABSTRACT FROM AUTHOR]

Moving target has a non-coherent phase characteristic regardless of micro-Doppler effect caused by body motion, because the movement of the target changes the beat-frequency and its phase. A phase compensation method to remove the phase variations caused by movement is proposed. Using the proposed phase compensation method, it is possible to classify targets as pedestrians or automobiles based on the phase variance because pedestrians and automobiles have non-coherent and coherent phases, respectively. Through applying experimental data, the possibility of target classification is shown. [ABSTRACT FROM AUTHOR]