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International audience; SOI circuit exhibits excellent performance and rehabilitee but with the component miniaturization trend and the clock frequency increase, the self-heating phenomena that arise from the SOI structure itself must not be underestimated. In order to minimize this problem, several candidates have been identified to replace the buried silicon oxide (SiO2) by high thermal conductive dielectric layers such as HfO2, Si3N4, diamond or Al2O3. In order to elaborate a SOI structure using this kind of innovative buried dielectric, first of all, their direct bonding with silicon has to be studied. In this work, we investigate the bonding thermal behaviour of Si/Al2O3 and Al2O3/Al2O3 direct bonded structures: bondings are submitted to room temperature up to 900 A degrees C annealing. Amorphous or crystallized Al2O3 thin films were used in this study. Bonding energies are measured in an anhydrous atmosphere and bonding defectivity is analysed using scanning acoustic microscope (SAM). With amorphous a-Al2O3 layer, for T > 200 A degrees C, high bonding energy are obtained even if high defect density appeared when annealing temperature exceeded 400-500 A degrees C. Spontaneous debonding phenomena even occurred for a-Al2O3/a-Al2O3 direct bonding. This defectivity, unobservable using infrared camera, may be explained by chemical or structural Al2O3 modification such as gases desorption, internal stress or crystallisation state. Bonding with crystallized Al2O3 film has been also characterized by infrared spectroscopy and complementary analysis. No high defect density is observed with crystallized Al2O3 layer. Based on these results, an Al2O3 bonding mechanism is proposed.

A photovoltaics conversion efficiency of 46% at 508 suns concentration was recently demonstrated with a four-junction solar cell consisting in a GaAs-based top tandem cell transferred onto an InP-based bottom tandem cell, by means of wafer bonding. We have successfully produced and characterized different InPOS (for InP-On-Substrate) composite substrates, that could advantageously replace fragile and expensive InP bulk wafers for the growth of the bottom tandem cell. The InPOS composite substrates include a thin top InP layer with thickness below 1µm, transferred onto a host substrate using the Smart Cut™ layer transfer technology. We developed InP-On-GaAs, InP-On-Ge and InP-On-Sapphire substrates with surface and crystal qualities similar to the InP bulk ones. A low electrical resistance of 1.4mΩ.cm² was measured along the InP transferred layer and the bonding interface. An epitaxial bottom tandem cell was grown on an InPOS substrate, and the corresponding PL behavior was found identical to that of cells...

Comparisons of various plasma assisted low temperature wafer bonding procedures have been conducted in order to carry out reliable void-free and high bonding strength. In this way, reactive ion etching (RIE), microwaves (MW) and inductive coupled plasma (ICP) modes have been investigated as surface cleaning and activation processes before Si-Si direct bonding. Moreover impacts of some additional prebonding surface treatments have been analyzed for such bonded structures. Using these additional treatments, focus has been specifically made on efficiencies to perform void-free and high bonding strength for Si-Si direct bonding thanks to prebonding 300{degree sign} heating and/or on under-vacuum bonding.

For both hydrophilic and hydrophobic surface preparation, using the combination of advanced surface treatment and tuned annealing process, void free Si/Si direct bonding have been successfully obtained. The pre-bonding procedure involves only low temperature (

Introduction of hybrid orientation substrates has led to the development of CMOS technologies in which NMOS transistors are fabricated on (100) Si and PMOS on (110) Si. This maximizes the crystal orientation dependent mobilities of electrons and holes. The Smart Cut technology has been successfully applied to fabricate hybrid orientation substrates with a buried oxide between the top Si layer and the bulk substrate having two different crystal orientations. This paper describes the application of the Smart Cut method for the fabrication of the directly (i.e. with no oxide in between) bonded 300 mm Si engineered substrates. The technological challenges, process flow and the results of the wafer characterization are presented and discussed.

In order to control simultaneously the nanostructures size, density and positioning, nanopatterned substrates are elaborated using an original process based on the revelation by preferential chemical etching up to the surface of a buried square dislocation network obtained by direct twist wafer bonding. By including the dislocation network into a SOI substrate thin film the surface patterning evolution during the selective chemical etching for 20 and 50 nm periodicity samples is controlled and checked by Scanning Electron Microscopy (SEM). A dislocation network periodicity dependent surface grating is showed. Si mesas with efficient aspect ratios are obtained after a second selective chemical etching allowing the further Ge islands self-assembled growth. Germanium growth equivalent to 10 Aå layer is performed at 600{degree sign} C on 50 nm periodicity nanopatterned surfaces. For different cooling rate from deposition temperature to room temperature the dots size, shape and density are characterized by Scanning Tunneling Microscopy and SEM.

Direct bonding is now a well-known technique to join two flat surfaces without any additional material. This technique is used in many application and especially in SOI (Silicon on insulator) elaboration or in some backside imager manufacturing process which is now almost a mass production process. Direct bonding mechanism study is then very important in order to clearly understand this bonding behaviour. Especially in the case of silicon or silicon dioxide hydrophilic surface, the role of water is essential. Water could lead to lots of different reactions at the bonding interface and especially the water stress corrosion could play an important role in the direct bonding mechanism. After having reviewed the different silicon dioxide water stress corrosion in the literature [1,2], its influence in the direct bonding area will be pointed out. The direct bonding energy measurement, G, using the double cantilever (DCB) beam technique is for instance highly affected by the water stress corrosion [3, 4, 5, 6]. In addition to the direct bonding energy, this DCB technique is also very interesting to allow improvement of the direct bonding mechanism. Indeed, as the water stress corrosion only appears with siloxane bonds, it could be an interesting characterization of the classical silicon direct bonding reaction: Si-OH+Si-OH => Si-O-Si+H2O We will then show that siloxane bonds could appear already at room temperature and not only during the classical post bonding annealing process using for instance plasma activated bonding by changing the relative humidity of the characterization atmosphere. This water stress corrosion is also put into evidence during adhesion bonding energy and subsequent G measurement in which the hysteresis cycle which appears between these two measurements shows that specific siloxane bonds appear after the bonding wave propagation [7, 8]. Moreover, they put in evidence the effect of the atmosphere humidity in such hysteresis cycle. In addition to this, the water stress corrosion could be used to put into evidence the remaining water at the bonded interface [9]. Indeed in specific dioxide/dioxide bonding, Ventosa et al. [10] show that the water could remain at the interface until post bonding annealing treatment of 400°C during 2 hours and we will show that this can be seen by the water stress corrosion which takes place even in anhydrous atmosphere for this bonding type. Thus, the stress corrosion study in anhydrous atmosphere can deeply participate to the elaboration of a direct bonding mechanism. Moreover, one could think that the water stress corrosion plays an active role in the direct bonding evolution. Indeed, in other silicon dioxide processes, as CMP for instance, the water stress corrosion helps to hydrolyze the surface and to remove the polished material. The water stress corrosion might help the surface asperities to deform in order to increase the bonding area and thus the bonding energy. Furthermore, as the water stress corrosion rate depends on the temperature [11], it could also participate to the bonding energy evolution versus annealing temperature. The direct bonding mechanism could then be seen as a mechanical model of asperity deformation greatly helped by the trapped water at the bonding interface. Besides the bonding energy evolution, we will also discuss how the water stress corrosion study of bonded structure could be very interesting for the characterization of bonded interface chemical resistance. Indeed a good relation is seen between the chemical interface resistance and the water stress corrosion sensitivity [12]. The water stress corrosion study in bonded structure and especially in silicon or silicon dioxide bonding is then very fruitful and should deserve to be extended to other type of bonding interface and materials. REFERENCES [1] S.M. Wiederhorn, et al., J.Mater.Sci. (17) 3460 (1982). [2] M. Ciccotti, J.Phys.D (42) 214006 (2009) [3] O. Vallin, et al., Mat.Sci.andEng. R50 109 (2005). [4] T. Martini, et al.,Soc. 144(1) 354 (1997). [5] Y. Bertholet, et al., Sens.Actua.A 110 157 (2004). [6] F. Fournel, et al., J.Apl.Phys. (111) 104907 (2012). [7] D. S. Grierson et al., ECS Trans. 33(4) 573 (2010). [8] D. Radisson, to be published. [9] C. Martin-Cocher, to be published. [10] C. Ventosa, et al., J.Appl.Phys. 104 (2008). [11] S. N. Crichton et al., J.Am.Ceram.Soc. 82(11) 3097 (1999). [12] T. Suni, et al., ECS Trans. (19) 70 (2003).

A buried (001) low angle twist boundary (misorientation angle 0.48°) in silicon is investigated by the technique of two-beam transmission electron microscopy using bright-field images obtained from diffracting vectors g{400}, g{311} and g{220}, and g{nnn} with n = 3 and 4. To analyse its elastic field, the concept of interfacial relaxation centres is assumed, for which the relative displacement field of the two crystals is zero. These centres are located in the middle of each square formed by a dislocation unit cell. This assumption is tested positively for the first time for a double periodic network of screw dislocations. For the image contrast calculations, the elastic field of the network is that of two perpendicular families of screw misfit dislocations in the sense of Bonnet (1981). Since the two-beam bright-field approximation is weak to explain the experimental images taken with g{nnn} and n = 3 and 4, extra N beam image calculations involving N

Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart CutTM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

Resume Une image d'un sous-joint de torsion (0 0 1) du silicium, obtenue en MET a deux ondes, est interpretee de facon quantitative au moyen de la theorie dynamique de la diffraction des electrons. Les caracteristiques du contraste sont discutees en fonction de l'epaisseur de la lame mince et des effets eventuels de relaxation elastique du sous-joint dans la lame mince. Pour citer cet article : R. Bonnet et al., C. R. Physique 3 (2002) 657–663.

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage issue, “molding last” was studied with the selected material, including compatibility with temporary bonding debonding, bumping, sawing and report on organic substrate. A focus is made on void-less molding-underfilling process development and wafer level reliability evaluation of first level (die to wafer) interconnections and TSV subjected to thermal cycles. For this study, a molding-last approach using a dry-film lamination process has been chosen. 170μm thick dice have been assembled on 120μm thin silicon interposers having 60μm diameter TSV via-last and encapsulated with optimized wafer-level MUF process. Electrical performances of the 35μm high Cu pillars interconnections have been measured on the interposer backside thanks to TSVs and rerouting. While the daisy chains resistances remained in specifications after molding and pre-conditioning, some electrical failures appeared after 250 thermal cycles. Cross-sections have highlighted cracks in solder joints leading to the development of an improved version of the compound. Finally, a complete test vehicle with a molded-underfilled interposer reported on an organic substrate has been achieved.

Micro Electro-Mechanicals Systems (MEMS) include moving elements in some cases and they require a controlled atmosphere to operate. Hence they are protected by a cap assembled to the sensor by wafer-level packaging. For specific MEMS packaging, the process should provide strong and hermetic sealing walls of reduced size, less than 100 μm which also ensure electrical conductivity. If a high-temperature-resistant sealing (>200 °C) is also required, Al-Ge eutectic bonding is suitable. In eutectic bonding, the constituents of the alloy are deposited on at least one of the two wafers which are brought into contact. The melting and then the solidification of the solder close the interface to form an assembly. The Al-29.5at%Ge eutectic alloy, with a melting temperature of 424 °C [1], has been shown allowing strong and void-free bonds [2-4]. Nevertheless, during bonding, the eutectic liquid tends to squeeze out of the seal ring which can lead to void formation at the sealing interface and areas with unwanted metal. Moreover, influences of the underlayer on the bonding mechanisms have not been investigated whereas it is known to have an impact on Al/Ge bilayers [5]. In this paper we study the formation and behaviour of liquid Al-Ge alloy, its solidification, the resulting microstructures and the appearance of voids. The main investigated parameters are: - the underneath layer which is related to the wettability of liquid Al-Ge eutectic - the annealing temperature and cooling rate and their influence on solidified microstructure - the seal rings geometry The 200 mm silicon substrates used in this study are either thermally oxidized or covered by a 50nm-thick titanium nitride layer to prevent metal diffusion into silicon substrate. Blanket and patterned Al/Ge deposited wafers with 0.59 μm Ge/1 μm Al are used as single wafers and in bonded structures. The seal rings are 5 mm square with widths varying from 50 to 200 μm. Thermal treatment and bonding are performed under either vacuum (10-3 mbar) or inert gas (N2) at atmospheric pressure. Experimental temperature is varied from 400 °C to 500 °C with cooling rates varying from 1 °C/min to 20 °C/min. In order to evaluate the influence of the underneath layer on the behaviour of liquid Al-Ge eutectic alloy during bonding, the wetting of different substrates is investigated by dispensed drop method, under a vacuum of 5x10-7mbar. High purity aluminum and germanium (99.999 %) are used to prepare the alloy in an alumina crucible ending by a capillary to deposit a droplet on the studied surface. Observations are made in situ by camera and analyzed using Drop Shape Analysis software (Fig 1a). In addition, the melting and solidification process of many 1x1 cm2samples from blanket Al/Ge deposited wafers are studied by Differential Scanning Calorimetry (DSC) by using different cooling rates. The microstructures are then analyzed by optical microscopy, Secondary Electron Microscopy SEM and Energy Dispersive X-ray spectrometry (EDX). In some cases large dendrites are observed, which could be critical for a bonded structure (Fig 1b). Finally blanket and patterned Al/Ge deposited wafers are bonded to silicon wafers either thermally oxidized or covered by a titanium nitride layer. The influence of underneath layer, geometry (for patterned wafers) and cooling rates on squeeze-out and voiding phenomenon are characterized using Scanning Acoustic Microscopy SAM and FIB SEM (Fig 2). Image analysis is used to compare voiding densities between bonded samples (Fig 3). The results appear to be dependent on the process conditions. Underneath layer and cooling rate seem of great importance to control the squeeze-out and solidified microstructures in Al-Ge eutectic sealing and to determine the quality of the final assembly. Thanks to these characterizations and especially to the wettability measurements, mechanisms will be proposed to explain the squeeze-out result. REFERENCES [1] Rodney P. Elliott et al., Bulletin of Alloy Phase Diagrams, vol 1, n° 1, pp 65-68, 1980 [2] B.Vu et al., J. Vac. Sci. Technol.B, vol. 14, n° 4, pp. 2588-2594, 1996. [3] F.Crnogorac et al., J. Vac. Sci. Technol.B, vol. 30, n° 6, 06FK01, 2012. [4] S.Sood et al., Advancing Microelectronics, vol 41, n° 5, pp 30-37, 2014. [5] K. Nakazawa et al., Jpn. J. Appl. Phys., vol 53, n°4, 04EH01, 2014. Figure 1

Direct wafer bonding has already been demonstrated as an efficient solution to create a linkage between two different surfaces. One of the main limitation is the temperature required to stabilize the bonding interface and the strength. For example, to completely stabilize a Si/Si bonding realized at room pressure, an annealing step done at 1000°C or above is required. In the past, alternative low temperature processes, using plasma activation of the surfaces before contact between them, were developed for SiO2 to Si and SiO2 to SiO2 bondings, lowering the annealing temperature at 300°C and enabling enough bond strength for many applications [1]. Another possible option to realize a room temperature Si/Si bonding is to use a covalent bonding process [2]. The EVG®580 ComBond® was developed with this aim by bringing the wafers in contact in an ultra-high vacuum environment, after activation in vacuum of both surfaces in the ComBond® Activation Module (CAM®) [3,4]. This paper aims to present observations made after the transfer of a thin layer using this novel direct covalent Si/Si bonding process. The bonding process was realized in an EVG®580 ComBond® equipment installed at CEA-Leti. At first, the equipment and the process window were qualified in terms of metal and particle contaminations. Measurements of particles with a threshold at 90nm were performed, and detection of metals contamination demonstrated that the whole bonding process was metal free with a specification of 1.1010 at/cm² for all metallic elements. The activation process, performed in the CAM®, was also characterized, especially in terms of etching rate, roughness and amorphous thickness measurement done by ellipsometry. Then, an appropriate bonding process, demonstrating a high bond strength (>5 J/m²) was developed for Si/Si 200 mm wafers. Using this process, the bonding of a SOI (Si 100nm - SiO2 200nm) with a Si wafer was performed, in order to transfer the SOI Si layer onto a new substrate and to characterize both the bonding and the transfer qualities. In this study, bonding quality is assessed using C-mode Scanning Acoustic Microscopy (C-SAM) which is performed just after bonding, as shown on figure 1a, where no defects have been observed. More generally, in order to control the bonding and the layer transfer processes, particle contamination measurements deserve to be performed on the SOI surface before bonding and after layer transfer. It may be done using a SurfScan equipment (SP2) from KLA-Tencor with a detection threshold value of 90 nm for instance. If large particles are deposited at the bonding interface during activation process, they lead to non-transferred areas (i.e. holes) visible after layer transfer. As we can see from figure 1b, no holes or additional defects are detected after such a layer transfer. Thus, perfect quality of transferred layers on 200 mm full wafers is shown. Additional measurements may be performed in order to characterize the bonding interface. Ellipsometry is used to measure the thickness of the amorphous area created during the surface activation step. TEM observations, made before and after recrystallization, allow to confirm the thickness of the amorphous layer, as well as to study the temperature at which the Si interface is fully recrystallized. Finally, SIMS measurements is used to characterize the other species than Si which could be found at the bonding interface like oxygen, carbon, and metallic elements for instance. The successful transfer of a thin Si layer onto a new substrate shown in this work demonstrates that such a bonding process would deserve to be applied to many other thin layer transfer techniques. REFERENCE [1] T. Plach, K. Hingerl, S. Tollabimazraehno, G. Hesser, V. Dragoi and M. Wimplinger, J. Appl. Phys., 113, 094905 (2013) [2] H. Takagi, K. Kikuchi, R. Maeda, T. R. Chung and T. Suga, "Surface Activated Bonding of Silicon Wafers at Room Temperature", Appl. Phys. Lett. Vol. 68, No.16 (1996), pp. 2222-2224. [3] C. Flötgen, N. Razek, V. Dragoi, M. Wimplinger, “Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication”, ECS Trans. 64(5), The Electrochemical Society, pp. 103-110, 2014 [4] C. Flötgen, N. Razek, V. Dragoi, “Functional Interfaces Fabrication Through Room Temperature Wafer-Level Bonding”, Proc. of WaferBond Conference, 2015, pp. 55-56 EVG®580 is a Trade Mark of EVGroup ComBond® is a Trade Mark of EVGroup CAM® is a Trade Mark of EVGroup Figure 1

A direct wafer bonding process has been developed to accurately control both the bonding interface twist and tilt angles between a monocrystalline layer and a bare monocrystalline wafer. This process is based on the bonding of twin surfaces produced by splitting a single wafer, using for instance the Smart Cut® process. A targeted control of ±0.005° is obtained for the twist angle without any crystallographic measurement. Moreover, pure twist-bonded interfaces have been artificially made between two (001) bonded silicon surfaces.

Ultrathin (001) Si films bonded onto (001) Si wafers, inducing grain boundaries with twist angles varying from 0.5° to 12°, were studied by transmission electron microscopy. A great structural difference between low (ψ 6°) twist angles was observed. In low twist angle grain boundaries, “twist interfacial dislocations” are dissociated and produce rough interfaces with no oxide precipitates. It is the opposite in high-angle grain boundaries: there is no dissociation, the interfaces are smoother but contain oxide precipitates. These differences are not attributed to the thin thickness of one grain, but to the large atomic differences between high- and low-angle twist grain boundaries, which is not the case for tilt grain boundaries.

Chemical mechanical planarization (CMP) process steps are increasing in frequency and criticality. The introduction of new, sensitive dielectric materials as well as sensitivity to residual slurry and particle contamination make the post CMP clean an integral part of a good yielding CMP step. Brush Scrubbing is the traditional method of post CMP cleaning. With this contact cleaning method particles are removed by direct contact of a rotating brush with the wafer surface. These particles are then swept away by the cleaning solution. This method of cleaning has some well known challenges, among them cross contamination from wafer to wafer, brush marking and scratching as well as process feedback and control. An alternative physical cleaning method utilizes the cavitation created by the presence of Megasonic energy in the process fluid to provide a non-contact method of slurry residual and particulate removal from the planarized surface. The Megasonic apparatus used in these experiments has been successfully applied to other single wafer cleaning processes and is implemented in many large volume production applications. Most mass production post CMP cleaning processes consist of a series of cleaning and chemistry steps as well as a mix of physical cleaning approaches. The challenge in quantifying effect and comparing cleaning efficiency between contact and non-contact physical cleaning has been in the isolation of cleaning results attributed to a change in method. In this work we were able to provide conditions for a direct comparison of cleaning methods in a special post CMP scrubber. This tool is configured for brush or Megasonic processes in the same chamber with the identical wafer flow from the polisher. The CMP was done on thermal SiO2 using two varieties of conventional slurry and a common pad type. Fifty wafers were split processed, half with 150835 and half with D3586. A large delta in particle removal efficiency was observed based on slurry type alone. The brush parameters were based on a long term process of record. (Table 1) Several megasonic parameters were varied to better understand the process window. Analysis of cleaning results was performed using an SP2 with a threshold of 90nm. (Figure 1) Table 1, Experimental process recipe details Brush Recipe Step Time (sec) Chemical Wafer RPM Brush RPM 1 40 NH4OH 2% 20 80 2 40 DIW 20 80 3 20 DIW 60 No Brush 4 Dry 2000 Meg Recipe 1 Step Time (sec) Chemical Wafer RPM W/cm2 1 52 NH4OH 2% 60 2.5 2 48 DIW 60 2.5 3 Dry 2000 0 Meg Recipe 2 Step Time (sec) Chemical Wafer RPM W/cm2 1 52 NH4OH 2% 60 1.85 2 48 DIW 60 1.85 3 Dry 2000 0 Meg Recipe 3 Step Time (sec) Chemical Wafer RPM W/cm2 1 90 NH4OH 2% 60 1.85 2 10 DIW 60 1.85 3 Dry 2000 0 These direct comparison tests prove that the non-contact Megasonic method equals or exceeds the cleaning results achieved with the traditional brush cleaning under identical process flow and conditions. Figure 1: Post CMP clean particle counts 90nm threshold with D3586 slurry. Figure 1

The misfit stress between an epilayer and its substrate can be determined, via the Stoney formula, from the sample curvature generated by the relaxation of this stress. This curvature method has been transposed to transmission electron microscopy. The Stoney model assumes the observed zones present particular dimensions and geometry. Finite element calculations have shown that narrow rectangular lamellae cut by focused ion beam comply well with the criteria of the model. This technique has been applied to analyse a Si/SiGe(001) structure.

Investigation of a surface patterned by buried dislocation networks is performed with grazing incidence x-ray scattering (GIXS). It is shown that surface long-range undulations lead to a azimuth-dependent diffusion spot, the scattering vector of which is mainly parallel to the x-ray propagation direction. This unusual scattering direction with GIXS is explained by the scales of the scattering objects. A geometrical model is proposed to extract the periodicity of the surface from GIXS.

In the past few years, the More than Moore initiative has led to a focus on developing new process flows in the 3D-IC field [1-2]. One of the key points for an entire 3D integration success is being able to handle the thin wafer during backside processing reliably. Temporary bonding has emerged as one of the answers [3-4]. However, some challenges still need to be overcome in order to fully control and understand this technique. Temporary bonding is based on the use of a carrier wafer bonded to a device wafer, thanks to an adhesive layer. Depending on the temporary bonding technology used, an additional release layer or anti-sticking-layer may be added to the stack to facilitate debonding. For any technology, the temporarily bonded stack consisting of the device and the carrier wafer has to withstand the backside process flow while being easily de-bondable at the end of this process. In order to fulfill these requirements, the temporary adhesive is playing a major role: it has to demonstrate at the same time high thermal resistance (above 260°C for 30min), as well as an excellent cleanability or removability after simple de-bonding. The adhesive must also provide a means for embedding the front side topology of the device wafer while demonstrating resistance against process chemicals and exhibiting compatibility with processes requiring vacuum environments. All these criteria are difficult to match with one solution because they require different polymer properties. Thermoplastic, silicone based and polyimide based materials as well as other polymers have been investigated with respect to overcoming those challenges [5-6-7]. Specifically, the delamination defect observed - most commonly with thermoplastic solutions- is an important issue remaining not fully understood. This paper aims at studying the root cause of delamination defects observed in temporary bonding, and defines which key parameters of the device or of the 3D integration process itself should be checked before selecting the temporary bonding material. Based on that, process windows for existing and new materials could be then studied regarding the key parameters defined through this work. To start, parameters which could be the possible root cause for delamination have been defined. This delamination phenomenon is occurring frequently during PECVD deposition. This deposition process is done under temperature and vacuum. Moreover, the use of plasma is creating a local increase of the temperature of the wafer. The thin device can also react to the deposition, by changing its stress or its bow during the process. Five factors are then discriminated from these observations as possible root cause (process temperature, vacuum level, thermal gradient, bow and warp, intrinsic stress). Simple test vehicles have been developed to study individually each of the five parameters listed above. At the end, some tests combining different parameters have finally shown the complex mechanism behind the delamination phenomenon. In this paper, we will present each test vehicle, the respective results and observations. At the end we will see that the combination of three parameters is leading to the delamination defect and the interaction between them will be discussed. Moreover mechanical simulation will be carried out to define numerical criteria for describing and finally avoiding such delaminations. REFERENCE [1] J. U. Knickernocker et al., “2.5D and 3D technology Challenges and Test Vehicle Demonstrations”, Proc. of Electronic Components and Technology Conference, 2012, pp.1068-1076. [2] S. Cheramy et Al., “200mm & 300mm processes & characterization for face to back flow chart for WideI/O”, Proc. of International Microelectronics And Packaging Society, 2012, pp. 8-13 [3] J. Burggraf et al., “Low temperature wafer bonding for 3D applications”, Proc. of WaferBond Conference, 2013, pp. 127-128 [4] T. Matthias et al., “Room temperature debonding – an enabling technology for TSV and 3D integration”, Proc. of Electronic Packaging and Technology Conference, 2012, pp. 244-247 [5] A. Jouve et al., “WSS and ZoneBONDTMtemporary bonding techniques comparison for 80µm and 55µm functional interposer creation”, Proc. of Electronic Components and Technology Conference, 2013, pp. 101-106 [6] K. Vial et al., “Challenges and solutions for ultra-thin (50µm) silicon using innovative ZoneBONDTMprocess”, Proc. of Electronic Packaging and Technology Conference, 2012, pp. 450-455 [7] P. Montméat et al., “TTV value improvement of thin films obtained by temporary bonding ZoneBONDTM technology”, Proc. of WaferBond Conference, 2013, pp. 147-148

Monolithic 3D Integration (3DMI) consists in processing transistors on top of each other sequentially. This technology appears to be an alternative solution to scaling, from the 7nm node integration and below, as substantial gain in area and performance as compared to planar technology is expected without scaling the transistor technology node. 3DMI appears to be the most optimized way to take advantage of the vertical dimension as almost no alignment constraints remains. By using a standard lithography, the top transistors can be aligned directly onto their bottom counterparts with a high accuracy (see Fig. 1), contrary to TSV-based 3D technologies [2]. Furthermore, 3DMI is a highly versatile technology as the different transistor levels can be optimized independently, from the choice of the channel characteristics (e.g. material, orientation, strain) to the architecture itself (e.g. CMOS on CMOS, PMOS on NMOS, FinFET on BULK, LVT on RVT) [3]. Such sequential integration raises two main technological challenges: - Creating an active layer above a bottom transistor which will become the channel of the top transistor. In order to achieve similar performance for top FET than bottom FET, the substrate quality must be equivalent than commercial substrates. Thus, this layer must be monocristalline and defect free in order to optimize the mobility and to be consistent with high performance criteria. A precise thickness control is also necessary in order to avoid device performance dispersion. - Realizing a high performance top transistor level without degrading the bottom level as the stacked transistor levels are processed sequentially, i.e. at low temperature process –typically below 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C [4]. To tackle the first challenge, we transfer a thin silicon layer from a high quality Silicon On Insulator (SOI) wafer by direct bonding. It appears to be the most effective solution to obtain a defect free monocristalline active layer with a well-controlled thickness. This method is preferred to different techniques which have been developed to create large monocristal grains of silicon either by laser anneal of amorphous Poly-Silicon [5] or by µ-Czochralsky process [6]. However, in both cases, large “seed layers” are necessary to control the orientation and the size of these grains, which is not consistent with for high density circuits. For this layer transfer, a blanket SOI wafer on which a Si02 layer is either grown or deposited, is bonded on the classical pre-metal dielectric above the bottom transistor level. The SOI backside is then removed by grinding and chemical etching to keep only the silicon layer. While expert knowledge has been reached for full sheet wafer bonding, the situation on a patterned layer can be really challenging with the design rules of 3DMI. In order to face these challenges, the surface preparation, the direct bonding process and the thinning steps have been optimized to prevent any defect on the whole 300mm surface. Also TMAH bevel edge protection and silicide protection layer have been added. This work will give a general overview of 3D monolithic challenges. Also, a specific focus will be made on direct bonding which is a major enabler of this type of integration. Indeed among the other alternative techniques, it appears to be the best solution to meet the high performance and high density criteria. REFERENCES: [1] P. Batude et al., VLSI Technology, pp. 158 (2011) [1] P. Batude et al., ECS Spring meeting, (16) pp. 47 (2008) [2] P. Batude et al., IITC-AMC (2014) [3] P. Batude et al., IEDM, pp.731-734 (2011) [4] C-H. Shen et al., IEDM, pp. 931-934 (2013) [5] J. Derakhshandeh et al., TED vol.58, no. 11 (2011) Fig.1: 3DMI demonstration with ultra-high alignment between the stacked transistors [1] obtained with 248nm stepper.

Direct bonding is used to join two mirror-polished wafers without any additional material. This technique demonstrates to be more and more attractive for microelectronics, MEMS, or optoelectronic applications as example. In many of them, Silicon-On-Insulator (SOI) substrate is used including a SiO2 buried layer (BOX). Face to circuit performance request, SOI self-heating in these devices has to be improved, replacing BOX by adapted layers, for instance. The conciliation between the thermal and electrical properties has already pointed out different materials such as diamond, Al2O3, HfO2 or Si3N4 [1]. Atomic Layer Deposited (ALD) amorphous Al2O3 thin film seems to be very interesting but different problems as for instance debonding phenomena [2][3], or defect emergence [4][5][6] could appear during their elaboration which motivated our direct bonding mechanism study. In this work, comparative results between free surfaces and bonding configurations will be done in order to establish bonding behaviour of ALD Al2O3.A bonding mechanism will be discussed and proposed. The study is carried out on 300mm, lightly p-doped Si wafers. Substrates have been oxidized by plasma or thermal treatment in order to create 1.5, 20 or 145nm SiO2 sub-layer. 20 nm-thick amorphous alumina (a-Al2O3) films were then deposited at low temperature (300°C) by ALD using TMA and H2O precursors. Some samples were annealed at various temperatures under nitrogen or oxygen atmosphere in order to crystallize the amorphous alumina. Due to low chemical resistance of the amorphous ALD Al2O3layer, the wafers were just rinsed with de-ionized water under megasonic power, dried and contacted to each other or directly to silicon wafers or oxidised silicon wafers at room temperature (RT) and atmospheric pressure. Bonding quality is analysed at room temperature and after various annealing temperatures. After 400°C post bonding annealing, using scanning acoustic microscopy (SAM), a high defect density is observed for several bonding type (fig 1a) which is invisible using wafer-scale IR observations (fig 1b). In the specific a-Al2O3/a-Al2O3bonding, debonding could even occur after 500°C annealing. Bonded surface analyses exhibit inhomogeneous fracture and bubble traces at the bonding interface (fig 1c). This paper will deal with bonding mechanism and the defect origin. We will highlight the role of water/hydrogen diffusion in the bonding process and the link that could be done with the well-known [4][7] defects which could appear during O2-atmosphere annealing of amorphous ALD Al2O3 free surfaces (fig2a) while no defect are seen under N2annealing (fig2b). Using atomic force microscopy to measure the surface roughness, the electron beam microscopy to visualize the debonding interface, the anhydrous bonding energy measurements, the FTIR-MIR [8] to characterize the chemical interface evolution and the X-ray reflectivity for monitoring the interface electron density profile, all the different bonding structures achieved in this study have been analysed (preannealing, sublayer use…). Based on known SiO2 hydrophilic direct bonding mechanisms [8], refined bonding mechanisms for amorphous a-Al2O3 bonding will be proposed. Therefore, defect free amorphous Al2O3bonding could be obtained overall the post bonding annealing temperature range (RT-1200°C) as shown for 300mm bonded structures (Fig 3). One of the first applications of this work would be the elaboration of high quality SOI structure having this ALD Al2O3layer as an insulating layer. ACKNOWLEDGMENT The authors would like to thank SOITEC for its support. REFERENCES [1] N. Bresson, et al. Solid-State Elect. 49, 1522-1528, 2005 [2] P. Ericsson, et al., ECS PV, 576, 1997 [3] C. de Beaumont, et al., Electro Soc. 3, 231-236, 2005 [4] M. Yokoyama, et al., Semi. Sci. Tech., 28, 2013 [5] D. Landru, et al., ECS JSS and Tech, 6, 2, Q83-Q87, 2013 [6] E. Beche, et al., Micro Techn (submitted) [7] T. Nabatame, et al., JAP, 42, 7205-7208, 2003 [8] C. Ventosa et al., JAP, 104, 2008

Single Si/SiO 2 quantum wells were fabricated using silicon on insulator (SOI) substrates, the upper barrier being a thin thermally oxidized Si layer. Samples were Er and O implanted at low energy in order to center their concentration profile in the well, and then annealed. A bulk Si sample implanted under the identical conditions was used as a reference. We present low temperature photoluminescence results using UV excitation in order to create photogenerated carriers mainly in the Si well. We show that the 1.54-μm photoluminescence is much more intense for Er in a well than for Er in implanted bulk silicon. We show that infrared emission occurs through an energy transfer mechanism from Si to Er centers. Confinement prevents the escape of photogenerated carriers towards the substrate and promotes energy transfer towards optical active erbium center.

International audience; Ultrathin films of silicon bonded on 4-inch (001) silicon wafers have been obtained by combining a direct hydrophobic silicon bonding technique with a layer transfer. The strain field produced by the dislocation network localized at the bonded interface is a good candidate to induce a long-range order growth of nanostructure. To be able to make this new kind of substrate, knowledge of the dislocation strain field extension is essential. Grazing incidence X-ray diffraction allows us to measure its spatial extension through the diffraction peak satellites due to different dislocation networks. The exponential decay of these peaks were measured and compared. We found that the decrease of the strain field extension is almost two times lower for the screw dislocation network than for the ‘mixed’ dislocations one. The film thickness control is then two times more critical for the screw dislocations.

International audience; Twist-bonded Si/Si (0 0 1) and Si/SiO2 interfaces have been investigated by grazing incidence X-ray scattering methods. For Si/Si (0 0 1) bonding, conventional X-ray reflectivity reveals the good quality of the interfaces in terms of flatness and roughness. In-plane grazing incidence diffraction measurements around the (2 2 0) reflection show satellite peaks close to the substrate and the layer diffraction peaks. These sharp satellites are produced by a periodic displacement resulting from a very regular buried dislocation network. The Si/SiO2 bonding has been studied with X-ray reflectivity within a transmission geometry. The analysis of the data shows the high quality of both bonded Si/SiO2 and thermal oxide SiO2/Si interfaces.

International audience; Ultra thin film of silicon bonded on 4 in. (001) silicon wafers have been obtained by combining a direct hydrophobic silicon bonded technique with a layer transfer. The twist angle between the ultra thin Si film and the Si substrate was varied from 0 to 15°. X-ray reflectivity measured the thickness and the roughness of the ultra thin films. Complementary results concerning the interface structure were obtained with high resolution transmission electronic microscopy. It is shown that an ultra thin film (a few nm) can be reproductively prepared upon the full 4 in. wafers. Moreover, this process gives very small thickness fluctuations and a small surface roughness. The bonding interface has a low concentration of oxide precipitates and presents two arrays dislocations respectively, due to the twist (screw dislocations) and a residual tilt angle (mixed dislocations) of the crystals. Dissociation of the screw dislocations is also observed on the lowest twist angle sample.

The increased complexity of microelectronic and sensor applications that have emerged over the past decade have driven wafer bonding to mature as a production technology for both MEMS and 3D stacked die manufacturing. The use of CMOS device wafers has restricted the types of viable bonding processes to low temperature fusion bonding, adhesive bonding and metal bonding. Due to the specific requirements of CMOS technology the allowed bonding processes had to be adapted in order to fulfill the specific CMOS-compatibility demands. This paper presents a novel single wafer Megasonic based cleaning method with enhanced process control capabilities. This cleaning process is integrated in low temperature fusion bonding process and enables higher bonding yields and a reduction in process fluid usage.

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Direct silicon wafer bonding is an attractive way to build up stacked structures. For applications, defect free bonding is required whatever the post bonding processes, which can include thermal treatment. Direct bonding processes are usually applied with hydrophilic surfaces. Thus water trapped at bonding interfaces can induce low temperature oxidation, which is a source of gas and bonding defects. The aim of this paper is to compare the efficiency of various H2O diffusion barriers, which can be elaborated onto silicon wafers before bonding. Behaviors of thin thermal silicon oxide, thermal silicon nitride and plasma induced silicon oxynitride capping layers have been evaluated and compared to a chemical oxide layer. The efficient role of thermal oxide or oxynitride layer as a H2O diffusion barrier has been pointed out.

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We performed a low temperature photoluminescence study of ultra thin single Si/SiO/sub 2/ quantum wells. We observe a strong quantum confinement effect and a high increase in the internal quantum efficiency in the thinnest wells.

Temporary bonding is a ley process for almost any 3D integration scheme. It offers not only more stability during the thinning process but also allows handling for backside processing of thin wafers like interposers during subsequent process steps [1–2]. Although the temporary bonding technology is already used in high volume manufacturing and has proven high yield process, nevertheless, some limitation appears for some specific applications [3-4-5]. One critical failure origin is delamination, which can lead to wafer breakage and therefore yield loss. This separation of the device wafer and the carrier wafer typically occurs when the temporary bonded wafer stack (device wafer, carrier wafer and temporary bonding adhesive in between) experiences further processing done under high temperature and low vacuum like PECVD deposition. Further insight into processing parameters and a better understanding of the key contributing factors as well as its dependencies help to prevent this failure. To investigate the root cause of the delamination, thermoplastic materials, which are widely used for temporary bonding and debonding applications have been used as temporary bonding adhesives in this work. Different process parameters were investigated individually but also in combination to find the origin of the delamination. These parameters include post thinning annealing temperature, which was varied up to 370C, vacuum level, thermal gradient, bow and warp and intrinsic stress of the thin device wafer. After evaluation of the main parameters affecting the delamination appearance, two extreme cases were experimented in order to check the hypothesis. The first one exhibits delaminations even using a very soft processing conditions for a temporary bonding integration and the second case is able to withstand extreme processing conditions like high temperature up to 370C under vacuum of about 1mbar without delamination appearance. In addition, during this work, the mechanical coupling existing between the carrier and the device wafer thanks to the adhesive has been investigated. Here, a thermoplastic material was used in a temporary bonded structures using wafers with different coefficients of thermal expansion (CTE). During thermal treatment, this CTE difference induce important internal stress bow of the wafer stack. The temperature dependence of the mechanical coupling is monitored during the annealing. A mechanical decoupling between the two wafers occurs when above the polymer glass transition temperature. As a result, the rheology of the thermoplastic layer is found as a contributor to the delamination mechanism. Critical combinations of process parameters in temporary bonding process are then clearly identified and will be presented in this work.

This thesis is dedicated to the study of an alternative and original method to produce strained single-crystal silicon thin film in an effort to develop a strain engineering platform for single crystal semi-conductor. Strain engineering is widely used to boost Si based transistor performance and offers outstanding possibility for the use of Complementary metal–oxide–semiconductor (CMOS) compatible semi-conductor in interesting optoelectronic applications. Usual methods used to fabricate strained semi-conductors are limited in terms of achievable strain value, strain orientation, strained surface and crystalline quality. We aim at proposing a process allowing to tune precisely deformation state (i.e., strain tensor) in a single-crystal. This process is applicable for different semi-conductors and materials and compatible with an industrial environment. The process studied here relies on temporary polymer wafer bonding, mechanical grinding, wet etching and direct bonding to transfer a single crystal silicon thin film from a Silicon On Insulator substrate to a flexible polymer, strain the crystal and bond it back on a rigid substrate. Silicon On Polymer structure were obtained with single crystal silicon thin film with a thickness ranging from 20 to 205 nm. Up to full diameter 200 mm films were transferred as well as patterned wafers. An extensive study of mechanical behavior of Silicon On Polymer (SOP) structures is provided using biaxial and uniaxial tensile test stages combined with Raman spectroscopy, digital image correlation, X-ray diffraction and Micro Laue X-ray Diffraction (μLaue). These results were used to validate a custom mechanical bench test for flexible SOP structures. Corresponding data acquisition and analysis strategies were also developed. The understanding of SOP mechanical behavior enabled the use of a bulge test apparatus to perform a direct bonding between a strained SOP and a silicon oxide die. μLaue allowed for a detailed analysis of the reported crystal. The transfer process was also adapted to functional devices and poly-crystal aluminum nitride thin films. Our custom mechanical bench test allowed the extraction of AlN Raman strain or stress coefficient in different configurations. Promising results showed that direct bonding is a suitable method to maintain a single crystal silicon thin film in a strained state after transfer from a stretched flexible polymer substrate. This can lead to some unprecedented development in strain engineering. Further work can enable the production of strained thin film of different nature, stress orientation and strain level., Cette thèse est consacrée à l’étude d’une méthode alternative et originale pour élaborer un film mince de silicium monocristallin ultra-contraint dans le but de développer une plateforme d’ingénierie de la déformation ("strain engineering") pour les semi-conducteurs monocristallins. Les contraintes sont largement utilisées pour améliorer les performances des transistors à base de silicium et offrent des possibilités exceptionnelles, notamment pour l’utilisation de semi-conducteurs compatibles Complementary metal–oxide–semiconductor (CMOS) dans des applications optoélectroniques. Les méthodes habituelles utilisées pour fabriquer des semi-conducteurs contraints sont limitées en termes de valeur de déformation, d’orientation de la contrainte, de surface déformée et de qualité cristalline. Notre objectif est de proposer un procédé permettant de contrôler précisément l’état de déformation (c’est-à-dire le tenseur de déformation) dans un monocristal. Ce procédé est applicable à différents semi-conducteurs et matériaux et est compatible avec un environnement industriel. Le procédé étudié ici repose sur le collage polymère temporaire, l’abrasion mécanique, la gravure humide et le collage direct pour transférer un film mince de silicium monocristallin d’un substrat de type silicium sur isolant à un polymère flexible. Puis le cristal est déformé en appliquant une contrainte externe et est enfin recollé sur un substrat rigide. Les structures silicium sur polymère (SOP) ont été obtenues avec des films minces de silicium monocristallin d’une épaisseur allant de 20 à 205 nm. Des films d’un diamètre total de 200 mm ont été transférés ainsi que des motifs. Une étude approfondie du comportement mécanique des structures SOP est fournie en utilisant des platines d’essai de traction biaxiale et uniaxiale combinées à la spectroscopie Raman, de la corrélation d’images numériques, la diffraction des rayons X et à la micro diffraction de Laue (μLaue). Ces résultats ont été utilisés pour valider un banc d’essai mécanique adapté aux structures silicium sur polymère flexibles. Des stratégies d’acquisition et d’analyse de données ont également été développées. L’utilisation d’une membrane sous pression (bulge test) a permis le collage direct entre un film de silicium déformé et un substrat de silicium oxydé. La diffraction des rayons X offre une analyse détaillée du cristal transféré. Le processus de transfert a également été adapté à des dispositifs fonctionnels et à des films minces de nitrure d’aluminium poly-cristallin. Notre banc d’essai mécanique a permis d’extraire le coefficient de déformation ou de contrainte Raman de l’AlN dans différentes configurations. Ces résultats prometteurs ont montré que le collage direct est une méthode appropriée pour maintenir un film mince de silicium monocristallin dans un état de contrainte après le transfert d’un substrat de polymère flexible étiré. Cela peut conduire à un développement sans précédent dans l’ingénierie de la déformation. Des travaux ultérieurs peuvent permettre la production de films minces déformés de différentes natures, orientations et niveaux de déformation.

Nowadays, the microelectronics industry is seeking to develop ever more efficient components while reducing energy consumption. Planar solutions having reached their limits, 3D structures were developed to vertically stack the circuits. This requires a perfect control of the different assembly processes in which the direct bonding of thin layers of silicon oxide deposited by PECVD constitutes an interesting alternative in the sense that it allows the elaboration at low temperature of structures integrating insulating layers composed of silicon oxide.The direct bonding of silicon oxide obtained by thermal oxidation has been widely studied in the past. However, the use of deposited PECVD silicon oxides has not been so far widespread in bonded structures. The purpose of our study was to evaluate the particularities of the silicon oxide deposited in the direct bonding framework as well as the specific mechanisms involved during sealing of the bonding interface. Since direct bonding takes place by bringing these surfaces into contact at room temperature and then generally followed byconsolidation annealing, special mechanisms will take place in the oxide volume and at the bonding interface to differentiate the behaviour of the PECVD deposited silicon oxides in bonding.In this study, we assembled different oxide configurations and showed the primordial influence of water on direct bonding. It appeared that, from the ambient temperature, the water was already impacting the bonding by modifying the physicochemical and mechanical properties of the oxide subsurface. At higher temperatures, the water migrates from the oxide volume to the bonding interface allowing the closing of the bonding interfaceby exacerbating the above oxide properties. The water resulting from the closing of the bonding interface is then either stored inside cavities forming at the bonding interface or discharged into the oxide subsurface dependingon the type of oxide. It was also shown that the deposited oxide had a relatively balanced water concentration profile and could contain a significant amount of water. These findings have led to the development of two-layerstructures optimized for direct bonding. Understanding these different mechanisms provides new insights into the use of direct bonding processes for future applications.; De nos jours, l’industrie de la microélectronique cherche à développer des composants toujours plus performants tout en réduisant la consommation d’énergie. Les solutions planaires ayant atteint leurs limites, desstructures 3D furent développées afin d’empiler verticalement les circuits. Cela nécessite une parfaite maitrise des différents procédés d’assemblage au sein desquels le collage direct de couches minces d’oxyde de silicium déposées par PECVD constitue une alternative intéressante en ce sens qu’elle permet l’élaboration à basse température de structures intégrant des couches isolantes composées d’oxyde de silicium.Le collage direct d’oxyde de silicium obtenu par voie thermique fut largement étudié par le passé. Cependant, l’utilisation d’oxyde de silicium obtenu par voie de dépôt PECVD fut jusqu’ici peu répandu dans les structures collées. L’objet de notre étude fut d’évaluer les particularités de l’oxyde de silicium déposé dans le cadre du collage direct ainsi que les mécanismes spécifiques mis en jeu lors du scellement de l’interface de collage. Le collage direct s’effectuant par la mise en contact de ces surfaces à température ambiante, puis étant généralement suivi d’un recuit de consolidation, des mécanismes particuliers auront lieu dans le volume de l’oxyde ainsi qu’à l’interface de collage permettant de différencier le comportement des oxydes déposés en collage.Dans cette étude, nous avons assemblés différentes configurations d’oxydes et montré l’influence primordiale de l’eau sur le collage direct. Il est apparu que, dès la température ambiante, cette dernière impactait déjà le collage en modifiant les propriétés physicochimiques et mécaniques de la subsurface de l’oxyde. A plus haute température, l’eau migre du volume de l’oxyde vers l’interface de collage permettant la fermeture de l’interface de collage en exacerbant les propriétés de l’oxyde précités. L’eau résultant de la fermeture de l’interface de collage est alors soit stockée à l’intérieur de cavités se formant à l’interface de collage, soit évacuée dans la subsurface de l’oxyde suivant la typologie de celui-ci. Il a également été montré que l’oxydedéposé disposait d’un profil de concentration d’eau relativement équilibré et qu’il pouvait contenir une quantité importante d’eau. Ces constations ont permis l’élaboration de structures bicouches optimisées pour le collage direct. La compréhension de ces différents mécanismes apporte un nouvel éclairage dans l’utilisation des procédés de collage direct pour les applications du futur.

Nowadays, the microelectronics industry is seeking to develop ever more efficient components while reducing energy consumption. Planar solutions having reached their limits, 3D structures were developed to vertically stack the circuits. This requires a perfect control of the different assembly processes in which the direct bonding of thin layers of silicon oxide deposited by PECVD constitutes an interesting alternative in the sense that it allows the elaboration at low temperature of structures integrating insulating layers composed of silicon oxide.The direct bonding of silicon oxide obtained by thermal oxidation has been widely studied in the past. However, the use of deposited PECVD silicon oxides has not been so far widespread in bonded structures. The purpose of our study was to evaluate the particularities of the silicon oxide deposited in the direct bonding framework as well as the specific mechanisms involved during sealing of the bonding interface. Since direct bonding takes place by bringing these surfaces into contact at room temperature and then generally followed byconsolidation annealing, special mechanisms will take place in the oxide volume and at the bonding interface to differentiate the behaviour of the PECVD deposited silicon oxides in bonding.In this study, we assembled different oxide configurations and showed the primordial influence of water on direct bonding. It appeared that, from the ambient temperature, the water was already impacting the bonding by modifying the physicochemical and mechanical properties of the oxide subsurface. At higher temperatures, the water migrates from the oxide volume to the bonding interface allowing the closing of the bonding interfaceby exacerbating the above oxide properties. The water resulting from the closing of the bonding interface is then either stored inside cavities forming at the bonding interface or discharged into the oxide subsurface dependingon the type of oxide. It was also shown that the deposited oxide had a relatively balanced water concentration profile and could contain a significant amount of water. These findings have led to the development of two-layerstructures optimized for direct bonding. Understanding these different mechanisms provides new insights into the use of direct bonding processes for future applications., De nos jours, l’industrie de la microélectronique cherche à développer des composants toujours plus performants tout en réduisant la consommation d’énergie. Les solutions planaires ayant atteint leurs limites, desstructures 3D furent développées afin d’empiler verticalement les circuits. Cela nécessite une parfaite maitrise des différents procédés d’assemblage au sein desquels le collage direct de couches minces d’oxyde de silicium déposées par PECVD constitue une alternative intéressante en ce sens qu’elle permet l’élaboration à basse température de structures intégrant des couches isolantes composées d’oxyde de silicium.Le collage direct d’oxyde de silicium obtenu par voie thermique fut largement étudié par le passé. Cependant, l’utilisation d’oxyde de silicium obtenu par voie de dépôt PECVD fut jusqu’ici peu répandu dans les structures collées. L’objet de notre étude fut d’évaluer les particularités de l’oxyde de silicium déposé dans le cadre du collage direct ainsi que les mécanismes spécifiques mis en jeu lors du scellement de l’interface de collage. Le collage direct s’effectuant par la mise en contact de ces surfaces à température ambiante, puis étant généralement suivi d’un recuit de consolidation, des mécanismes particuliers auront lieu dans le volume de l’oxyde ainsi qu’à l’interface de collage permettant de différencier le comportement des oxydes déposés en collage.Dans cette étude, nous avons assemblés différentes configurations d’oxydes et montré l’influence primordiale de l’eau sur le collage direct. Il est apparu que, dès la température ambiante, cette dernière impactait déjà le collage en modifiant les propriétés physicochimiques et mécaniques de la subsurface de l’oxyde. A plus haute température, l’eau migre du volume de l’oxyde vers l’interface de collage permettant la fermeture de l’interface de collage en exacerbant les propriétés de l’oxyde précités. L’eau résultant de la fermeture de l’interface de collage est alors soit stockée à l’intérieur de cavités se formant à l’interface de collage, soit évacuée dans la subsurface de l’oxyde suivant la typologie de celui-ci. Il a également été montré que l’oxydedéposé disposait d’un profil de concentration d’eau relativement équilibré et qu’il pouvait contenir une quantité importante d’eau. Ces constations ont permis l’élaboration de structures bicouches optimisées pour le collage direct. La compréhension de ces différents mécanismes apporte un nouvel éclairage dans l’utilisation des procédés de collage direct pour les applications du futur.

Coupled electrokinetic phenomena within nanochannel are of interest for energy harvestingand production of electricity based on the controlled mixing of river water with sea water known as "blue energy". The origin of the phenomena is related to interaction with charged walls and transport of ions within the so called Debye layer. This work aims at a better understanding of the physics and transport phenomena in this layer associated with solution confined in nanochannel.A specific instrumentation has been developed during this thesis to study the mechanisms governing coupled nanofluics fluxes. The idea is to characterize simultaneously the mass transport within the nanochannel and the electrical current driven through the nanochannel by the application of either salinity difference , pressure difference or voltage difference across the channel. The thesis is divided into three parts.In the first part, a custom made flow cell and experimental conditions to control and measure various fluxes is presented. The capability of cell to measure current or voltage under applied pressure or salinity gradient is presented taking the benefit of commercial nanoporous Nafion membrane.The second part is focused on an easy way of preparation of nanochannel sample in the form of single chip, in which nanochannel is interfaced to micro and macroscopic world. A well-controlled, 1.4µm long nanochannel of conical geometry with a maximum aspect ratio of 10 is fabricated. The minimum apex size of nanochannel achieved here is 50 nm which is about 30 times less than the length of channel. The presence of electrode directly at the interface of nano to micro cavity allow to perform electrical characterization of nanochannel with high precision.The third part of the thesis is devoted to the development of a method for the direct measurement of flow rate as low as 10 pL/min across a single nanochannel. This measurement approach combined with electrical measurement, could be used, in presence of pressure, voltage or salinity gradient, to measure the flow rate and the electrical current across a single nanochannel simultaneously and independently.; Les phénomènes électrocinétiques couplés au sein d'un nanocanal sont d'intérêt pour la conversion d'énergie et la production d'électricité reposant sur le mélange contrôlé d'eau douce et d'eau salée aussi appelée "énergie bleue". L'origine des phénomènes est lié à l'interaction avec des parois chargées et au transport d'ions au sein de ce qu'on nomme les couches de Debye. Ce travail vise à une meilleure compréhension de la physique et des phénomènes de transport dans ces couches dans le cadre de solutions confinées dans des nanocanaux.Une instrumentation spécifique a été développée pendant la thèse pour étudier les mécanismes qui gouvernent ces flux couplés. L'idée est de caractériser simultanément le transport de masse et le courant électrique au sein d'un nanocanal soumis à une différence de salinité de pression ou de tension électrique. Ce travail est divisé en trois parties.Dans la première partie, est décrite une cellule conçue pour la mesure et le contrôle de courant et tension électrique en présence de différence de pression ou de salinité au bornes d'un nanopores. L'utilisation de la cellule est illustrer dans le cas d'une membrane nanoporeuse de nafion.La seconde partie est focalisée sur une méthode simple de préparation d'un nanocanal directement connectable à un dispositif macroscopique. Le nanocanal, d'un micromètre de long, présente une géométrie conique, d'angle ajustable, et des extrémités équipées d'électrode déposées par pulvérisation cathodique.La troisième partie, concerne le développement d'une méthode pour la mesure directe de débit jusqu'à 10 pL/min s'écoulant au sein d'un nanocanal. Cette méthode combinée à une caractérisation électrique, pourra être utilisée, en présence de gradient de pression, de tension ou de salinité pour mesurer le débit et le courant électrique au sein d'un nanocanal de manière simultanée et indépendante.

Direct wafer bonding refers to the spontaneous establishment of attractive forces between two surfaces at ambient temperature without any additional polymer material. Available at ambient pressure or under vacuum, this technology is attractive for monocrystal-amorphous stacks, perfectly illustrated by SOI (Silicon On Insulator) substrate elaboration widely used nowadays in microelectronics or microtechnologies. Electronic device performance and multidisciplinarity needs require this technology on many different materials. In this context, a precis understanding of bonding mechanism is paramount. The aim of this work is to study the hydrophilic bonding mechanisms for alumina, nitride silicon and ultra-low k thin films.In this study, hydrophilic bonding of deposited dielectric films prepared by chemical treatment were analyzed as function of post-bonding annealing temperature. Chemical and mechanical bonding interface closure has been analyzed from mechanical and chemical point of view via several characterization techniques: anhydrous bonding energy measurement, acoustic microscopy, X-Ray reflectivity and infrared spectroscopy. Each material demonstrates interesting behaviors embedded at the bonding interface compared to the deposited film free surfaces. Throughout the studies, correlations between bonding and free surface evolution have led to their bonding mecanisms and some recommendations for efficient and high quality bonding elaboration., Le collage direct consiste à l’adhésion spontanée dès température ambiante de deux surfaces sans ajout de matière polymère à l’interface de collage. Réalisable sous vide ou à pression atmosphérique, il possède l’avantage de permettre l’empilement de matériaux monocristallins sur des matériaux amorphes, parfaitement illustrée, par exemple, avec la fabrication de substrats SOI (silicium sur isolant) couramment utilisé de nos jours en microélectronique et/ou en microtechnologie. La course à la performance et/ou pluridisciplinarité des circuits électroniques nécessite la maîtrise de ce procédé pour un plus large panel de matériaux. La compréhension des mécanismes physico-chimique à l’interface de collage devient alors primordiale. L’objectif de cette thèse est d’étudier les mécanismes mis en jeu dans le collage direct hydrophile de couches diélectriques autres que l’oxyde de silicium : l’oxyde d’aluminium, le nitrure de silicium et un ultra-low k.Dans cette étude, des procédés de collage direct hydrophile de films diélectriques déposés sont développés avec différentes préparations de surface. L’évolution mécanique et chimique de l’interface de collage, après différents traitements thermiques, est analysé via différentes techniques de caractérisation comme la mesure anhydre d’énergie de collage, la microscopie acoustique, la réflectivité des rayons X et la spectroscopie infrarouge. Chaque matériau démontre un comportement particulier une fois confiné à l’interface de collage par rapport à son comportement en surface libre. Tout au long de cette thèse, le lien entre collage et surface libre a permis d’établir les mécanismes de collages des différents matériaux étudiés et d’énoncer des recommandations pour obtenir des collages de qualité.

Coupled electrokinetic phenomena within nanochannel are of interest for energy harvestingand production of electricity based on the controlled mixing of river water with sea water known as "blue energy". The origin of the phenomena is related to interaction with charged walls and transport of ions within the so called Debye layer. This work aims at a better understanding of the physics and transport phenomena in this layer associated with solution confined in nanochannel.A specific instrumentation has been developed during this thesis to study the mechanisms governing coupled nanofluics fluxes. The idea is to characterize simultaneously the mass transport within the nanochannel and the electrical current driven through the nanochannel by the application of either salinity difference , pressure difference or voltage difference across the channel. The thesis is divided into three parts.In the first part, a custom made flow cell and experimental conditions to control and measure various fluxes is presented. The capability of cell to measure current or voltage under applied pressure or salinity gradient is presented taking the benefit of commercial nanoporous Nafion membrane.The second part is focused on an easy way of preparation of nanochannel sample in the form of single chip, in which nanochannel is interfaced to micro and macroscopic world. A well-controlled, 1.4µm long nanochannel of conical geometry with a maximum aspect ratio of 10 is fabricated. The minimum apex size of nanochannel achieved here is 50 nm which is about 30 times less than the length of channel. The presence of electrode directly at the interface of nano to micro cavity allow to perform electrical characterization of nanochannel with high precision.The third part of the thesis is devoted to the development of a method for the direct measurement of flow rate as low as 10 pL/min across a single nanochannel. This measurement approach combined with electrical measurement, could be used, in presence of pressure, voltage or salinity gradient, to measure the flow rate and the electrical current across a single nanochannel simultaneously and independently., Les phénomènes électrocinétiques couplés au sein d'un nanocanal sont d'intérêt pour la conversion d'énergie et la production d'électricité reposant sur le mélange contrôlé d'eau douce et d'eau salée aussi appelée "énergie bleue". L'origine des phénomènes est lié à l'interaction avec des parois chargées et au transport d'ions au sein de ce qu'on nomme les couches de Debye. Ce travail vise à une meilleure compréhension de la physique et des phénomènes de transport dans ces couches dans le cadre de solutions confinées dans des nanocanaux.Une instrumentation spécifique a été développée pendant la thèse pour étudier les mécanismes qui gouvernent ces flux couplés. L'idée est de caractériser simultanément le transport de masse et le courant électrique au sein d'un nanocanal soumis à une différence de salinité de pression ou de tension électrique. Ce travail est divisé en trois parties.Dans la première partie, est décrite une cellule conçue pour la mesure et le contrôle de courant et tension électrique en présence de différence de pression ou de salinité au bornes d'un nanopores. L'utilisation de la cellule est illustrer dans le cas d'une membrane nanoporeuse de nafion.La seconde partie est focalisée sur une méthode simple de préparation d'un nanocanal directement connectable à un dispositif macroscopique. Le nanocanal, d'un micromètre de long, présente une géométrie conique, d'angle ajustable, et des extrémités équipées d'électrode déposées par pulvérisation cathodique.La troisième partie, concerne le développement d'une méthode pour la mesure directe de débit jusqu'à 10 pL/min s'écoulant au sein d'un nanocanal. Cette méthode combinée à une caractérisation électrique, pourra être utilisée, en présence de gradient de pression, de tension ou de salinité pour mesurer le débit et le courant électrique au sein d'un nanocanal de manière simultanée et indépendante.