101. Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes.
- Author
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Mayahinia, Mahta, Marinelli, Tommaso, Pei, Zhenlin, Liu, Hsiao-Hsuan, Pan, Chenyun, Tokei, Zsolt, Catthoor, Francky, and Tahoori, Mehdi B.
- Abstract
To deal with stagnated performance and energy improved by successive technology scaling, system-technology co-optimization (STCO) comes as a rescue which involves the co-optimization of the important system parameters from the high-level application all the way down to the low-level technology. This article addresses the interconnect dominance issue in advanced nodes as a bottleneck in energy-efficient static RAM (SRAM)-based last-level cache (LLC) and aims to mitigate it through an STCO mechanism. Our main approach in this work is the utilization of a workload-aware controlled dynamic segmented bus (DSB) as the intramacro (interbanks) interconnect. Based on our results, our approach can improve the energy efficiency of the SRAM-based LLC by an average of 35%. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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