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The confined states in [001]-oriented strained silicon layers embedded in oxide are investigated using dasiafull-zonepsila k.p analysis within the envelop function approximation and Tight-Binding (TB) model. Calculations of important transport parameters - energy band shifts and transport masses - show new results, rising the issues of the limit of simple models like the Effective Mass Approximation (EMA).

The holes confined states in [001] -oriented 5 nm-thick relaxed silicon layer embedded in oxide are investigated using full-band k.p method within the envelop function approximation. Full-band calculations of important transport parameters - energy band shifts, curvature masses and density-of-state masses - show new results, rising the issues of the limit of simple models like the Effective Mass Approximation (EMA) and the 6-level k.p model.

The confined states in ultra-thin Ge layers on oxide are investigated using three different state-of-the-art full-band methods. Contrary to the prediction of the simple effective mass approximation (EMA) and multiband-models that decoupled the Conduction Bands (CB) and the Valence Bands (VB), full-band calculations predicts much lower subband energy shifts due to quantum confinement.

The electronic energy band structure of strained and unstrained Si, Ge, and $\mathrm{SiGe}$ alloys is examined in this work using a 30-level $\mathbit{k}∙\mathbit{p}$ analysis. The energy bands are at first obtained with ab initio calculations based on the local-density approximation of density-functional theory, including a $GW$ correction and relativistic effects. The so-calculated band structure is then used to extract the unknown $\mathbit{k}∙\mathbit{p}$ fitting parameters with a conjugate-gradient optimization procedure. In a similar manner, the results of ab initio calculations for strained materials are used to fit the unknown deformation potentials that are included in the present $\mathbit{k}∙\mathbit{p}$ Hamiltonian following the Pikus-Bir correction scheme. We show that the present $\mathbit{k}∙\mathbit{p}$ model is an efficient numerical method, as far as computational time is concerned, which reproduces accurately the overall band structure, as well as the bulk effective density of states and the carrier effective masses, for both strained and unstrained materials. As an application, the present 30-level $\mathbit{k}∙\mathbit{p}$ model is used to describe the band offsets and the variations of the carrier effective masses in the strained ${\mathrm{Si}}_{1\ensuremath{-}x}{\mathrm{Ge}}_{x}∕{\mathrm{Si}}_{1\ensuremath{-}y}{\mathrm{Ge}}_{y}$ system.

Recent works have shown that accurate bandstructure for strained silicon can be obtained using full-zone k.p method [1]. In this paper we have performed full-band Monte Carlo transport simulations in strained silicon using k.p band structure [1], and we have compared to simulations performed using the well-benchmarked EPM band structure [2][3][4].

Capacitance measurements have been performed on strained Si on relaxed Si/sub 0.8/Ge/sub 0.2/ buffer and compared to self-consistent solution to Poisson-Schrodinger equations accounting for the silicon electronic band structure. The electronic structure of strained Si on Si/sub 1 -x/Ge/sub x/ buffer is examined using 30-level k.p analysis including spin orbit correction. The effective masses, the band gap shifts and the carrier densities are reported for various Ge concentrations. As a result, good agreement between the measurements and the simulations is obtained within the framework of our model and the impact of strained Si layer on the MOSFET capacitance is explained from accumulation to inversion regime.

We present measurements of GIDL at various temperatures and terminal biases. Besides band-to-band (BBT) tunneling leakage observed at high drain-to-gate voltage V/sub DG/, we also observed trap-assisted-tunneling (TAT) leakage currents at lower V/sub DG/. Based on ISE TCAD simulations of the electric field, we propose analytical models for BBT and TAT GIDL currents suitable for compact modelling.

SiGe material brings outstanding advantages for pMOS transistors [1,2]. Low Vt values are much easier to control thanks to specific band structure. The strain induced by engineering of lattice mismatch with silicon leads to enhanced mobility and performances. However a lot remains to understand in these processes and performances. This paper puts the light on two effects: (1) an unexpected Vt shift induced by Ge and (2) the relative impact of Ge, strain and defects on the mobility gain. Many SiGe processes and architectures have been studied to allow clear and reproducible conclusions: (1) pMOS with a given Ge content and various stack thicknesses; (2) pMOS with a given stack and various Ge compositions; (3) SiGe pMOS performed by epitaxy or by Ge-enrichment technique, from unstrained or strained Si substrate, leading to various combinations of stress and Ge content. Both bulk and SOI devices have been processed. Data have been analyzed in a global and coherent view, thus avoiding addressing non pertinent data. Extra Ge-induced Vfb shift: Advanced simulations have been performed using UTOX simulator [3,4]. 6×6 kp simulations and Poisson Schrodinger allow to simulate band structures with strain effects for all %Ge as well as electrical C(V) responses. Comparison between simulations and experiments indicates an extra Vt shift which is not expected from the band structure (Fig.1). This shift is proportional to %Ge content in the channel; it has been observed on SOI and Bulk devices. The analysis of the various gate stack thicknesses rules out an effect of charges in the stacks or at the interfaces. All the electrical data lead to a behavior explained with a Ge induced dipole at the SiGe/SiON interface. Detailed SIMS analysis (Fig.2) as well as STEM, EELS, HAADF experiments show a slight Ge diffusion in SiON probably explaining the dipole at this interface. Notice that this diffusion does not reach the SiON/HfO2 interface and the other existing dipole at this interface [5]. This result is essential for future devices design and modeling, as the extra shift is in the range of the expected Vt (~0.2V). Mobility on strained pMOS: The described processes induce an initial biaxial compressive stress in SiGe layer. This stress improves significantly the channel hole mobility. Meanwhile Ge atoms degrade the SiGe/SiON interface and increase the interface states density Dit (Fig.3). These Dit are related to Ge diffusion in SiON and induce dipoles. However they have no direct effect on Vt. Using the various technological splits available we have compared splits with similar final strain but different concentrations of Ge (Fig.4). This shows that the strain generated by lattice mismatch has a 1storder effect. The percentage of Ge itself as well as generated dipoles and Dit play a minor role, at least at the low %Ge (≤30%). At higher %Ge this is no more true and the gain by strain is counter-balanced by the interface degradation. An improvement of process is required to maintain a good interface quality. Real devices have 10-20 nm length and width. In this case the strain can relaxed depending on directions and may significantly increase or decrease the performances. A careful strain engineering is then expected. This will be discussed in the final paper. References: [1] H. Rusty Harris et al, VLSI, p.154, 2007. [2] S. Takagi et al, IEEE TED, p.21, 2008. [3] D. Rideau et al, ULIS, p.63, 2008. [4] A. Soussou et al, Micro.Eng., 109, p.282, 2013. [5] M. Charbonnier et al., IEEE TED, p. xx, 2010. Acknowledgment: This work was supported by the Places2be project.

High-energy transport properties of charge carriers in ternary random Si1−x−yGexCy alloys are investigated using Full-Band Monte Carlo simulations. Models for scattering mechanisms include phonon scattering, impact ionization and alloy scattering. Phonon scattering rates are wave-vector dependent and calculated consistently with the Full-Band structure. Impact ionization rates are modeled using analytical Keldysh formulas fitted to previously reported ab initio results. We derive a model for alloy scattering rate specific to ternary random alloys. It involves 2 effective alloy potentials which are independently calibrated on experimental mobility measurements. Presented Monte Carlo simulation results are shown to be in very good agreement with a variety of high-energy transport measurements, including drift velocities, impact ionization coefficients and quantum yields. Effects of alloy composition on the electrical characteristics of Si1−x-yGexCy alloys are investigated.

Complementary MOS device electrical performances are considerably affected by the degradation of the oxide lay- ers and Si/SiO2 interfaces. A general expression for electrically stressed MOS impedance has been derived and applied within the nonradiative multiphonon theory of carrier capture/emission at oxide defects. The capacitance and the conductance of aged MOS field-effect transistor oxides, and their dependences on bias voltage, temperature, and stress conditions have been investigated.

The advantages and drawbacks of Capacitance vs Voltage (CV) characteristics, trap-assisted gate leakage tunneling and multi-frequency charge pumping techniques, have been brought out through an attentive investigation of oxide defects in CMOS technologies. To this purpose, the importance of the extension of the accessible regions of the oxide in energy and depth and the influence of model parameters, are discussed using a novel methodology based on a multiphonon charge trapping model. The significant differences found in the probed regions and their localization in the oxide extracted with the three techniques constitutes an important information for process development and oxide quality optimization.

A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. The device equations account for charge balance effects on the isolated floating gate node and parasitic couplings between the terminals of the memory cell. The compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb and memory endurance degradation due to oxide aging. After validation, the model has been applied to parametric analysis and used to evaluate critical trade-offs in memory design. (C) 2013 Elsevier Ltd. All rights reserved.

Multifrequency charge pumping analysis has been performed using a multiphonon-assisted charge trapping model in the view of analyzing the oxide region in energy and position that can be characterized using charge pumping (CP) characterization. Transient phenomena observed during CP and ac characterization (hysteresis loops) have been modeled, and the role of out-of- equilibrium quasi-Fermi levels in proximity of the Si/SiO2 inter- face has been studied in detail.

Transient and endurance mechanisms in highperformance embedded non-volatile memory flash devices are investigated in detail. An extraction methodology combining measurements on equivalent transistors and flash cells is proposed to discriminate the effects of defects on program/erase (P/E) efficiencies and on DC characteristics. A semi-analytical multiphonon-assisted charge trapping model is used to investigate the role and the impact of trapped charges on channel hotelectron injection and Fowler-Nordheim efficiencies, threshold voltage variations and endurance characteristics. © 2011 IEEE.

Single-photon avalanche diodes (SPADs) emerged as the most convenient photodetectors for many photon-counting applications, taking advantage of their high detection efficiencies and fast timing responses. Over the past years, their design rules have been evolving to reach more aggressive performances. Usually, trade-offs are required to meet the different constraints.To face these technological challenges, the development of reliable models to describe the device operation and predict the relevant figures-of-merit is compulsory. Evidently, the numerical solvers must be both physics-based and computationally efficient.This Ph.D. work aims to improve the modeling of silicon SPADs, focusing on the avalanche build-up and the quenching efficiency. After a state-of-the-art overview, we investigate various device architectures and potential technological improvements using TCAD methods. We highlight the role of calibrated models and scalability laws in predicting the electrical response.Furthermore, we present a Verilog-A model accounting for the temporal current build-up in SPADs. The important parameters of this model are fitted on TCAD mixed-mode predictions. Importantly, the resulting SPICE simulations of the quenching compare favorably with measurements, allowing a pixel designer to optimize circuits.Since standard TCAD tools are based on deterministic models, the stochastic description of carriers is limited. Hence, Monte Carlo algorithms are used to simulate the statistical behavior of these photodiodes, with a particular attention on the photon detection efficiency and timing jitter. The good agreement between simulation results and experiments confirms the method's accuracy, and demonstrates its ability to assist the development of new generation SPADs.; Les diodes à avalanche à photon unique (SPAD) sont apparues comme les photodétecteurs les plus pratiques pour de nombreuses applications de comptage de photons, tirant parti de leurs efficacités de détection élevées et de leurs réponses rapides. Au cours des dernières années, leurs règles de conception ont évolué pour atteindre des performances plus agressives. Habituellement, des compromis sont nécessaires pour répondre aux différentes contraintes.Pour faire face à ces défis technologiques, le développement de modèles fiables pour décrire le fonctionnement du dispositif et prédire les facteurs de mérite pertinents est obligatoire. De toute évidence, les solveurs numériques doivent être à la fois basés sur la physique et efficaces en terme de calcul.Les travaux de cette thèse visent à améliorer la modélisation des SPADs en silicium, en se concentrant sur l'accumulation de l'avalanche et l'efficacité de son extinction. Après un aperçu de l'état de l'art, nous étudions différentes architectures de ces dispositifs et les potentielles améliorations technologiques à l'aide des méthodes TCAD. Nous soulignons le rôle des modèles calibrés et des lois de scalabilité dans la prédiction de la réponse électrique.De surcroît, nous présentons un modèle Verilog-A pour simulater l'accumulation temporelle du courant dans les SPADs. Les paramètres importants de ce modèle sont ajustés aux prédictions TCAD. Les simulations SPICE résultantes se comparent favorablement aux mesures, permettant à un concepteur d'imageurs à base de SPADs d'optimiser les circuits.Vu que les outils TCAD standards sont basés sur des modèles déterministes, la description stochastique des porteurs est limitée. Par conséquent, des algorithmes Monte Carlo sont utilisés pour simuler le comportement statistique de ces photodiodes, avec une attention particulière portée à l'efficacité de la détection de photons et la résolution temporelle. Le bon accord entre les résultats de simulation et ceux de l'expérimentation témoigne de la précision de la méthode, et démontre sa capacité à aider au développement des nouvelles générations de SPADs.

One of the most important device for semiconductor industry nowadays is the Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) which is hugely applied in the development of a vast number of electronic applications. The downscaling of MOSFET geometry has been a very successful process to improve the performances of Complementary Metal-Oxide Semiconductor (CMOS) devices. The scaling of transistors dimensions according to scaling rules enabled the performance improvements up to the 90 nm technology node, but the continuous shrinking of MOSFET dimensions faces both physical and economical limitations. In order to overcome these limitations and achieve the performance requirement, several “boosters” have been explored by the semiconductor industries, notably the use of alternative device structures such as “Fully Depleted Silicon On Insulator” (FDSOI), whose architecture has been chosen to be explored in this work.For advanced CMOS technology, robust and predictive electronic transport modeling is a major concern. This PhD work intended to improve the device modeling for ultimate FDSOI devices, with a particular focus on carrier transport. In this scenario, Technological Computer-Aided Design (TCAD) based on Density-Gradient and Drift-Diffusion models arise as a fast and powerful tool to support the technological development within the industry, however we have shown that their accuracy for predicting advanced nodes is often doubtful. In order to overcome this issue, we presented a two-dimensional simulation tool (UTOXPP) based on physical models which makes use of state of the art C++ architecture and accounts for a complete and friendly GUI. By means of Finite-Difference method, we describe a complete modeling strategy for the most important parts of the solver, namely 1.5D Poisson-Schrödinger, Quantum Drift-Diffusion and the mobility models from Kubo-Greenwood formulation and Nonequilibrium Green’s function (NEGF). Simulation results showed the efficiency of UTOXPP for solving electrostatics and the quantum effects for both carrier distribution and transport for the given devices. The objective of this PhD work has been achieved as UTOXPP delivers reliable results for advanced nodes in a timely manner, being an excellent choice for the industrial daily use., Parmi les plus important dispositifs pour l'industrie des semi-conducteurs, le transistor “Metal Oxide Semiconductor Field-Effect Transistor” (MOSFET) est largement utilisé pour le développement d'un grand nombre d'applications électroniques. La miniaturisation de ces dispositifs MOSFET a été un processus très efficace pour améliorer la performance de la technologie “Complementary Metal-Oxide Semiconductor” (CMOS). La mise à l'échelle des transistors selon “scaling rules” a permis l'amélioration des performances jusqu'à nœud technologique 90 nm, mais la diminution continue des dimensions MOSFET fait face à des limitations physiques et économiques. Afin de surmonter ces limitations et de parvenir à l'exigence de performance, plusieurs “boosters” ont été explorées par l’industrie des semi-conducteurs, notamment l'utilisation de dispositifs efficaces tel que "Fully Depleted Silicon On Insulator" (FDSOI), dont l'architecture a été choisie pour être explorée dans ce travail.Pour la technologie CMOS ultime, la modélisation fiable du transport électronique est une préoccupation majeure. Ce travail de thèse vise à améliorer la modélisation de dispositifs ultimes FDSOI, concentré sur le transport des porteurs. Dans ce scénario, “Technological Computer-Aided Design” (TCAD) basé sur des modèles Densité-Gradient et de Dérive-Diffusion se présente comme un outil rapide et puissant pour soutenir le développement technologique dans le secteur technologique. Cependant, nous avons montré que leur précision pour prédire les nœuds avancés est souvent douteuse. Afin de surmonter ce problème, nous avons présenté un outil de simulation à deux dimensions (UTOXPP) basé sur des modèles physiques et qui est implementé sur une efficace architecture C++ avec une bonne interface graphique. Au moyen de la méthode Finite-Difference, nous décrivons une stratégie de modélisation complète pour les parties les plus importantes de ce outil, à savoir 1.5D Poisson-Schrödinger, Quantum Drift-Diffusion et les modèles de mobilité de la formulation Kubo-Greenwood et de la fonction de Green hors equilibrium (NEGF). Les résultats de simulation ont montré l'efficacité de UTOXPP pour résoudre les effets quantiques à la fois pour la distribution de charge et également pour le transport des dispositifs choisis. L'objectif de ce travail de thèse a été réalisée puisque UTOXPP se montré capable de fournir des résultats fiables et rapides pour les nœuds avancés, raison d'être un excellent choix pour l'usage quotidien dans la industrie.

Maintaining good threshold voltage (VT) centering is a paramount challenge for CMOS technology. The SiGe introduction in bulk and FDSOI pFETs requires VT control for such devices. To this end, we have to extract accurately electrical parameters and to understand Ge integration effects in SiGe based pFETs. In this thesis, first, we have proposed extraction methods to determine VT, flat band voltage (VFB) and equivalent oxide thickness (EOT) parameters in bulk and FDSOI transistors. The extraction methods have been validated via Poisson-Schrodinger (PS) simulations and successfully applied to measurements. Second, we have highlighted and explained electric effects of Ge on pMOS gate stack parameters. Electrical characterizations compared with PS simulations have evidenced an additional effective work function increase, induced by Ge, related to interfacial dipoles. STEM, EELS and SIMS characterizations have demonstrated that dipoles are located at SiGe/IL interface., L'introduction du SiGe dans les pMOS (Bulk et FDSOI) exige un bon contrôle de la tension de seuil (VT). Ceci nécessite une extraction précise des paramètres électriques ainsi qu'une compréhension des effets électriques du Ge dans de tels dispositifs. Dans cette thèse, nous avons d'abord proposé des méthodes pour une identification précise des paramètres électriques du « gate stack »: VT, la tension de bande plate (VFB) et l'épaisseur équivalente d'oxyde (EOT). Ces méthodes ont été validées avec des simulations Poisson-Schrödinger (PS) et appliquées avec succès aux mesures. Dans un second temps, nous avons étudié les effets électriques du Ge sur les paramètres du « gate stack » des pMOS. La comparaison des caractérisations électriques (C-V) avec les simulations PS a montré un décalage supplémentaire du travail de sortie effectif qui croit avec le Ge. Des caractérisations STEM, EELS et SIMS ont prouvé que ce décalage est due à la présence de dipôles à l'interface SiGe/oxyde.