395 results on '"Cheng-Kok Koh"'
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102. Repeater block planning under simultaneous delay and transition time constraints.
103. Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration.
104. A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits.
105. Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation.
106. A two-dimensional domain decomposition technique for the simulation of quantum-scale devices.
107. Routability-driven repeater block planning for interconnect-centric floorplanning.
108. UST/DME: A Clock Tree Router for General Skew Constraints.
109. A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise.
110. Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits.
111. Frequency Domain Analysis of Switching Noise on Power Supply Network.
112. Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures.
113. Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.
114. Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.
115. Power minimization by simultaneous dual-Vth assignment and gate-sizing.
116. A parallel branch-and-cut approach for detailed placement.
117. Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing.
118. Optimal Double Via Insertion With On-Track Preference.
119. A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks.
120. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
121. Tolerating process variations in large, set-associative caches: The buddy cache.
122. Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
123. Fast and Optimal Redundant Via Insertion.
124. Interconnect layout optimization under higher-order RLC model.
125. Global interconnect sizing and spacing with consideration of coupling capacitance.
126. Interconnect design for deep submicron ICs.
127. Routability-Driven Placement and White Space Allocation.
128. SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
129. Simultaneous buffer and wire sizing for performance and power optimization.
130. Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors.
131. Performance analysis of latency-insensitive systems.
132. Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction.
133. Postlayout optimization for synthesis of Domino circuits.
134. Bounded-skew clock and Steiner routing under Elmore delay.
135. Minimum-Cost Bounded-Skew Clock Routing.
136. Mixed block placement via fractional cut recursive bisection.
137. Synthesis of skewed logic circuits.
138. Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
139. Simultaneous driver and wire sizing for performance and power optimization.
140. On-chip interconnect modeling by wire duplication.
141. Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.
142. UST/DME: a clock tree router for general skew constraints.
143. Routability-driven repeater block planning for interconnect-centricfloorplanning.
144. Interconnect sizing and spacing with consideration of couplingcapacitance.
145. Interconnect layout optimization under higher order RLC model forMCM designs.
146. Bounded-skew clock and Steiner routing.
147. Performance optimization of VLSI interconnect layout.
148. Saath: Speeding up CoFlows by Exploiting the Spatial Dimension
149. A parallel direct solver for the simulation of large-scale power/ground networks
150. Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design.
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