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Extremely narrow and bulk-like p-type InAs–Si nanowire TFETs are studied using (i) a full-band and atomistic quantum transport simulator based on the sp 3 d 5 s ∗ tight-binding model and (ii) a drift–diffusion TCAD tool. As (iii) option, a two-band model and the WKB approximation have been adapted to work in heterostructures through a careful choice of the imaginary dispersion. It is found that for ultra-scaled InAs–Si nanowire TFETs, the WKB approximation and the quantum transport results agree very well, suggesting that the former could be applied to larger hetero-TFET structures and considerably reduce the simulation time while keeping a high accuracy.

The growth of III-V semiconductors on Si generates defects at the III-V/Si interface which are known to degrade the performance of electronic devices where this interface is an active region. This paper presents a density functional theory based analysis of the InAs/Si interface with the aim to find the origin of traps at this interface. The optimized structure is obtained by structural minimization and is compared with a filtered Transmission Electron Microscopy image from the literature. The good qualitative agreement between the two results validates the atomic model of the InAs/Si interface. Electronic structural calculations are performed on the geometrically optimized InAs/Si slab to identify the interface trap levels. The study reveals that the InAs/Si interface traps originate from unsaturated orbitals present on Arsenic interface atoms. The saturation of the unsaturated As atoms by H or S is able to passivate the interface and to reduce the Dit.

The influence of channel quantization and interface traps on the performance of InAs/Si pTFETs is analyzed, and a device geometry is predicted which is least sensitive to trap-assisted tunneling (TAT). The good agreement between simulated and measured transfer characteristics validates the reliability of the simulation setup. Simulations show that TAT degrades the sub-threshold swing (SS) of the tunnel field effect transistor (TFET) and that channel quantization reduces its ON-current. The same simulation setup is used to find the device geometry which is least susceptible to interface traps. Scaling down the nanowire diameter below 20 nm inhibits TAT at the oxide/InAs interface. Furthermore, aligning the gate edge with the InAs/Si hetero-junction reduces the degradation of the SS caused by TAT at the hetero-interface. In this way, a gate-aligned InAs/Si nanowire TFET with diameter ~20 nm can deliver sub-thermal sub-threshold swing even in the unavoidable presence of oxide- and hetero-interface traps.

Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The ‘trap-tolerant’ device geometry can result in a small sub-threshold swing despite commonly present trap concentrations.

Trap-assisted tunneling is known to detrimentally affect the performance of TFETs. To find the origin of traps at the InAs/Si interface, Density Functional Theory (DFT) based modeling of the interface is performed using the DFT tool CP2K. Geometrically optimized atomic positions at the InAs/Si interface obtained by using structural minimization are in qualitative agreement with TEM images reported in the literature. Electronic structure calculations using the optimized atomic structure reveal highly localized trap states at the InAs/Si interface. The trap states originate from unsaturated atomic orbitals on As atoms and are primarily localized at As atoms.

The effect of traps in the hetero-junction and at the oxide interface on slope and ON-current of vertical and lateral InAs/Si Nanowire (NW) Tunnel FETs (TFETs) is demonstrated through physics-based TCAD analyses in combination with experimental findings. The high density of interface states (D it ) at the highly lattice-mismatched material interface degrades the sub-threshold swing (SS) and makes band-to-band tunneling (BTBT) completely dominated by Shockley-Read-Hall (SRH) generation and trap-assisted tunneling (TAT) up to high gate voltages. When the NW diameter is scaled into the volume-inversion regime, the TFET can even turn into an artificial MOSFET with close-to-60mV/dec slope due to the intrinsic Si channel. The only remedy is then given by a “trap-tolerant” geometry where the gate edge is aligned with the hetero-junction.

Awake fiberoptic intubation seems to continually lose importance in recent years. Alternative options of airway management are coming more and more into the focus of clinical anaesthesia and are moreover advertised specifically for the difficult airway. The concern seems justified that this intubation technique - once the indisputed standard in the management of the anticipated difficult airway - is practised less and less so that especially younger colleagues can hardly gain routine practice. This article aims at counteracting this trend and particularly demonstrates a practical approach. Against this background the equipment is described and tips and tricks are given for execution. The main focus are safety aspects and the success factor of a good topical mucosal anaesthesia, which is of greater importance than a concomitant sedation.

The fabrication technology of extra-functionality CMOS devices involves process steps which lead to high damage in the silicon lattice. Amorphizing implants and simultaneous reduction of thermal budgets to gain better control of the formation of ultra-shallow junctions render the presence of extended defects in active regions unavoidable. In particular, dislocation loops (DLs) have proven to be stable under thermal treatment. To better understand the electrical properties of DLs and their impact on the leakage current we developed an analytical tool to extract defect parameters from measured Deep Level Transient Spectroscopy (DLTS) signals and capacitance transients. Commercial process and device simulators are used to test the plausibility of applied defect models and the basic assumptions about the electrical activity of DLs. Simulation of DLTS peak broadening caused by the broadening of a defect level distribution in the band gap of silicon.

A framework is proposed that allows for a joint description and optimization of both binary polar coding and 2m-ary digital pulse-amplitude modulation (PAM) schemes. For the latter, the multilevel coding (MLC) approach as well as bit-interleaved coded modulation (BICM) are considered. The conceptual equivalence of polar coding and multilevel coding is covered in detail. Based on an alternative characterization of the channel polarization phenomenon, rules for the optimum choice of the labeling in coded modulation schemes employing polar codes are developed. Simulation results regarding the error performance of the proposed schemes on the AWGN channel are included.

Physics-based TCAD simulations of measured vertical and lateral InAs/Si hetero nanowire tunnel FETs are presented to demonstrate the effect of major non-idealities on slope and ON-current. The Dit limit for sub-thermal TFET operation is predicted, and it is shown that a high defect density at the InAs/Si interface can result in a slope close to 60 mV/dec due to thermionic emission in an arising MOSFET with the intrinsic Si region as gated channel.

Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thin-body (DG-UTB), a triple-gate FinFET, and a gate-all-around nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of Lg=15 nm and 10.4 nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for Lg=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50–60%.

Through ab-initio quantum transport simulations the logic performance of single-layer InAs, InN, InP, and InSb III-V compounds is analyzed in this paper for n- and p-type applications. The key findings are that (i) the low electron effective masses of all these materials lead to very similar and attractive ON-currents in n-type transistors, but cause a rapid deterioration of their sub-threshold swing as the gate length shrinks to 10 nm and below, (ii) the p-type devices show much smaller and scattered current values that are too low to eventually challenge Si FinFETs, and (iii) the density-of-states bottleneck effect strongly influences the behavior of the n-type devices.

In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously demonstrated vertical devices, which are now implemented horizontally in-plane on the Si wafer. The InAs/Si TFETs show excellent performance with Ion of about 4μA/μm at Vgs = Vds = −0.5V, combined with average subthreshold swings (SS) of 70–80mV/dec. The SS is limited by trap mechanisms at the heterojunction, which will also be discussed. The InAs/GaSb n-TFETs represent our first devices in this material system, with doping levels and gate stack not yet optimized; the all III-V TFETs show about an order of magnitude greater current levels, but at a worse SS.

With the growing interest in III-V-based nano-scale transistors as potential candidates for next-generation switches there is a need for efficient simulation tools capable to predict the impact of inherent quantum effects. In this paper we show how quantum drift-diffusion (QDD) models can be used to mimic those quantum effects. The models do not only properly account for geometrical confinement in Ino.53Gao.47As FETs with a body thickness below 12 nm, but also for source-to-drain tunneling, the main cause of rising OFF-current at gate lengths shorter than 25 nm. The parameters of the QDD models available in the commercial device simulator S-Device were calibrated with the help of the quantum transport code QT-Solver. Transfer characteristics of double-gate transistors with various gate lengths were computed. Their sub-threshold swings were extracted and used as metric for the comparison. Various QDD models, also in combination with a barrier tunneling model, were tested. The pre-factor of the density-gradient model in S-Device turned out to depend on normal electric field and body thickness. Expressions for both dependencies were implemented in the Physical Model Interface of S-Device. Good agreement for inversion layer density and sub-threshold slope obtained with the QDD models and those computed with QT-Solver was found for low and high source-drain bias.

The paper presents a semi-classical model to take into account the effect of field induced as well as geometric quantization. It uses the transfer matrix method to determine whether the energy of a given tunnel path lies above or below the first sub-band level. The validity of the model is verified by simulating transfer characteristics of a one-dimensional InGaAs/GaAsSb n-channel TFET and comparing the result with those of quantum-mechanical calculations. Furthermore, the good agreement between transfer characteristics of InAs/Si bilayer TFETs obtained by 2D semi-classical simulations with those found by OMEN simulations suggests that the developed model is also useful for 2D devices. It also implies that, replacing a rigid 2D TFET simulation by semi-classical 1D simulations along straight tunnel paths is a viable TCAD approach.

The impact of surface roughness (SR) and phonon scattering on extremely narrow InAs-Si Nanowire TFETs is studied in this paper. The rough surface of the nanowire is generated by randomly distributing the atoms at the InAs-Si/Oxide interface according to an Ando-like exponential auto-correlation function. Phonons are atomistically treated by means of the valence-force-field method. A full-band and atomistic quantum transport simulator based on the sp3d5s* tight-binding model and the non-equilibrium Green's function formalism is used to solve the quantum transport problem where the electron-phonon interactions are tackled within the self-consistent Born approximation. Phonon scattering is found to have no major effect on the device ON-state, while in the OFF-state the current is significantly increased. SR scattering has a detrimental impact on the TFET performance with a ON-current reduction by almost two orders of magnitude, but it induces limited variability. A direct comparison of both scattering mechanisms reveals the dominant behavior of SR over phonon scattering.

In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with I on of a couple of µA/µm (|V GS | = |V DS | = 0.5V) combined with average subthreshold swing, SS, of 70–80mV/dec. The all III–V n-TFETs show about an order of magnitude higher I on , but their SS is limited by the non-optimized gate stack and doping profiles. Thorough simulation studies of our devices show trap-assisted tunneling at the heterojunction to be the main limitation on SS. We will discuss the impact of different trap mechanisms and compare our results with other experimental data.

Good thermoelectric devices with a high value of figure of merit are required to convert back waste heat into useful energy. One way to achieve this goal is to engineer the surface of nanostructures by introducing roughness, thus leading to a significant reduction of their thermal conductivity. We formulate here new theoretical descriptions of phonon interface roughness scattering in Si nanowires with a surface distributed either according to a Gaussian or exponential correlation function. Our calculations of the thermal conductivity of Si nanowires show an excellent agreement with experimental data. It is further demonstrated that the distribution of the nanowire surface (Gaussian or exponential) has almost no influence on the thermal conductivity. We finally predict that the thermal conductivity depends on the nanowire crystal orientation with a lower value along the (100) rather than the (111) direction. The developed scheme can now be used to model the thermal conductivity of other materials as well.

In this talk we will discuss fabrication and device aspects of IBMs work on III–V Tunnel FETs. Since our focus is on the monolithic integration of III–V on Si, we will show our recently developed Template Assisted Selective Epitaxy (TASE) technology and its application to both TFETs as well as other electronic devices. In TASE, III–V materials can be grown within templates, which allows for versatility in materials choice and freedom in growth parameters and is ideally suited for the heterojunction devices required for tunnel FETs. Generally, reducing traps at the heterojunction and at the interface is a great challenge for tunnel FETs, thus we will also discuss the impact of the different trap mechanisms in our devices.

As a potential candidate for solid-state switches in low-power electronic circuits, the Tunnel Field Effect Transistor (TFET) has attracted the attention of device designers in the past few years. Although simulations have shown that ideal hetero TFETs can achieve sub-thermal sub-threshold swing (SS), the fabrication of a TFET with sufficient on-current and sub-thermal SS over a few decades of drain current remains to be done. Non-idealities in a TFET such as interface traps, band tails, or surface roughness exhibit stronger influence on TFET characteristics in the sub-threshold region. In Ref. [1] we observed that among all of these non-idealities the strongest effect is due to interface traps. On the other hand, simulations have shown that channel quantization severely degrades the on-current [2]. In this work, we analyse experimental transfer characteristics of InAs/Si nanowire TFETs (diameter « 100 nm) and find reasons for the degradation of SS and on-current. We give an estimate for the D it that still would allow a sub-thermal SS.

The catalytic conversion of methane and carbon dioxide was studied in a fluidized bed reactor supported by a 13.56 Hz driven coaxial DBD-reactor. Palladium or cupper catalyst which are covered on Al2O3 particles were used. The goal was to test whether biogas can be used for the production of synthesis gas. The influences of discharge power, catalysts and temperature of the catalyst bed on the product yield were studied. The starting material and product stream was analyzed by quadrupole mass spectrometry and infrared spectroscopy. H2/CO ratios can be adjusted in a range between 0.65 (without a catalyst) and 1.75 (using a copper catalyst). The process is highly selective for hydrogen production (up to 83%, using a Palladium catalyst). A copper catalyst increases the H2/CO ratio can from 1.04 to 1.16 and the palladium catalyst from 1.11 to 1.43 by heating the catalyst to a temperature of 250°C.

We report on the fabrication and characterization of silicon nanowire tunnel diodes. The silicon nanowires were grown on p-type Si substrates using Au-catalyzed vapor-liquid-solid growth and in situ n-type doping. Electrical measurements reveal Esaki diode characteristics with peak current densities of 3.6 kA/cm(2), peak-to-valley current ratios of up to 4.3, and reverse current densities of up to 300 kA/cm(2) at 0.5 V reverse bias. Strain-dependent current-voltage (I-V) measurements exhibit a decrease of the peak tunnel current with uniaxial tensile stress and an increase of 48% for 1.3 GPa compressive stress along the111growth direction, revealing the strain dependence of the Si band structure and thus the tunnel barrier. The contributions of phonons to the indirect tunneling process were probed by conductance measurements at 4.2 K. These measurements show phonon peaks at energies corresponding to the transverse acoustical and transverse optical phonons. In addition, the low-temperature conductance measurements were extended to higher biases to identify potential impurity states in the band gap. The results demonstrate that the most likely impurity, namely, Au from the catalyst particle, is not detectable, a finding that is also supported by the excellent device properties of the Esaki diodes reported here.

Over the last years, novel low-complexity approaches to the equalization of MIMO channels have gained much attention. Thereby, methods based on lattice basis reduction are of special interest, as they achieve the optimum diversity order. In this paper, a tutorial overview on LRA equalization optimized according to the MMSE criterion is given. It is proven that applying the zero-forcing BLAST algorithm to a suitably augmented channel matrix – the inverse of the square root of the correlation matrix of the data symbols times the noise variance forms its lower part – results in the optimum solution. This fact is already widely used but lacks a formal proof. It turns out that it is more important to take the correlations of the data correctly into account than what type of lattice reduction actually is used.

Conventional scaling is hampered by the inability to further reduce operating voltages. The main reason for this is the limitation on the subthreshold swing of a MOSFET which determines the abruptness of the on-off transition. This is an inherent limitation of the MOSFET device physics and cannot be remedied by the introduction of novel materials or architectures, but remains an underlying physical limitation. A number of devices have been proposed to overcome this limitation, of those, the most promising in a CMOS setting remains the tunnel FET (TFET). Within the past decade, initial euphoria regarding TFET properties were replaced by more realistic hopes as more thorough simulations brought a deeper understanding of device limitations and opportunities. In this respect it became clear that careful device design and a stringent control of defects is required to realize the promise of TFETs experimentally. Very recently experimental tunnel FETs showing sub-thermionic swing over a significant current range were demonstrated, showing that it is possible to beat CMOS performance. However, technologically heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this talk we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development.

The hybrid plasma-catalytic system was tested for the mixture of methane and CO2 conversion at the pressure of 1.2 bar with the use of a dielectric barrier discharge (DBD) reactor powered at the frequency of 5.7–6 kHz. Three kinds of catalytic packing were examined: alumina ceramic carrier (Al2O3) and two catalysts, i.e. Ag/Al2O3 and Pd/Al2O3. The effects of temperature (120–290 °C), [CO2]:[CH4] molar ratio in the inlet gas mixtures (CH4 + CO2 + Ar), gas flow rate, and specific energy on the conversion were studied. Hydrogen, carbon oxide, hydrocarbons (ethane, ethylene + acetylene fraction, propane, propylene, n-butane, and i-butane), and alcohols (methanol and ethanol) were identified in the outlet gas. Among the organic gaseous products, ethane was dominant over the entire parameter range under examination. Non-volatile products (carbon, macromolecular substances) formed a visible deposit on the quartz dielectric barrier and metal electrode surfaces. With the Pd/Al2O3 catalyst, the overall methane conversion was 30–50% and the methane conversion to C2–C4 hydrocarbons reached 22%.

We present a combined electrical and modeling study to determine the tunneling electron effective mass and electron affinity for HfO 2 . Experimental capacitance–voltage ( C – V ) and current–voltage ( J – V ) characteristics are presented for HfO 2 films deposited on Si(1 0 0) substrates by atomic layer deposition (ALD) and by electron beam evaporation (e-beam), with equivalent oxide thicknesses in the range 10–12.5 A. We extend on previous studies by applying a self-consistent 1D-Schrodinger–Poisson solver to the entire gate stack, including the inter-layer SiO x region – and to the adjacent substrate for non-local barrier tunnelling – self-consistently linked to the quantum-drift-diffusion transport model. Reverse modeling is applied to the correlated gate and drain currents in long-channel MOSFET structures. Values of (0.11 ± 0.03) m 0 and (2.0 ± 0.25) eV are determined for the HfO 2 electron effective mass and the HfO 2 electron affinity, respectively. We apply our extracted electron effective mass and electron affinity to predict leakage current densities in future 32 nm and 22 nm technology node MOSFETs with SiO x thicknesses of 7–8 A and HfO 2 thicknesses of 23–24 A.

The gate leakage currents of single-gate silicon-on- insulator (SOI) n-type MOSFETs are investigated, assuming direct tunneling as the leakage mechanism and using either a 1-D Schrodinger-Poisson-based approach coupled to the conventional drift-diffusion transport model or a full quantum mechanical treatment. The first approach consists of calculating the transmission probability through the dielectric material along straight lines connecting the transistor channel to the gate. The second method is based on a 2-D Schrodinger-Poisson solver, where carriers are injected into the device from the source, drain, and gate contacts. The simulated structures have a physical gate length of 32 nm. The channel is isolated from the gate contact by a dielectric layer with an equivalent oxide thickness of 1.2 nm. This layer is composed of either pure SiO2 or a high-kappa SiO2 - HfO2 stack. Irrespective of the dielectric material, the leakage currents calculated with the 1-D approach are about one order of magnitude smaller at low gate voltages and converge toward the same value as the channel potential barrier decreases. The difference is caused by the diffraction of the electron waves at both edges of the gate contact. This peculiar 2-D behavior of the gate leakage currents, as well as the limit of the 1-D model, is discussed in this paper for various dielectric configurations.

In this paper a method to compute transport parameters in semiconductor devices as a function of the driving forces is presented. The method is based on an exact expansion of the distribution function (solution of the Boltzmann transport equation) in a series in the electric field and the gradient of the quasi-Fermi potential. Eventhough this series probably diverges for high fields, it is still usable for low and moderate field intensities. Results for silicon clearly show that the usual parametrization of the mobility in TCAD models is inaccurate in pn junctions. Furthermore, it gives new insights into the form of the correct parametrization. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

We present semi-classical simulations of Gate-overlapped-Source Tunnel Field Effect Transistors (GoS-TFETs) taking into account the effects of trap-assisted tunneling, channel quantization, surface roughness, and density-of-state tails.

A comprehensive description of band gap and effective masses of III–V semiconductor bulk and ultra-thin body (UTB) structures under realistic biaxial and uniaxial strain is given using numerical simulations from four different electronic structure codes. The consistency between the different tools is discussed in depth. The nearest neighbor sp3d5s* empirical tight-binding model is found to reproduce most trends obtained by ab initio Density Functional Theory calculations at much lower computational cost. This model is then used to investigate the impact of strain on the ON-state performance of realistic In 0.53 Ga 0.47 As UTB MOSFETs coupled with an efficient method based on the well-known top-of-the-barrier model. While the relative variation of effective masses between unstrained and strained cases seems promising at first, the calculations predict no more than 2% performance improvement on drive currents from any of the studied strain configurations.

The extraction of transport parameters as mobilities and diffusivities has been a subject of research for more than 20 years. However, the solutions proposed up to now are not satisfactory particularly when applied to nanoscale devices. In this brief, we review the two most popular methods to extract mobilities and show how they fail in nanoscale devices, where transport is strongly quasi-ballistic. We also show that these methods are not appropriate to extract tensorial transport parameters. As an alternative, we propose to use recently derived general definitions of mobilities and diffusivities that naturally solve these problems and, thus, constitute a universal method to extract transport parameters.

In a previous theoretical work, the concept of mobility has been unequivocally extended to inhomogeneous nonequilibrium systems. This generalization naturally suggests a new one-particle Monte Carlo method to solve the Boltzmann equation, which can self-consistently take into account generation-recombination processes, as well as quantum corrections. This new scheme has been successfully applied to different kinds of MOSFETs. The results of the simulations clearly show that, surprisingly, the mobility in the channel can become negative. In this brief, we present a detailed analysis of this phenomenon and show that negative mobilities are directly related to regions, where quasi-ballistic transport takes place.

The characterisation of a discharge requires the knowledge about few parameters. The most important are the electron density, the debye-length λd and the voltage/current characteristic. Normally the electron density is obtained using a Langmuir Probe. This method delivers reliable results if the influence on the electric field can be neglected. In the analysis of microdischarges, this assumption is not fulfilled. J. Park et al. (J. Appl. Phys.2001, 89, 15), developed a model which allows to calculate the electron density using the plasma current, the area of the discharge and the electric field strength. The debye-length can be estimated using the dimensions of the dark space of the discharge. With this information it is possible to calculate the electron temperature. To measure the dimension of the dark space, it is crucial to take a close look at the discharge. We used an ocular of a microscope (40× magnification) to project an image of one electrode gap onto the sensor of an ICCD-Camera. The electrical parameters were obtained using an ENI V/I-Probe®. The experiments were conducted in helium and argon at atmospheric pressure. In order to cover the whole glow-discharge regime, the applied power was raised in steps of 1 W from the point of ignition to the glow-to-arc transition. Electron densities and temperatures as well as the debye-length could be obtained.

International audience; In this work, the electrical properties of dislocation loops and their role in the generation ofleakage currents in p-n or Schottky junctions wereinvestigated both experimentally and throughsimulations. Deep Level Transient Spectroscopy(DLTS) reveals that the implantation of siliconwith 21015Ge cm2and annealing between 1000C and 1100C introduced two broad elec-tron levels EC0.38 eV and EC0.29 eV in n-type samples and a single broad hole trap EVþ0.25 eV in the p-type samples. These trap levels are related to the extended defects (dislocationloops) formed during annealing. Dislocation loops are responsible for the significant increase ofleakage currents which are attributed to the same energy levels. The comparison between struc-tural defect parameters and electrical defect concentrations indicates that atoms located on theloop perimeter are the likely sources of the measured DLTS signals. The combined use of defectmodels and recently developed DLTS simulation allows reducing the number of assumptions andfitting parameters needed for the simulation of leakage currents, therefore improving their pre-dictability. It is found that simulations based on the coupled-defect-levels model reproduce wellthe measured leakage current values and their field dependence behaviour, indicating that leakagecurrents can be successfully simulated on the exclusive basis of the experimentally observedenergy levels

InAs-Si double-gate TFETs exploiting the two-dimensional (2D) density-of-state (DOS) switch are studied. A full-band and atomistic quantum transport simulator based on the sp3d5s∗ tight-binding model is used to solve the quantum transport problem taking into account both lateral and vertical band-to-band tunneling paths. TFETs with only vertical tunneling components are also investigated. Our findings suggest that InAs-Si 2D-2D TFETs might offer a device solution with both steep sub-thermal sub-threshold swing (SS) and high ON-current. In the best case of an extremely thin InAs-Si 2D-2D TFET the minimal swing reaches SS = 12mV/dec and the ON-current 241 A/m.

We show that the negative differential resistance in the I/sub d/-V/sub ds/ characteristics observed in hydrodynamic transport simulations of partially depleted silicon-on-insulator MOSFETs disappears if the nonlocality of tunneling effects are properly accounted for in the recombination-generation process.

For achieving a physical gate length lower than 50 nm and keeping at the same time good transistor performance, a careful design of drain-extension and channel doping profiles is required. For this we investigate the influence of drain-extension and HALO doping gradients at the drain-extension channel junction (DECJ). It is found that the influence of the drain extension doping gradient on the threshold voltage roll-off behavior is small for steep profiles when keeping saturation current and overlap capacitance constant. On the other hand, the shape of the HALO profile influences the threshold voltage roll-off characteristics and allows to adjust the roll-off behavior without degrading the saturation current dramatically. The effect of process parameters like HALO implantation angle and energy on the transistor performance is studied.

The inclusion of quantization effects on the carrier densities is now the state of the art in modern semiconductor device simulators and yields, for example, quantum-corrected threshold voltages and quantum-mechanical models of the channel mobility. However, the effect of charge quantization on nonradiative thermal generation–recombination has not received much attention. In this article, Shockley–Read–Hall recombination is examined for situations in which electrons and/or holes are confined in semiconductor devices. For the transitions between band states and a single deep level, a previously developed multiphonon description is adopted. It is found that the lifetimes have to be altered due to the same quantized local density of states that also accounts for the carrier distribution. Numerical evaluation of this model for one-dimensional potentials and small phonon energies results in spatially varying lifetime profiles that exhibit two opposite regimes. The additional nonclassical offset of the subband eigenenergies causes an increased lifetime in the limit of strong quantum confinement. For nondegenerate statistics, an analytical high-temperature approximation is presented for this limit, where the activation energy of the lifetime is increased by the lowest-subband offset. In the absence of confinement, however, high electric fields reduce the lifetime due to carrier tunneling into the bandgap.

Double-gate MOSFETs with gate lengths of 50 and 25 nm are theoretically analyzed by drift-diffusion (DD), hydrodynamic (HD) and self-consistent full-band Monte Carlo (MC) simulation. The underestimation of the on-current Ion by DD is found to be stronger than the overestimation by HD. The main differences to the case of bulk MOSFETs are: (i) not only the velocities in the source-side of the channel, but also the sheet densities vary appreciably between the different transport models, (ii) current conservation leads to strong non-equilibrium in the highly doped source region with high velocities and electric fields and (iii) surface roughness appears to become more effective for reduced silicon film thicknesses which might jeopardize the performance enhancement upon further scaling.

Single electron transistors are studied by self-consistent 3D quantum mechanical simulation. Computation of the linear-response conductance requires the calculation of thermal ensemble averages. The evaluation of these quantities can be substantially accelerated by means of Monte-Carlo sampling.