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We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved I ON , +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (L G ) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with As and 5nm fin suppresses off state leakage current under the gate efficiently even in P extension case though P diffusion is faster than As.

In this work, the potential of Si 1−x Ge x Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for Si 1−x Ge x Quantum Well devices, which is attributed to junction induced defects creation at the SiGe/Si buffer layer interface. This highlights the need for a dedicated junction solution in SiGe QW devices. The junction leakages are also investigated, and it is found that Band to Band Tunneling is the dominant mechanism setting the minimum Off-state leakage current. Band to Band Tunneling is increasing when the Ge content is increased, and it may effectively cap the allowed Ge channel content for Low Power Applications. The minimum Off state leakage requirement for DRAM peripheral applications is still obtained for a Ge concentration of 45%.

In this work, the potential of the recently demonstrated D&GR (Diffusion & Gate Replacement, [5]) for thick oxide I/O devices integration is investigated. A D&GR integration flow compliant with EOT requirements for I/O devices is demonstrated, with no penalty with regard to HKMG Non D&GR flow in terms of short channel effects and intrinsic transistor performance. Threshold voltage tuning options from 150 up to 300 mV are demonstrated, and one preferred integration route (keeping the same work function shifters for both thin and thick oxide devices) is highlighted. Finally, it is also shown that HKMG I/O devices (D&GR and non D&GR) do not suffer from reverse narrow gate width effects.

This simulation work studies whether optimal wafer and channel orientations exist that maximize the mobility of 10 nm-node strained-silicon FinFETs. For NFinFETs, strain-relaxed buffers or source/drain stressors yield the highest mobilities on rotated-notch wafers. For PFinFETs, industry-standard directions give the highest mobilities when using Si 1−y C y strain-relaxed buffers as a stress booster. Using {110} substrates leads to strained mobilities that are in between what can be obtained by industry-standard and rotated-notch directions.

Employing a 8 band k.p solver, the self-consistent band structure of the rectangular IIIV nanowires (NW) has been calculated. It is shown that the strong confinement combined with the band nonparabolicity will considerably change the effective masses and the band gap. The mass tensor elements get heavier than the bulk values and improve the density of state (DOS) and centroid capacitance accordingly, while in return the mobility will be degraded. The band widening has also been calculated for different width and height combinations. It is shown that oxide thickness scaling cannot compensate the poor DOS of IIIV, where the silicon device exhibits a continuous performance boost by thinning the oxide layer. Possible improvements of DOS through the width and the mole fraction modulation have been investigated.

In heterojunction Tunneling Field-Effect Transistors (TFET), the effective tunneling bandgap (E g,eff ) has a strong impact on the on-current (I on ) and the subthreshold swing (SS) (figure 1). There is however significant uncertainty on E g,eff for the staggered heterojunction In 0.53 Ga 0.47 As/GaAs 0.50 Sb 0.50 (InGaAs/GaAsSb), with values in literature ranging from 0.5 eV to 0.27 eV [3–6]. An additional problem is that E g,eff is usually measured optically on lowly doped heterojunctions [7–8]. These values may be far off for use in TFETs where there is bandgap narrowing due to heavy doping (doping-BGN) in the source and pocket regions. The impact of doping-BGN on Band-To-Band Tunneling (BTBT) is currently not well understood, contributing to the difficulty in making quantitative hetero-TFET predictions.

A FinFET high-k replacement metal gate stack resistance model is proposed. Introduction of non-negligible contact resistance existing in boundaries between metal layers achieves a good model accuracy which is validated by FEM-based simulation results in 14nm and 10nm technology nodes. Impact of the contact resistance on digital and analog circuit is investigated, resulting in 20% degradation of analog speed by 5 Ω·μm2 contact resistance. The derived gate resistance model is applicable to further downscaled FinFET technology.

A transition from planar to FinFET brings additional variability sources from 3D channel structure. In this study, the impact of fin shape variability on device performance, especially from the view point of short channel effect control, is investigated with using Si-validated TCAD. This reveals that the width, height and taper angle of fin have significant impact on the electrostatics of the device. In addition, through the statistical Monte-Carlo simulations with compact model, the impact of fin shape variability is visualized in comparison with conventional device variability sources, i.e., gate length, work function, and equivalent oxide thickness. As a result, fin width and fin angle are found to be major variability source in addition to gate length. This indicates that the suppression of the process variability in fin width and fin angle is key to control device variability, especially in advanced node.

Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.

A simple analytical model of thin-body In 0.53 Ga 0.47 As-on-InP MOSFET low-field electron mobility suitable for integration in Technology-CAD (TCAD) tools is presented. Phonon, Coulomb and surface roughness scattering are accounted for. In order to characterize the phonon scattering contribution, an expression for the device effective thickness is derived from 1-D Schroedinger-Poisson simulations. The model is validated through comparison with experimental C G -V gs and I d -V gs curves collected on transistors with body thicknesses down to 5 nm.

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. (C) 2015 AIP Publishing LLC.

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G M,SAT,EXT / SS SAT of 250 µS.µm−1 / 130 mV.dec−1 (at the targeted V DS =0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern day’s CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics/design issues as well as in materials/process integration are highlighted.

In this work, we study oxide defects in various III-V/high-k metal-oxide-semiconductor (MOS) stacks. We show that the choice of a given starting measurement voltage with respect to the MOS flat-band voltage affects the observed capacitance-voltage hysteresis. We discuss how this behavior can be used to study the distribution of oxide defect levels. With the help of comprehensive experimental data, we show that Al2O3 and HfO2 have different hysteresis characteristics related to different oxide defect distributions. In case of an Al2O3/HfO2 bilayer stack with Al2O3 on the channel side (interfacial layer, IL), as the IL thickness reduces from 3 nm to 0 nm, the hysteresis behavior switches from the typical Al2O3 behavior to the one corresponding to HfO2. We link the characteristic behavior of two dielectrics to the defect level distributions inside their respective band-gaps through a simple energy-driven charging model. Based on the experimental data and simulation results, we show that Al2O3, despite having...

Embedded SiGe, used to boost pFET performance, is grown by selective epitaxy on silicon. Pattern density effects cause the deposited thickness to be different across different product chips under otherwise identical conditions. Since device control depends critically on thickness, we apply a pattern-density based predictive growth rate, which is used as input for the existing advanced process control method. We demonstrate that the deposited layer thickness is in acceptable range for device performance across a product chip.

Theoretically, confined heterostructure p(-n)-i-n (n(-p)-i-p) TFETs are promising candidates for future low-power applications, with n-TFET outperforming p-TFET. An optimal body thickness of about 10nm is predicted for Ga 0.5 As 0.5 Sb-In 0.53 Ga 0.47 As n-TFET with I 60 =20µA/µm. For p-TFETs, stronger confinement may be required to avoid tunneling to the heavy-hole band. An unexploited domain is the insertion of thin heterostructure slabs offering a locally reduced dielectric constant, enhancing both SS and I on .

Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFET's potential to obtain a sub-60 mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60 mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In0.53Ga0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60 mV/dec SS, with an on-current comparable to the conventional source design. (C) 2014 AIP Publishing LLC.

Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers. The reduced negative bias temperature instability (NBTI) of JL pFETs outperforms the previously reported best NBTI reliability data obtained with Si channel devices and guarantees 10-year lifetime at typical operating voltages and high temperature. This behavior is understood through the reduced oxide electric field and lessened interaction between charge carriers and oxide traps during device operation. These findings encourage the investigation of JL devices with alternative channels as a promising alternative for 7-nm technology nodes meeting reliability targets.

The trap-assisted tunneling (TAT) current in tunnel field-effect transistors (TFETs) is one of the crucial factors degrading the sub-60 mV/dec sub-threshold swing. To correctly predict the TAT currents, an accurate description of the trap is required. Since electric fields in TFETs typically reach beyond 10(6) V/cm, there is a need to quantify the impact of such high field on the traps. We use a quantum mechanical implementation based on the modified transfer matrix method to obtain the trap energy level. We present the qualitative impact of electric field on different trap configurations, locations, and host materials, including both semiconductors and oxides. We determine that there is an electric-field related trap level shift and level broadening. We find that these electric-field induced quantum effects can enhance the trap emission rates. Published by AIP Publishing.

The temperature dependence of ring-oscillator delay of high-kappa /metal-gate (HKMG) and poly-Si/SiON technologies are analyzed. HKMG gate stacks drive significantly stronger threshold temperature dependence over poly-Si/SiON. This effect, together with the reduced mobility temperature sensitivity, result in higher drive current at elevated temperature for HKMG devices. This is in contrast to poly-Si/SiON technology where the low-driven current performance-limiting corner is typically at high temperature.

We report a strong direct correlation (above 0.9) between conventional transistor-level parametrics typically used in the industry to monitor and control intra-die variability (IDV) and a novel, non-contact performance-based metrology (PBM), technology that was integrated into an active die on a 32nm SOI advanced logic product platform. We demonstrate a PBM test structure measurement repeatability of less than 0.4%. In this work, we also demonstrate the compatibility of integrating the PBM technology into an advanced CMOS process flow with no added processing or steps, as well as its footprint scalability. The data suggests that the non-contact PBM technology meets all prerequisites for its deployment as a standard, within-product IDV monitor.

The conduction and valence band offsets between a strained silicon-germanium layer and a silicon-germanium substrate are reported for arbitrary substrate and channel crystal orientations. The offsets are calculated both for the case of biaxial stress, corresponding approximately to the stress state of a thin strained channel in a planar field-effect transistor (FET), and for uniaxial stress, which is the approximate stress state for strained channels in a FinFET configuration. Significant orientation dependence is found for the conduction band offset, overall leading to the strongest electron quantum confinement in biaxial-tensile stressed channels on {100}-oriented substrates, and uniaxial-tensile stressed channels in the ⟨100⟩ and ⟨110⟩ directions. For biaxially stressed layers on {111} substrates, the conduction band offset is significantly smaller than for {100} or {110} directions. For the valence band offset, the dependence on crystal orientation is found to be small.

A systematic method is proposed to address modeling challenges in accurate chip level leakage prediction, namely a precise total leakage width count method, a simple model to quantify leakage uplift caused by systematic across-chip variation, and a consistent model to capture 3-sigma leakage and leakage spread at fixed performance.

We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minimizing systematic ACV. Thermally-driven ACV was identified as a major mechanism in 32nm SOI technology. An optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power-performance trade-off.

Over the past three technology generations we have made systematic observations on device-design strategies leading to optimal circuit-limited yield. These strategies now impose additional considerations that need to be directly coupled into the technology-development paradigm. At the core of the present discussion is the balance between traditional FET (Field Effect Transistor) and small-circuit optimization and the concurrent impact seen at product level. Certain device-design tradeoffs need to be understood in order to maximize performance for a diverse range of products.

A common platform technology at 65 nm is described. The platform consists of a low-power CMOS base technology with a broad menu of optional features including high- performance passive devices, standard cell libraries, SRAM compilers and a process design kit enabling custom design. These elements enable competitive leadership technology for ASICs and Foundry applications, resulting in a highly competitive technology that is an excellent choice when performance and cost must be balanced.

In this work, we discuss how the position of the flat band voltage with respect to the starting voltage of the C-V measurement sweep can influence the estimation of the hysteresis in high-k/InGaAs MOS devices. We show that, with the support of experimental data and conceptual oxide defect band calculations, the interpretation and subsequent parameter extraction from flat-band voltage shifts observed in III-V MOS devices is more complex as compared to Si gate stacks. It is demonstrated that such complication arises due to the wider distribution of defect levels in the dielectric band gap in the case of InGaAs/high-k stack as compared to standard Si/SiO2/HfO2 MOS. In particular, for Al2O3 deposited on InGaAs, two wide, partially overlapping oxide defect bands are identified, centered ∼1.5 eV and ∼0.5 eV above and below the channel conduction band, respectively. Such defect levels are expected to affect the device operation and reliability.

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating effect included) at 200nA/mum off-state current and VDD of 1.0V. PMOS drive current is enhanced by 5% to a value of 575muA/mum (60OmuA/mum if 5% PFET SOI self-heating effect included) which is less than enhancement observed in the NFET due to the differing amount of enhancement of capacitive inversion thickness (TINV) at short channel. With respect to circuit and product performance, this device provides a 5% delay improvement for a product-like ring-oscillator (RO) and results in an improved cross-die statistical distribution of RO delay time. The minimum stable SRAM operating voltage (Vmin) is also significantly improved, indicating that control of the overlap capacitance (Cov) may play a significant role in determining SRAM Vmin. For the first time, we report that the NFET Tinv reduction by LSA is substantially larger at shorter channel lengths which explains the large NFET drive current enhancements obtained by LSA

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.

Strain Engineering has become extremely important in the semiconductor industry as a means of achieving device performance enhancement as device scaling runs out of steam. It is important to detect strain as a function of position in device sized areas in order to assess the viability of different process schemes. In the present work, Moire fringe patterns were used to measure and map the relaxation effects in SiGe and Si/SiGe structures fabricated on SIMOX substrates. Initially, measurements of the strain state using the Moire technique were correlated with those obtained by x-ray diffraction for blanket SiGe on insulator films over the range 0.2–0.8%. Using this correlation as a basis, several interesting relaxation characteristics were found on patterned structures. Evidence of a rhombohedral relaxation was seen for rectangular SiGe mesas fabricated by patterning and then homogenizing SiGe/Si bilayers on SIMOX substrates. The magnitude of the relaxation was found to depend of the size of the structure and the distance to the nearest edge. Elastic relaxation of Si lines was also seen. Lastly, evidence of non uniform relaxation was seen in the SiGe template in wide channel areas of silicide-contacted device structures.

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Integration of strained Si and high-K gate dielectric is demonstrated for the first time. While providing a >1000/spl times/ gate leakage reduction, strained Si NMOSFETs with HfO/sub 2/ gate dielectric exhibit 60% higher mobility than the unstrained Si device with HfO/sub 2/ gate dielectrics, and 30% higher mobility than the conventional Si NMOSFETs with SiO/sub 2/ gate dielectric (universal MOSFET mobility).

We present enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL (middle-of-line) process. For the first time, we systematically designed silicide proximity in SOI and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 /spl mu/A/um and 420 /spl mu/A/um at Ioff = 40 nA/um with Vdd = 1.0 V, for NFET and PFET, respectively), significant reduction in effective gate oxide thickness under gate inversion by /spl sim/1.2 /spl Aring/ and /spl sim/2.1 /spl Aring/, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.

SOI MOSFET devices have proven very robust to plasma process induced gate oxide damage. In this work, we demonstrate that SOI devices with very large antenna ratios may be successfully fabricated without damage, provided that asymmetry of charging is not intentionally introduced, no connection is made to the wafer bulk, and that the integrity of the buried oxide is maintained.

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I/sub off/ levels of 100 nA/um for 1.1 volt operation. The physical gate length (L/sub poly/) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I/sub off/ levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f/sub max/ of 193 GHz has been demonstrated along with an f/sub T/ of 178 GHz.

The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.

This work demonstrates the integration of Al/sub 2/O/sub 3/ gate-dielectrics into a sub 0.1 /spl mu/m n-MOS process using polycrystalline silicon gates, Devices incorporating Al/sub 2/O/sub 3/ films with a dielectric constant /spl epsi/-11 and electrical thickness t/sub qm/

Understanding the reliability implications for silicon-on-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SOI material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SOI CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasma-induced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to burn-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD).

We describe a circuit-based model of charging damage, in which the plasma characteristics are modeled with simple plasma equations, and devices on the wafer are modeled with standard FET compact models. A circuit solver is then used to determine the nodal potentials and currents. We first use this approach for bulk technology and illustrate some aspects of the model, examining oxide thicknesses of 2.3 nm, 3.5 nm, and 6.8 nm. We then apply the model to understand charging in an SOI technology, where the interconnections may be quite complex and all nodes are independent of the wafer substrate. Although SOI circuits are generally immune to charging damage, some bulk-like behavior may be induced by introducing differential electron shading. Results from the model are compared with data, and then the usefulness of the model in analyzing complex circuits is described.

High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance G m, conductance G ds, G m/I d, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., I on–I off, I off–V tsat, DIBL, C jswg) and reliability (HCI) have also shown the comparability of HPA devices over control.

For sub-7nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have impact on the transient performance of an ESD protection diode. vfTLP measurement results and TCAD simulations prove that the performance in bulk GAA NW based diodes is maintained in comparison to bulk FinFET diodes.

We present a systematic study on maximizing polysilicon gate activation for aggressively scaled 0.1 /spl mu/m CMOS technologies. The fundamental limit of gate activation due to poly depletion effect was investigated in terms of gate implant/anneal condition and sequence, poly grain size, dopant penetration and activation. For the first time, we achieved significant improvement in CMOS performance by developing a novel process of "gate postdoping" to decouple implant and anneals for gate, source/drain, and extension. The method successfully reduces the poly depletion effect and thus the equivalent gate oxide thickness in inversion by up to /spl sim/2 /spl Aring/, improving CMOS on-currents by 9/spl sim/33% over a conventional process.

In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit. We propose a mixed-radix encoding system for a multi-device synaptic unit achieving high classification accuracy (94%) including device variability. To our knowledge, this is the first paper to discuss the tradeoff between single and multi-device synaptic weight in terms of design and technology using silicon data. We have demonstrated that high level of variability can be handled by the neuromorphic algorithm. The results presented in the paper has been obtained from 1Mb array.