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We have compared the worst-case of HC degradation between Low Leakage (LL) and High Speed (HS) p-channel MOSFET's which is found under Channel Hot-Hole (CHH) injections as the electron trapping is vanishing with the reduction of the gate-oxide thickness. We focus on the distinction between HH injection and the direct tunneling of holes which is measured even at low voltage in the state-of the art 2.1 nm thick gate-oxide MOSFET's. This latter effect has been included in the Charge-Pumping (CP) analysis showing no strong effect when using appropriate measurement conditions by I/sub CP/-V/sub GL/ (V/sub GH/) curves in contrast to the standard fixed amplitude technique. LL and HS devices have shown distinct behaviors under uniform and localized CHH injections related to the different contributions of the degraded regions. CHH damage shows that for a same interface trap generation LL devices exhibit a stronger effect on the transistor performances due to the defect above the channel while HS devices have a larger degradation in the gate-drain overlap region. This is explained by the location of the peak lateral field and damage extent between both devices.

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO 2 gate-oxide ranging from T ox =3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the T ox thinning and the shrink of the gate-length with L G ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the T ox and L G margin. It is shown that the interface trap generation (Δ N it ) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (Δ L ) with the L G reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.

International audience; Carrier injection mechanisms have been compared in surface p-channel metal–oxide–semiconductor field-effect transistors with a 2.1 nm thick gate-oxide. Currents as a function of voltage, I(V), were correlated with a corrected charge-pumping analysis taking into account the tunneling components. Channel hot-hole injection at the gate and drain voltages, |VGS| >=|VDS|, induces damage even at low stress voltage (

International audience; In this work, we have studied the evolution of the electrical properties of 1.2–2.5 nm-thick SiO2 oxides in N-channel metal–oxide–semiconductor field effect transistors submitted to either uniform electron injections in the direct tunneling regime or localized channel hot carrier injections. The degradation of the oxide is investigated through the classical electrical parameter set of the transistor, the gate leakage current, and charge pumping measurements. Constant current stresses at Jinj = 34 mA/cm2 did not induce any damage. In contrast, constant voltage stresses at VG ¼ 3:5 V led to an increase up to a factor of 10 in the gate current, IG, in the [-0.4,-1 V] range, while small variations of transistor parameters were detected. Hot carrier stresses were performed in 50/1 µm transistors at the condition of maximum of substrate current for drain voltages, VD = 3:5 and 4 V, with or without a substrate bias. We find an increase in the interface state density measured by charge pumping practically independent of the oxide thickness for times >100 s, which is correlated to transconductance and drain current reduction depending on substrate bias. But no correlation is found with the evolution of the gate current, which indicates that the IG increase is not directly linked here to the increase in interface state density revealed by charge pumping. An explanation of this apparent contradiction using the different energy levels and the localization of the defects induced in both cases is proposed.

We have investigated the degradation behavior of single transistors using DC and AC alternating stress conditions as the interface trap generation and the charge trapping/detrapping phenomena become a competitive interaction during AC cycles in 0.25 /spl mu/m CMOS technologies with 5 nm thick gate-oxide. In this way, we determine to what extent the effects and mechanisms are affecting the resultant degradation behavior between N- and P-MOSFETs in order to explain the degradation observed in actual circuits. The effect of temperature is further investigated between -40/spl deg/C and 125/spl deg/C as Negative Bias Temperature Instability (NBTI), thermal emission, field-enhanced charge detrapping may contribute to the transistor degradation and modify the circuit degradation. We verify the usefulness of the experimental procedure and model based on duty cycle calculations for ring oscillators.

The hot-carrier reliability of deep-submicrometer surface-channel pMOSFETs presents more severe limitations than the usual electron-trapping-induced channel shortening. New degradation mechanisms are found during AC pass transistor degradations whereby the electron trapping is quickly suppressed by the subsequent detrapping phases leading to the strong influence of donor-type interface traps which reduce the transistor performances as in the case of n-MOSFETs. This effect becomes more pronounced in thin gate-oxide (7 nm) and shows a large dependence with the propagation delay which is partly due to the lower sensitivity to negative trapped charge in thin oxides and due to the increasing proportion of the detrapped charges and of the generated interface traps.

International audience; We compare in this work the electrical properties of gate leakage currents induced through the thin SiO2 oxide layer of metal-oxide-semiconductor structures by high-energy ion implantation (Boron B2+) and high field electrical stresses where electrons are injected from the gate in the Fowler–Nordheim regime. Even if the high-frequency capacitance–voltage characteristics are very different after both treatments, comparable increases and similar shapes are found at low field in static gate current–voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism.

International audience; In this study, we report on the electrical properties of the stress induced leakage current which appears through a 4.7 nm-thick SiO2 gate oxide of N-channel metal-oxide-semiconductor field effect transistors after localized channel hot carrier injections and Fowler–Nordheim uniform injections. We show that channel hot hole injections are able to induce a stress leakage current leading at longer times to a gate current versus gate voltage similar to the one obtained after uniform injections in the Fowler–Nordheim mode, and well fitted by a Schottky law. However, the kinetics of both degradation modes differ. Other localized hot carrier injection modes (channel hot electron injections) appear to be less efficient in producing stress induced leakage current. Hole injection at the Si/SiO2 interface, present in both channel hole injections and negative gate voltage Fowler–Nordheim stresses via the anode hole injection mechanism, is found to be the key phenomenon leading to stress induced leakage current generation.

International audience; In this study, we have investigated the electrical properties of the failure mode referred as quasi-breakdown or soft-breakdown in MOS capacitors on p-type substrate with an oxide thickness of 4.5 nm. Quasi-breakdown appears during high field stresses as a sudden increase between two and four orders of magnitude in the gate current over the whole gate voltage range, but remains undetected in C(V) characteristics between 20 Hz and 100 kHz. Quasi-breakdown was systematically triggered during negative gate voltage stresses after a threshold between 10 and 15 C/cm2 was reached in the injected charge, this threshold being independent of the stressing oxide field. A very weak temperature dependence and a low frequency noise in the gate current were also observed. The I(V) characteristics are found to follow a first-order exponential law versus the gate voltage, indicative of a direct tunneling process, which could result from a local lowering of the oxide thickness resulting from a sudden metal/isolant transition in a localized region of the oxide near the anode due to oxide defects.

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25‐125 8C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. DiAerent degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what eAectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 8C using inverter and pass transistor operations in a 0.35 mm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation. # 1999 Elsevier Science Ltd. All rights reserved.

International audience; We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (

The hot carrier degradation of large-angle-tilt implanted drain (LATID) and standard LDD N-MOSFETs has been investigated thoroughly using the combination of I-V characterization, charge-pumping and profiling of the damaged region. Although the LATID structure exhibits a good current drivability and net improvement in the hot-carrier immunity, the gate-voltage dependence of the transistor degradation shows significant differences compared to the LDD structure. The distinct time-dependence of the transconductance degradation and the filling of acceptor-like (neutral) oxide traps were emphasized. It is shown that the degradation in LATID is less sensitive to the gate-voltage V g governing hole or electron injection, which leads to a “flat” V g -dependence where holes are less efficient to create acceptor-like oxide traps. The charge-pumping analysis has shown a similar V g -dependence between the interface trap generation and the acceptor-like oxide traps in both structures. Less positive and negative trapped charges are found in LATID than in LDD with a larger difference in the high V g -stress region (where the trapping of negative charge largely dominates the interface trap generation). This was confirmed by profiling measurements which have shown that the density of the negative trapped charges in LATID is one half of that in LDD, but in contrast presents a significant extension from the n -region into the channel. Finally, though the LATID N-MOSFET is one of the best structures able to exceed a DC lifetime of 10 years, lifetime experiments have shown that acceptor-like oxide traps clearly reduce the device lifetime in LATID in the same way as in LDD, which could lead to enhanced hot-carrier degradation in some cases of AC operation for these structures.

International audience; New degradation mechanisms are found during AC pass transistor operation combined with charge-pumping analysis in thin gate-oxide p-MOSFET's. The electron trapping is clearly saturating and in some cases can be completely suppressed by the subsequent detrapping phases leading to the strong influence of donor type interface traps alone, as no positive oxide charge is detected in a moderate field range. These influences reduce the transistor performances as in the case of n-MOSFET's and become more pronounced in 7nm gate-oxide, showing a large dependence with the propagation delay. This is partly due to the low sensitivity to the negative trapped charge with respect to the increasing proportion of the detrapped charge and of generated interface traps in 7nm gate-oxide surface-channel p-MOSFET's.

International audience; Charge trapping and interface trap creation phenomena observed in 8 nm thick thermally grown oxides and oxides nitrided by low pressure ammonia plasma are reported. These phenomena are observed for samples subjected to uniform high-field current injection. It is demonstrated that trap creation is limited to the generation of interface states. No electron trapping and no positive charge generation are observed for injected fluences ranging from 10−6 − 102 C/cm2 at oxide fields in the range 8–11 MV/cm. Quite similar trap creation rates and kinetics are observed in both samples, which demonstrates the good reliability performance of the nitrided oxide. Results are discussed in terms of impact ionization and trap creation by hydrogen-related species models.

International audience; The charging and discharging properties of electron traps created by hot‐carrier injections in the thin gate oxide of n‐channel metal oxide semiconductor transistors are analyzed by means of the effects that charge state transitions induce on the low‐level gate current (lower than 1 pA) of the transistor. This current is measured by a very senstive floating‐gate technique [F.H. Gaensslen and J.M. Aitken, IEEE Electron. Device Lett. EDL‐1, 231 (1980)]. Two traps with electron capture cross sections of the order of 1E-14 and 1E-15 cm2 are analyzed which are linked with optical and field‐dependent measurements of electron emission properties. Thermal and optical ionization energies of these defects are determined at ≊1.7±0.2 and ≊3.0±0.5 eV, respectively. Comparison with theory suggests that Si dangling bonds or oxygen vacancy in the oxide should be the defects created by hot‐carrier injections.

The integration of High-k dielectrics in transistors gate stacks lead to new complex reliability issues. Furthermore new problematics appear with the use of fully depleted silicon on insulator (FDSOI) substrates for future sub-32nm planar technologies. Indeed, the integration of a buried oxide underneath the silicon film changes the electrostatic of the structure and create a new Si/SiO2 interface which may be degraded. This thesis presents different electrical characterization techniques and reliability studies on High- /metal gate FDSOI transistors. First, a complete electrostatic study of FDSOI structures is done allowing a better understanding of the effects of backgate biases. Different techniques to characterize interface traps are then presented and adapted to FDSOI devices, where traps at backgate interface, between the silicon film and the buried oxide, must be considered. Finally, different reliability studies are presented, from NBTI and PBTI issues on long channel devices to smaller dimension devices specific studies such as hot carriers degradation on ultra-thin film FDSOI devices and threshold voltage increase with gate width scaling., L'intégration de diélectriques High- k dans les empilements de grille des transistors a fait naître des problèmes de fiabilité complexes. A cela vient s'ajouter, en vue des technologies sub-32nm planaires, de nouvelles problématiques liées à l'utilisation de substrats silicium sur isolant complètement désertés FDSOI. En effet, l'intégration d'un oxyde enterré sous le film de silicium va modifier électrostatique de la structure et faire apparaître une nouvelle interface Si/SiO2 sujette à d'éventuelles dégradations. Ce manuscrit présente différentes méthodes de caractérisation électrique ainsi que différentes études de fiabilité des dispositifs FDSOI intégrants des empilements High- /grille métallique. Dans un premier temps, une étude complète du couplage électrostatique dans des structures FDSOI est réalisée, permettant de mieux appréhender l'effet d'une tension en face arrière sur les caractéristiques électriques des dispositifs. Différentes méthodes de caractérisation des pièges d'interface sont ensuite présentées et adaptées, lorsque possible, au cas spécifique du FDSOI, où les défauts entre le film de silicium et l'oxyde enterré doivent être pris en compte. Enfin, différentes études de fiabilité sont présentées, des phénomènes de PBTI et de NBTI sur des dispositifs à canaux longs aux phénomènes propres aux dispositifs de petite dimension, tels que l'impact des porteurs chauds dans des structures FDSOI à film ultra fins et les effets d'augmentation de tension de seuil lorsque les largeurs de grille diminuent.

Electrostatic Discharges (ESD) is a major reliability concern for semiconductor companies. To prevent the ICs from failures caused by ESD events, on-chip ESD protections concepts are implemented. With the down-scaling of the CMOS technologies, the boundary conditions defined by application and process is getting extremely challenging for the conception of robust protection elements. In this work the emerging issues of the thin oxide failures due to ESD is addressed. The work contributes also to the understanding of thin oxide dielectrics and device reliability degradation mechanisms under ESD events. A new characterization approach for thin gate oxides under short pulse stresses (down to 20 ns) is introduced; it allows complete modeling of the time-to-breakdown. An universal time-to-fail voltage power law acceleration is reported. This is an extremely important result for the ESD designs with regard to all kinds of ESD stress events. From the modeling package established in this work, a novel ESD development kit is described, aiming to improve the ESD robustness and reliability of products based on advanced sub-micron CMOS technologies.; Les décharges électrostatiques (ESD) constituent un problème majeur de fiabilité pour les entreprises de semi-conducteurs. Pour enrayer les défauts générés par les ESD sur les circuits intégrés (ICs), des éléments de protection sont implantés directement dans les puces. La constante poussée de l'intégration des circuits a pour conséquence la réduction des dimensions des cellules technologiques élémentaires ainsi que l'accroissement du nombre d'applications supportées par les ICs. Les conditions restrictives imposées par les procédés technologiques et par la complexité croissante des systèmes entraînent un défi considérablement accru pour le développement de produits robustes aux ESD. Dans ce travail de recherche, le problème émergeant des défaillances des couches d'oxydes minces d'épaisseur Tox = 8 à 1.1nm sous contraintes ESD est adressé dans les technologies CMOS les plus avancées, par une contribution à la compréhension des mécanismes de dégradation de la fiabilité du diélectrique et des dispositifs sous contraintes ESD. Une nouvelle approche de caractérisation des oxydes minces sous des stress à pulses ultra-courts (20 ns) est décrite jusqu'à la modélisation complète de la dépendance temporelle du claquage du diélectrique. Basé sur un ensemble cohérent de modélisations, une nouvelle méthodologie est proposée pour ajuster la détermination de la fenêtre ESD de façon mieux adaptée aux intervalles de tension et d'épaisseur d'oxyde de grille pour l'ingénierie des concepts de protection. Ceci a permis d'améliorer la prise en compte des problèmes ESD pour une meilleure fiabilité et robustesse des produits conçus en technologies CMOS fortement sub-microniques vis-à-vis des décharges électrostatiques.

Electrostatic Discharges (ESD) is a major reliability concern for semiconductor companies. To prevent the ICs from failures caused by ESD events, on-chip ESD protections concepts are implemented. With the down-scaling of the CMOS technologies, the boundary conditions defined by application and process is getting extremely challenging for the conception of robust protection elements. In this work the emerging issues of the thin oxide failures due to ESD is addressed. The work contributes also to the understanding of thin oxide dielectrics and device reliability degradation mechanisms under ESD events. A new characterization approach for thin gate oxides under short pulse stresses (down to 20 ns) is introduced; it allows complete modeling of the time-to-breakdown. An universal time-to-fail voltage power law acceleration is reported. This is an extremely important result for the ESD designs with regard to all kinds of ESD stress events. From the modeling package established in this work, a novel ESD development kit is described, aiming to improve the ESD robustness and reliability of products based on advanced sub-micron CMOS technologies.; Les décharges électrostatiques (ESD) constituent un problème majeur de fiabilité pour les entreprises de semi-conducteurs. Pour enrayer les défauts générés par les ESD sur les circuits intégrés (ICs), des éléments de protection sont implantés directement dans les puces. La constante poussée de l'intégration des circuits a pour conséquence la réduction des dimensions des cellules technologiques élémentaires ainsi que l'accroissement du nombre d'applications supportées par les ICs. Les conditions restrictives imposées par les procédés technologiques et par la complexité croissante des systèmes entraînent un défi considérablement accru pour le développement de produits robustes aux ESD. Dans ce travail de recherche, le problème émergeant des défaillances des couches d'oxydes minces d'épaisseur Tox = 8 à 1.1nm sous contraintes ESD est adressé dans les technologies CMOS les plus avancées, par une contribution à la compréhension des mécanismes de dégradation de la fiabilité du diélectrique et des dispositifs sous contraintes ESD. Une nouvelle approche de caractérisation des oxydes minces sous des stress à pulses ultra-courts (20 ns) est décrite jusqu'à la modélisation complète de la dépendance temporelle du claquage du diélectrique. Basé sur un ensemble cohérent de modélisations, une nouvelle méthodologie est proposée pour ajuster la détermination de la fenêtre ESD de façon mieux adaptée aux intervalles de tension et d'épaisseur d'oxyde de grille pour l'ingénierie des concepts de protection. Ceci a permis d'améliorer la prise en compte des problèmes ESD pour une meilleure fiabilité et robustesse des produits conçus en technologies CMOS fortement sub-microniques vis-à-vis des décharges électrostatiques.