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Thermal processing steps in the production of packaged integrated circuits can lead to thermomechanical stresses. Additionally, the process of bonding wires to contact pads can lead to strain fields attributable to these. Synchrotron x-ray topography has been applied to packaged EEPROM Si ICs in order to produce maps of the strain fields induced by such processing steps. This technique allows for depth-resolved mapping with resolutions currently in the region of 5–10 μm throughout the entire mapping volume.

The continued decrease in critical dimensions and increasing integration levels in Si CMOS technology is imposing ever tighter constraints on quality control parameters for the IC manufacturing industry. One very important issue is the need to ensure a uniform, high quality Si substrate, i.e. minimise defect/dislocation densities and eliminate strain distributions in the starting wafer material. A comprehensive Synchrotron X-Ray Topography (SXRT) study was applied to commercially supplied 200mm diameter Si wafers. These wafers, which all included a surface Si epilayer growth were supplied from manufacturers from around the globe. The study revealed not only differences in the overall quality of the wafers, but also differences in the quality of the individual Silicon epilayers and substrates. In all wafers the substrate quality varied dramatically with position across the wafer, as measured by the distribution of oxygen precipitates and stacking faults in the wafer. This distribution also varied significantly from manufacturer to manufacturer. The strain fields induced by the growth of lightly doped Si epilayers were also observed to qualitatively vary with location on a wafer, together with (as expected) thickness of the epilayers. The results clearly indicate that optimal quality control for such commercial wafers has not yet been achieved.

Large area transmission and section topographs of semi-insulating gallium arsenide wafers grown by the gradient freeze technique are made with synchrotron radiation at HASYLAB in Hamburg and at ESRF in Grenoble. Several high-resolution images including stereo pairs are obtained on the same film at a time. A typical dislocation line is an arc of a circle which starts from one surface and ends at the same surface. From the disappearance of the dislocation image and using the g · b = 0 criterion it is concluded that the Burgers vector b of the most common dislocations is parallel to 〈110〉. Rather large volumes of the wafer are dislocation-free. Section topographs of epitaxial wafers show defects and strain fields at the interface between an n-type substrate and the epitaxial layers grown by chemical vapor deposition. The results are compared with those obtained from detector performance measurements.

We show that x-ray diffraction imaging (topography) and finite-element modelling can determine accurately the probability of propagation of individual cracks in brittle single crystal materials. The x-ray image of the crack provides a critical parameter for crack propagation which informs a predictive model, enabling us to identify critical defects that lead to catastrophic shattering of silicon wafers during high temperature thermal processing. Wafers fracture on cooling and finite element modelling shows that, during cooling, the tangential stress at the wafer edge is tensile and results in crack propagation. The predicted fracture geometry agrees extremely well with that observed experimentally.

The crystallographic properties of a semiconducting CdTe pixelated sensor were investigated at the ANKA synchrotron facility (KIT, Karlsruhe) by means of back reflection white beam topography and high resolution X-ray diffraction. From the results, several orientation contrast features were identified that could be assigned to small angle grain boundaries of 0.01°. Those structures are disseminated in the whole area of the investigated crystal and form a mosaic structure network of tiled and twisted blocks. The topographic mapping of the sensor was correlated with its X-ray response map. The comparison demonstrates the presence of similar features, proving that the structural quality of the sensor material influences the charge carrier transport and consequently the detector performances.

Macro- and microsegregation of sulphur in InP crystals grown from In solution by the travelling heater method under microgravity and normal gravity are analyzed using spatially resolved photoluminescence. Whereas the macrosegregation in earth- as well as space-grown crystals is explained by conventional steady-state models based on the theory of Burton, Prim and Slichter (BPS), the microsegregation can only be understood in terms of the non-steady-state step exchange model.

Three GaSb single crystals have been successfully grown under microgravity on Spacehab -4 during the STS-77 Space Shuttle flight. Two Te-doped crystals with 16 mm diameter and lengths of 31.5 and 18 mm, respectively, were grown by the floating-zone method. From the transition of striated to striation-free material it was possible to determine the critical Marangoni number for the onset of time-dependent thermocapillary convection for the FZ growth: Ma c2 =375±125. This is in good agreement with 3-D numerical simulations resulting in Ma c2 =355±90. The simulations showed that the 3D flow pattern with an azimuthal instability varies from Si-FZ configurations; the reason is most probably the more barrel-shaped zone caused by the large growth angle of 30.7°. In addition to the FZ crystals, one undoped crystal with 15 mm diameter and 1 mm crystallized length was grown from a free Bi zone, the first time a crystal was grown from a free solution zone in space. On earth, a free Bi solution zone is not only limited to small diameters as in the FZ method, but cannot be used at all due to fluid creep. Under μ g , the Bi zone was stable and the grown crystal is free of cracks.

Synchrotron x-ray topography was used in total reflection topography (TRT) mode to observe strain-induced surface bumps due to the presence of underlying misfit dislocations in strained-layer SiGe on Si epitaxial heterostructures. In these experiments, the x rays approached the sample surfaces at grazing incident angles below the critical angles for total external reflection for a number of reflections, and hence, surface strain features nominally less than a few tens of angstro/ms from the sample surface have been observed. These are similar to the surface bumpiness observed by atomic force microscopy, albeit on a much larger lateral length scale. The fact that TRT mode images were taken was confirmed by the observation of conventional backreflection topographic images of misfit dislocations in all samples when the grazing incidence angle became greater than the critical angle.

Full semiconductor wafer defect/dislocation characterization is difficult to implement manually. We present an analysis of an automated algorithm used to extract Threading Screw Dislocation defect data from Synchrotron White Beam X-Ray Topographical images of SiC wafers. This extraction involves a two-fold process; firstly the algorithm highlights the appropriate defect and secondly updates the counter to provide a final result of defect count. The result of the automated algorithm is compared to hand counts in all cases, thus allowing a critical analysis of the technique. Improvements to this algorithm have been made since last reported by the same authors [1], which are discussed. The analysis herein was also performed on a much larger sample of SiC wafer images than previously used by the same authors [1] allowing a better judgment of performance and critical evaluation. The algorithm is also compared with the original previous algorithm that was used [1]. The success of this methodology paves the way for a complete analysis of whole SiC wafers, which previously was extremely difficult due to image analysis inaccuracy or the bottleneck presented by manual counting.

Solder based flip-chip packaging has prompted interest in many integrated circuit (IC)packaging applications due to its many advantages in terms of cost, package size, electricalperformance, input/output density, etc. The ball grid array (BGA) is one of the most commonflip-chip packaging techniques used for microprocessor applications. However, mechanicalstresses induced by the flip-chip process can impact adversely on the reliability of production.White beam synchrotron x-ray topography (SXRT), a non-destructive technique, has beenemployed to investigate the spatial extent of strain fields imposed on the underlying siliconsubstrate for Intelν®Pentiumν®III microprocessors due to the lead-tin solder bump process for BGApackaging. Large area and section back-reflection SXRT images were taken before and after asimulation of the reflow process at 350°C in atmosphere. The presence of induced strain fields inthe Si substrate due to the overlying bump structures has been observed via the extinction contrasteffect in these x-ray topographs. In addition, orientational contrast effects have also been foundafter the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps.The estimated magnitudes of stress, ∣σ∣, imposed on the underlying silicon were calculated to be100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the leadbumps were removed from the wafer, which confirms that the bumps are indeed a major source ofstrain in the underlying Si. Finite element analysis (FEA) has also been performed in 2-D planestrain mode. The magnitudes and spatial distribution of the stresses after the reflow process are ingood agreement with the SXRT results.

Synchrotron x-ray topographs of GaAs epitaxial lateral overgrowth (ELO) samples are made both in transmission and reflection geometries. The topographs show that the bending of the ELO layers is visible in most geometries. A simulation of the topographic images is implemented taking into account only the orientational contrast. Simulated back reflection section topographs are in good agreement with the experimental ones. The shape of the lattice planes in an ELO layer is calculated using the simulation data and compared to the measured surface profile of the same ELO stripe.

Synchrotron x-ray back reflection section topographs of epitaxial lateral overgrown (ELO) GaAs samples grown on (001) GaAs substrates show images of the GaAs layers bent due to the interaction between the layer and the SiO2 mask. The topographs are simulated under the assumption of orientational contrast. Using the same data the measured x-ray diffraction curve is simulated. The calculations, which are in good agreement with the measurements, are used to gain information on the tilted (001) lattice planes in each ELO layer. We show that the bending of ELO lattice planes reaches a maximum at the center of the ELO stripes, where misorientation is at a minimum, and decreases towards the edges of the stripes, where misorientation reaches a maximum.