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A kind of facilities for wafer fabrication, cluster tools (CTs) need to close down to an idle state from time to time because of periodical maintenance and switches from one type of lots to another, which is called a normal close-down process (NCDP). It is crucial to optimize such a transient process since it tends to occur more and more frequently due to customization. Also, process modules (PMs) in CTs are known to be failure-prone. Once a PM failure occurs, a tool needs to close down to an idle state as well, which is different from NCDP and is called a failure close-down process (FCDP). With wafer residency time constraints (WRTCs) being imposed, close-down process optimization for such a tool is challenging, since one needs to not only finish this process as soon as possible but also meet WRTCs during this transient process. In order to tackle this problem, this article first introduces steady state scheduling problems. Then, with a presented backward robot task sequence, a linear programming model is first proposed to optimize NCDP. To deal with the PM failures, efficient PM failure response policies are formulated for the cases in which a PM fails. Then, four linear programs are proposed to optimize an FCDP. Finally, industrial case studies are given to show the usefulness of the proposed approaches.

Real-time process monitoring is a vital technique to maintain safety and quality in the wafer fabrication processes. Hence, statistical process monitoring methods such as statistical process control chart, principal component analysis have been widely applied in wafer fabrication. However, these methods often suffer from the performance degradation problem caused by run-to-run (R2R) variations such as uneven duration and R2R drifts. In this paper, we propose a real-time monitoring framework for continuous wafer fabrication processes with uneven duration and R2R drifts. In this framework, processes are divided into several phases and further aligned in a real-time manner to solve the uneven duration problem. Then, R2R drifts are compensated by a down-sampling seasonal autoregressive integrated moving average model and a moving window multi-batch forecast strategy. Finally, multiphase multiway principal component analysis models are built on the compensated data to monitoring the processes. The efficiency of this framework is demonstrated by a case study on a plasma etch process. The results indicate that the proposed framework can diminish the influence of R2R variations and improve the monitoring model performance.

Nowadays, wafer fabrication in semiconductor manufacturing is highly dependent on cluster tools. A cluster tool is equipped with several process modules (PMs) and a wafer handling robot. When the tool is operating, generally each PM is processing a wafer, and the robot is responsible for delivering the wafers from one PM to another. Thus, when a wafer is completed in a PM, the robot may be busy for performing other tasks such that it cannot immediately unload the completed wafer in the PM, resulting in that the wafer has to stay there for some extra time. The processing time of a wafer together with its delay time for waiting for the robot’s arrival for unloading is defined as wafer residency time in a PM. However, a long wafer delay time may deteriorate its quality. Therefore, it is highly desired and important to reduce the wafer delay time at each step as much as possible. This work aims to tackle this important issue for single-arm cluster tools (SACTs). Specifically, by using a Petri net model, this work analyzes the steady-state operational behavior of an SACT under the backward and earliest starting strategies. It is found that there must exist wafer delay time at the steps in the upstream of the bottleneck step, and such wafer delay time can be reduced by properly adjusting the robot waiting time. Thus, three algorithms are developed to reduce the wafer delay time at each step as much as possible by properly assigning the robot idle time. Finally, the application of the proposed method is illustrated by using examples. Note to Practitioners —In a modern semiconductor fab, there are hundreds of cluster tools for wafer fabrication. To ensure wafer quality, it is important to reduce the wafer delay time in PMs of cluster tools after a wafer is processed since the high temperature, chemical gas, and particles in the PMs may damage the wafer. To do so, this work proposes three algorithms with polynomial complexity to assign the robot idle time as robot waiting time such that the wafer delay time in PMs can be reduced as much as possible. Furthermore, the obtained schedule by these algorithms is optimal in terms of the cycle time. Besides, the developed algorithms can be easily embedded into the controller of cluster tools by facility engineers. Therefore, this work has a practical value.

Electron beam inspection (EBI) with high resolution is a promising technique to improve the defect inspection on the surface of patterned wafer. However, high resolution usually means long inspection time, which results in the low throughput and limitation of EBI applied in practice. This study aims to optimize the inspection time of EBI by reducing the total number of inspection regions without loss of the accuracy. We first refine this defect inspection optimization problem as a partial congruent square cover problem. Then, we propose two novel mixed-integer linear programming models for this problem. To deal with the large-scale problems, an approximation algorithm is developed to obtain the high-quality solutions. This approximation algorithm efficiently utilizes the linear programming (LP) rounding technique and greedy strategy based on the proposed model. Compared with the existing algorithms in the literature, numerical results show the superiority of the proposed model and algorithm. Note to Practitioners —Defect inspection is a key process in wafer fabrication for identifying and inspecting the patterning defects generated during the complicated fabrication processes. Electron beam inspection (EBI) takes place of optical inspection gradually as the design rules keep shrinking and the circuits are more susceptible to nanoscale killer defects. Low throughput is the main drawback of EBI and the improvements on throughput have far-reaching significance on the high volume manufacturing of semiconductor products. This study aims to reduce the number of inspection regions to improve the total inspection time in the EBI process. Considering that the inspection time for each inspection region is constant, less inspection regions means less total inspection time. However, the positions of inspection regions are arbitrary across the continuous planar space, putting pressure on modeling and solving the problem. A preprocessing algorithm is designed to discover a limited number of candidate positions of inspection regions without loss of optimality, which greatly simplifies the problem. For dealing with large-scale instances, an approximation algorithm combining linear programming (LP)-rounding technique and greedy strategy is designed to get near optimal solutions. Since the number of inspection regions is one key factor determining the total inspection time, the proposed optimization methods have a potential to be applicable to enhance the efficiency of advanced EBI platforms, such as ASML HMI eP series.

The properties of a learning-based system are particularly relevant to the process study of the unknown behavior of a system or environment. In the semiconductor industry, there is regularly a partially observable system in which the entire state of the process is not directly or fully visible due to uncertainties or disturbances. The model for studying such a system that permits uncertainties regarding the stochastic (Markov) process for state information acquisition is called a partially observable Markov decision process (POMDP). This study aims to deal with the optimization issue of compensation control bias of a dynamic multilayer lithography process in wafer fabrication with prior information, the existence of high-dimensionality, and unmeasurable uncertainties. We show how the POMDP on a linear state-space model with uncertainties can encode the information from past runs and layers, and deal with accumulated overlay error at the current run and layer. The Gibbs sampling is applied to optimize the belief function of POMDP optimization approach. Note to Practitioners —The multilayer overlay error of the photolithography process is one of the remarkable and challenging issues in wafer fabrication. In a multilevel manufacturing process, errors occur at each level, which would be accumulated in the upstream operations. The optimization objective will be even more critical in a high-mixed fabrication process. In this study, the learning-based control system emerged with the state-space model compensates the multilayer overlay error. The Gibbs sampling as a Bayesian approach as a core structure of optimization algorithm is utilized, which can be updated with information from engineering’s domain knowledge or estimated information about previous runs. The robustness of the proposed optimization algorithm is shown by comparing the distribution of overlay error with conventional methods and with a fast convergence rate of the learning algorithm.

This paper introduces a new approach to design and model shop floor control techniques for wafer fabs in the very large-scale integrated circuit manufacturing industry. The new model suggests the s...

We examine a scheduling problem for a dual-armed cluster tool that processes multiple similar wafer types concurrently. It has been recently proved that the well-known swap sequence, which is widely used for single wafer type processing, also minimizes the cycle time for concurrent processing. In this article, we wish to minimize wafer delays in a process chamber, which are critical to wafer quality degradation, while maintaining the minimum cycle time. In particular, we show that concurrent processing of wafers with different processing times complicates the analysis of wafer delays significantly, and the wafer delays can be remarkably reduced by finding a proper cycle plan which is the release sequence of different wafer types. We first characterize wafer delays for a given cycle plan by analyzing the circuits of the timed event graph (TEG) model. From this, we prove that concurrent processing of wafers may cause a significant workload imbalance between parallel chambers of a process step, and hence the wafer delays increase substantially. We present that the wafer delays are minimized by a cycle plan that evenly balances workloads between parallel chambers. We also propose how wafer loading task at each process step has to be postponed to meet wafer delay constraints while maintaining the minimum cycle time. Note to Practitioners —Wafer quality control has become an essential fab operational problem in semiconductor manufacturing industry. In cluster tools, which are dominantly being used for diverse wafer fabrication stages, it has been proven that the wafer delays within process chambers have a crucial impact on the wafer quality. Accordingly, modern fabs have introduced stringent quality control to regulate wafer delays in cluster tools. In this research, we propose a scheduling strategy to minimize the wafer delays when a cluster tool concurrently processes multiple wafer types. We first show that the release sequence of different wafer types significantly impacts the wafer delays under concurrent processing, and we then propose how these wafer delays can be minimized by finding the optimal wafer release sequence.

In semiconductor manufacturing, an extremely stringent quality control is enforced for wafer fabrication processes. Consequently, cleaning operations that clear residual chemical gases and heat in ...

Automated stocker system is widely used in semiconductor and liquid crystal display (LCD) industries for handling and storage of valuable wafers or glass panels. Massive front opening unified pods (foups) containing wafers, or cassettes storing glass panels, are placed in shelf stockers during manufacturing. Although several preventative measures have been taken, during the past earthquakes, substantial financial loss from the industries were reported, and one of the main causes was attributed to collision of the foups or cassettes and shake off from the shelfs. This paper proposes a methodology of incorporating viscous fluid dampers into the stokers to mitigate their seismic response. Unlike conventionally been done in buildings where dampers are placed between adjacent stories, it is proposed to install dampers in between the ceiling and top of the stocker. Such configuration utilizes the large velocity at the stocker top under vibration, resulting in smaller damper size, and enables a leverage mechanism that requires smaller damper force to resist the stocker’s vibration. Both shake table tests and simulation of a full-scale stocker under realistic earthquakes have been conducted. Results indicate that both displacement and acceleration responses of the stocker can be significantly reduced, and dynamic response of the stocker under seismic excitations can be well predicted.