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Deep convolutional neural networks (DCNNs) have been proposed as enhanced developments of neural networks (NNs) in the field of artificial intelligence (AI) and successfully applied in deep learning (DL) scenarios. With the advancement of technology, the number of network layers has continuously increased, resulting in a huge number of calculations and memory accesses required in the training and inference process of DCNNs and thereby hindering their further deployment and application. Using a specific dataflow formed by reusable DCNN data in the network-on-chip (NoC), reducing the memory access pressure and improving DCNN processing efficiency has become a promising acceleration scheme for the current DCNN. In this article, a novel convolution layer (CONV) acceleration strategy based on logical PE set segmentation for row stationary (RS) dataflow is proposed to solve the problems of low flexibility and inefficient processing array utilization faced by the conventional folding mapping strategy. The simulation results show that the new mapping strategy based on PE set segmentation can achieve better processing element utilization and CONV acceleration improvement at the expense of little increase in the data movement energy consumption compared with the conventional strategy. [ABSTRACT FROM AUTHOR]

Summary: The dataflow model is gradually becoming the de facto standard for big data applications. While many popular frameworks are built around this model, very little research has been done on understanding its inner workings, which in turn has led to inefficiencies in existing frameworks. It is important to note that understanding the relationship between dataflow and high performance computing (HPC) building blocks allows us to address and alleviate many of these fundamental inefficiencies by learning from the extensive research literature in the HPC community. In this article, we present TSets, the dataflow abstraction of Twister2, which is a big data framework designed for high‐performance dataflow and iterative computations. We discuss the dataflow model adopted by TSets and the rationale behind implementing iteration handling at the worker level. Finally, we evaluate TSets to show the performance of the framework and the importance of the worker level iteration model. [ABSTRACT FROM AUTHOR]

We describe the design and implementation of an autonomous prototype vehicle which finds an empty parking slot in a parking area, and parks itself in the empty parking slot, using neural networks based on deep reinforcement learning (RL). To perform an autonomous parking procedure for our prototype vehicle, two different artificial neural networks (ANNs) are trained using a deep RL Algorithm in a simulation environment and embedded into the computing platform of the prototype car. One of the ANNs enables the vehicle to drive autonomously in the parking environment. At the same time, an image processing algorithm is used to determine whether a parking slot is empty. When the image processing algorithm finds a suitable parking slot, a different ANN is activated and performs a safe parking procedure. However, ANN‐based machine learning techniques require high processing power and impose a high computational burden on embedded CPU and GPU platforms. To alleviate the computational burden, one can achieve higher performance and less power consumption using an application‐specific hardware design, where logic resources are fully exploited according to the algorithm of interest, in an energy‐efficient manner. In this article, hardware accelerators for our ANN models are designed and generated via the Vivado high‐level synthesis (HLS) tool, targeting an ARM based programmable SoC platform, ZedBoard. Our ANN accelerators have achieved a speedup of 17x as compared to an ARM software implementation. For deeper fully‐connected layers used in deep RL‐based solutions, function‐level parallelism (Vivado's dataflow) is employed to improve the computational efficiency. Our proposed stage‐level description for fully connected layers outperforms recent studies in terms of computation time. [ABSTRACT FROM AUTHOR]

Summary: Support vector machines (SVM) is a widely used machine learning algorithm. With the increasing amount of research data nowadays, understanding how to do efficient training is more important than ever. This article discusses the performance optimizations and benchmarks related to providing high‐performance support for SVM training. In this research, we have focused on a highly scalable gradient descent‐based approach to implementing the core SVM algorithm. In providing a scalable solution, we have designed optimized high‐performance computing and dataflow‐oriented SVM implementations. A high‐performance computing approach means the algorithm is implemented with the bulk synchronous parallel (BSP) model. In addition, we analyzed the language level optimizations and math kernel optimizations on a prominent HPC modeling programming language (C++) and dataflow modeling programming language (Java). In the experiments, we compared the performance of classic HPC models, classic dataflow models, and hybrid models designed on classic HPC and dataflow programming models. Our research illustrates a scientific approach in designing the SVM algorithm at scale in classic HPC, dataflow, and hybrid systems. [ABSTRACT FROM AUTHOR]

There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements (PEs) interacting via custom buffer hierarchies and networks-on-chip. The efficiency of these accelerators comes from employing optimized dataflow (i.e., spatial/temporal partitioning of data across the PEs and fine-grained scheduling) strategies to optimize data reuse. The focus of this work is to evaluate these accelerator architectures using a tiled general matrix-matrix multiplication (GEMM) kernel. To do so, we develop a framework that finds optimized mappings (dataflow and tile sizes) for a tiled GEMM for a given spatial accelerator and workload combination, leveraging an analytical cost model for runtime and energy. Our evaluations over five spatial accelerators demonstrate that the tiled GEMM mappings systematically generated by our framework achieve high performance on various GEMM workloads and accelerators. [ABSTRACT FROM AUTHOR]

Convolutional neural network (CNN) have been widely used in speech recognition, object detection and image recognition. In the process of inference, data access operations consume more energy than calculations. Therefore, optimizing the dataflow from external storage to the on-chip processing unit is an effective method to reduce the power consumption. The state-of-the-art row stationary dataflow maximizes the data reusing to reduce the number of data movement and thus reducing the power consumption of the system. However, it has the problems of low processing unit utilization and poor scalability. In this letter, we propose an enhance row stationary (ERS) dataflow. ERS dataflow maps the data of each channel of the three-dimensional filter and input feature map (ifmap) into a column of processing units by changing the mapping of data. The processing array operates multiple filters in parallel, which effectively improves the utilization of computing resources. Within each processing unit, one row of filter data and one row of ifmap data are processed at a time, and the filter row data and ifmap row data are reused in multiple convolution operations. In addition, a configurable sliding window model is proposed to solve the problem that the existing dataflow cannot handle the calculation array width smaller than the filter width. Simulation results show that for AlexNet and VGG16, the execution speed of ERS dataflow is improved by about 60% compared with row stationary dataflow, and the hardware resource utilization is improved by about 30%. For the MobileNet V1, the execution speed of ERS dataflow is improved by about 4% compared with the row stationary dataflow. [ABSTRACT FROM AUTHOR]

In recent years many frameworks have appeared, which enable users to easily build, visualize and execute deep learning networks on graphical interfaces. However, they do not always provide enough opporunities to automate this process. Generally, data processing programs can be organized into dataflow graphs that define the operations to be performed sequentially on the data. The operation of deep learning neural networks can also be interpreted in a similar way, in which the input data to be processed is a specific data set and the operations to be performed on the data are the layers of the net. Due to architectural reasons, the entire deep learning neural network graph must be built before actual running, thus it is necessary to change topological execution of dataflows to evaluation preceding graph building since knowing the layers separately is not enough to operate the nets. As a solution for displaying editable program graphs, we created a framework in which data processing related to Python packages can be described and the programs built from them can be visualized and executed (mostly) automatically

Model-driven methodology has been widely adopted in embedded software design, and Dataflow is a widely used computation model, with strong modeling and simulation ability supported in tools such as Ptolemy. However, its code synthesis support is quite limited, which restricts its applications in real industrial practice. In this article, we focus on the automatic code synthesis of Dataflow, and implement DFSynth, a code generator that could support most of the widely used modeling features, such as the expression type and Boolean switch, more efficiently. First, we disassemble the Dataflow model into actors embedded in if-else or switch-case statements based on the schedule analysis, which bridges the semantic gap between the code and the original Dataflow model. Then, we design well-designed templates for each actor, and synthesize well-structured executable C and Java codes with sequential code assembly. Compared to the existing C and Java code generators of Dataflow model in Ptolemy-II, and the C code generator in Simulink, the lines of code synthesized by DFSynth are decreased by an average of 99.7%, 81.4%, and 61.9%, and the execution time of the synthesized code by DFSynth is also decreased by an average of 76.2%, 56.8%, and 22.7%, respectively. [ABSTRACT FROM AUTHOR]

Digital twin (DT) technology has been entrusted with the tasks of modeling and monitoring of the product, process, and production system. Moreover, the development of semantic modeling and digital perception provides the feasibility for the application of DT in the manufacturing industry. However, the application of DT technology in assembly workshop modeling and management is immature for the discreteness of assembly process, diversity of assembly resource, and complexity of dataflow in the assembly task execution. A method of ontology-based modeling and evolution of DT for the assembly workshop is proposed to deal with this situation. Firstly, the ontology-based modeling method is given for the assembly resource and process. By instantiating in the ontology, resources and processes can be involved in the modeling and evolution of the DT workshop. Secondly, the DT assembly workshop framework is introduced with the detailed discussions of dataflow mapping, DT evolution, storage, and tracing of historical data generated during the operation of the workshop. In addition, a case study is illustrated to show the entire process of construction and evolution of the DT modeled on an experimental field, indicating the feasibility and validity of the method proposed. [ABSTRACT FROM AUTHOR]

Tasks and business entities are the major constituents of business processes but they are not always considered equally important. The activity-centric approach and the artifact-oriented one have radically different visions. The former focuses on the control flow, i.e., on the representation of the precedence constraints between tasks, and considers the dataflow an add-on. The latter emphasizes the states of the business entities and defines the transitions between states in a declarative way that makes it difficult to figure out what the control flow is. This paper presents the ELBA notation whose purpose is to integrate those different visions by leveraging the dataflow. The dataflow defines the input and output entities of the tasks in process models. Entities flowing through tasks change their states and then a process model results from the combination of the life cycles of the entities managed by the process. Process models are complemented by information models that show the attributes and relationships of the entity types handled by the processes. Life cycles are intertwined in process models but they can be separated by means of an extraction technique that is illustrated in this paper with the help of two examples.

Over the last decade, Convolutional Neural Networks (CNNs) have become the go to technique to perform tasks in deep learning applications such as computer vision, speech recognition, etc. LeCun et al (Nature 521(7553), 436–44) 2015. Even though CNNs are very efficient at these tasks they are not suitable for embedded applications due to the limited power budget. In this work we present an improved architecture to process the convolution layers in a CNN. This work is based on our earlier architecture which uses FIFO (First In First Out memory)s to accelerate CNNs. Panchbhaiyye and Ogunfunmi 2020. The architecture presented takes advantage of sparsity in CNN layer's inputs and outputs to achieve performance improvement. We evaluate the proposed improvement on 16 bit floating point and 8 bit integer data types and find that this leads to more than 13% improvement in the processing time of convolution layers for VGG16 with float16 data type. Also, we show how this architecture can be used to compute fully connected layers. Overall we are able to exceed the performance of state-of-the-art architectures by more than 1.65x using an inexpensive Pynq Z1 board running at 100Mhz. [ABSTRACT FROM AUTHOR]

Streaming processing is an important and growing class of applications for analyzing continuous streams in real time. In such applications, sliding-window aggregation (SWAG) is a widely used approach, and generalpurpose processors cannot efficiently handle SWAG because of the specific computation patterns. This article proposes an efficient dataflow accelerator architecture for ubiquitous SWAGs, called ShuntFlowPlus. Shunt- FlowPlus supports two main categories of SWAGs that are widely used in streaming processing. Meanwhile, we propose a shunt rule to enable ShuntFlowPlus to efficiently handle SWAGs with arbitrary parameters. Furthermore, we propose a novel realization scheme of SWAG kernels based on buffer sharing to maximize buffer utilization. As a case study, we implemented ShuntFlowPlus on an Altera Arria 10 AX115N FPGA board at 150 MHz and compared it to previous approaches. The experimental results show that ShuntFlowPlus provides a tremendous throughput and latency advantage over CPU and GPU implementations on both reducelike and index-like SWAGs. Compare to ShuntFlow, 41% of buffer resources are saved. [ABSTRACT FROM AUTHOR]

Machine learning (ML) models are widely used in many important domains. For efficiently processing these computational- and memory-intensive applications, tensors of these overparameterized models are compressed by leveraging sparsity, size reduction, and quantization of tensors. Unstructured sparsity and tensors with varying dimensions yield irregular computation, communication, and memory access patterns; processing them on hardware accelerators in a conventional manner does not inherently leverage acceleration opportunities. This article provides a comprehensive survey on the efficient execution of sparse and irregular tensor computations of ML models on hardware accelerators. In particular, it discusses enhancement modules in the architecture design and the software support, categorizes different hardware designs and acceleration techniques, analyzes them in terms of hardware and execution costs, analyzes achievable accelerations for recent DNNs, and highlights further opportunities in terms of hardware/software/model codesign optimizations (inter/intramodule). The takeaways from this article include the following: understanding the key challenges in accelerating sparse, irregular shaped, and quantized tensors; understanding enhancements in accelerator systems for supporting their efficient computations; analyzing tradeoffs in opting for a specific design choice for encoding, storing, extracting, communicating, computing, and load-balancing the nonzeros; understanding how structured sparsity can improve storage efficiency and balance computations; understanding how to compile and map models with sparse tensors on the accelerators; and understanding recent design trends for efficient accelerations and further opportunities. [ABSTRACT FROM AUTHOR]

Equipping mobile platforms with deep learning applications is very valuable. Providing healthcare services in remote areas, improving privacy, and lowering needed communication bandwidth are the advantages of such platforms. Designing an efficient computation engine enhances the performance of these platforms while running deep neural networks (DNNs). Energy-efficient DNN accelerators use skipping sparsity and early negative output feature detection to prune the computations. Spatial DNN accelerators in principle can support computation-pruning techniques compared to other common architectures, such as systolic arrays. These accelerators need a separate data distribution fabric like buses or trees with support for high bandwidth to run the mentioned techniques efficiently and avoid network on chip (NoC)-based stalls. Spatial designs suffer from divergence and unequal work distribution. Therefore, applying computation-pruning techniques into a spatial design, which is even equipped with an NoC that supports high bandwidth for the processing elements (PEs), still causes stalls inside the computation engine. In a spatial architecture, the PEs that perform their tasks earlier have a slack time compared to others. In this article, we propose an architecture with a negligible area overhead based on sharing the scratchpads in a novel way between the PEs to use the available slack time caused by applying computation-pruning techniques or the used NoC format. With the use of our dataflow, a spatial engine can benefit from computation-pruning and data reuse techniques more efficiently. When compared to the reference design, our proposed method achieves a speedup of $\times 1.24$ and an energy efficiency of $\times 1.18$ per inference. [ABSTRACT FROM AUTHOR]

Building efficient embedded deep learning systems requires a tight co-design between DNN algorithms, hardware, and algorithm-to-hardware mapping, a.k.a. dataflow. However, owing to the large joint design space, finding an optimal solution through physical implementation becomes infeasible. To tackle this problem, several design space exploration (DSE) frameworks have emerged recently, yet they either suffer from long runtimes or a limited exploration space. This article introduces ZigZag, a rapid DSE framework for DNN accelerator architecture and mapping. ZigZag extends the common DSE with uneven mapping opportunities and smart mapping search strategies. Uneven mapping decouples operands (W/I/O), memory hierarchy, and mappings (temporal/spatial), opening up a whole new space for DSE, and thus better design points are found by ZigZag compared to other SotAs. For this, ZigZag uses an enhanced nested-for-loop format as a uniform representation to integrate algorithm, accelerator, and algorithm-to-accelerator mapping. ZigZag consists of three key components: 1) an analytical energy-performance-area Hardware Cost Estimator, 2) two Mapping Search Engines that support spatial and temporal even/uneven mapping search, and 3) an Architecture Generator that auto-explores the wide memory hierarchy design space. Benchmarking experiments against published works, in-house accelerator, and existing DSE frameworks, together with three case studies, show the reliability and capability of ZigZag. Up to 64 percent more energy-efficient solutions are found compared to other SotAs, due to ZigZag's uneven mapping capabilities. [ABSTRACT FROM AUTHOR]

The convolutional neural network (CNN)-based super-resolution (SR) has shown outstanding performance in the field of computer vision. The implementation of inference hardware for CNN-based SR has suffered from the intensive computation with severely unbalanced computation load among layers. Various light-weighted SR networks have been researched with little performance degradation. However, the hardware-efficient dataflow is also required to efficiently accelerate inference hardware within limited resources. In this article, we propose the hardware-efficient dataflow of CNN-based SR that reduces computation load by increasing data reuse and increases process element (PE) utilization by balancing the computation load among layers for high throughput. In the proposed dataflow, row-wise pixels in the receptive field are computed by circularly shifting memory addresses to maximize data reuse. The partial convolution is exploited in a layer-based pipeline architecture to relieve intensive computation in a single pipeline stage. The delay-balancing with adjusting parallelism is employed for balancing computations precisely in the overall layers. Furthermore, the inference hardware of CNN-based SR is implemented for 4K ultrahigh definition at 60 fps on a field-programmable gate array (FPGA). For hardware-friendly computation, the quantization of activation and weight is adopted. The proposed hardware shows an average peak signal-to-noise ratio of 36.42 dB in the Set-5 dataset with a memory usage of 53 KB and an average PE utilization of 76.7% in the overall layers. Thus, it achieves the lowest memory usage and highest PE utilization compared with other inference hardware for CNN-based SR.

Abstract This paper presents novel models and design optimization methods for gapless deep waveform applications, where continuous streams of data must be processed reliably without dropping any samples. The approaches developed in this paper involve unified dataflow-based modeling of the interfaces and signal processing functionality of gapless deep waveform analysis. Bottleneck actors (computational modules) in the resulting dataflow model are then identified and tackled with approximate computing techniques. These techniques are developed and configured carefully so that large performance gains are achieved while keeping reductions in signal processing accuracy to a manageable level. Efficient actor- and graph-level code optimization techniques are also applied to further improve real-time performance. In addition to providing accurate, real-time processing on the experimental platform used in our experiments, the algorithm- and model-based formulation of the contributions in this part promotes their general utility in deep waveform analysis and their retargetability to other platforms.

With the increase of the search for computational models where the expression of parallelism occurs naturally, some paradigms arise as options for the current generation of computers. In this context, dynamic dataflow and Gamma—General Abstract Model for Multiset mAnipulation—emerge as interesting computational model choices. In dynamic dataflow model, operations are performed as soon as their associated operands are available, without rely on a Program Counter to dictate the execution order of instructions. The Gamma paradigm is based on a parallel multiset rewriting scheme. It provides a nondeterministic execution model inspired by an abstract chemical machinemetaphor, where operations are formulated as reactions that occur freely among matching elements belonging to the multiset. In this work, equivalence relations between the dynamic dataflow and Gamma paradigms are exposed and explored, while methods to convert from dataflow to Gamma paradigm and vice versa are provided. It is shown that vertices and edges of a dynamic dataflow graph can correspond, respectively, to reactions and multiset elements in the Gamma paradigm. This work provides the scientific community with the possibility of taking profit of both parallel programming models, contributing with a versatility component to researchers and developers. [ABSTRACT FROM AUTHOR]

Data flow formalisms are commonly used to model systems in order to solve problems of buffer sizing and task scheduling. A prerequisite for static analysis of a modeled system is the existence of a periodic schedule in which the sizes of communication channels can be bounded for an unbounded execution (consistency), and that communication dependencies do not introduce a deadlock in such an execution (liveness). In the context of Cyber-Physical Systems, components are often interfaced with the physical world and have frequency constraints. The existing data flow formalisms lack expressiveness to fully cover the expected behavior of these components. We propose an extension to static data flow paradigms, called PolyGraph, that includes frequency constraints and adjustable communication rates. We show that with these extensions, the conditions for a model to be consistent and live are no longer sufficient, and we extend the corresponding theorems with necessary and sufficient conditions to preserve these properties. We illustrate how PolyGraph can be used in practice on a realistic Advanced Driver Assistance System, and present a framework to check PolyGraph properties in the tool DIVERSITY, along with experiments on realistic and random models. [ABSTRACT FROM AUTHOR]

This brief presents a memory-efficient CNN accelerator design for resource-constrained devices in Internet of Things (IoT) and autonomous systems. A segmented logarithmic (SegLog) quantization method is exploited to mitigate the on-chip memory and bandwidth requirements, thus accommodating more processing elements (PEs) in a given chip area to organize a reconfigurable multi-cluster architecture. The evaluation results show that SegLog quantization can achieve 6.4 × model compression with less than 2.5% accuracy loss on various CNNs. An ASIC implementation with 168 PEs configuration is validated in a 40-nm CMOS process, with 2.54 TOPs/W energy efficiency and 0.8 mm2 chip area reported. The accelerator has also been implemented on FPGA with 1512 PEs configured and 468 kB on-chip memory, achieving a 1.29 GOPs/kB memory efficiency. Compared with the state-of-the-art accelerators, our ASIC implementation enhances area efficiency and arithmetic intensity by 1.94 × and 5.62 ×, while the FPGA implementation achieves the memory efficiency improvement by a factor of 2.34 ×. [ABSTRACT FROM AUTHOR]

We present a novel neural decoding system for calcium imaging data. Miniature calcium imaging is of great utility for examining population neural activity of animals. Our neural decoding system is developed using a carefully designed support vector machine subsystem together with dataflow-based techniques for system design, which capture the high-level structure of the application and enable powerful system-level analysis and optimization. Also, we introduce a framework for handling imbalanced data. This addresses a problem of imbalanced datasets, which arises commonly in neural decoding applications, as well as in a wide variety of other applications in biomedical engineering and advanced robotics. We developed an ensemble learning-based method to tackle this problem. The proposed framework systemically incorporates two heterogeneous model characteristics into a combined model. Through extensive experiments, we evaluate the proposed system using calcium imaging datasets in which neural activities of D1 medium spiny neurons in the dorsal striatum were recorded. The results show that the F 1 score of the proposed system is significantly better than those of previously developed neural decoding systems for calcium imaging. [ABSTRACT FROM AUTHOR]

This paper presents a notation to model business processes in the context of B2B (Business to Business) systems. Data-awareness is a key asset of the notation: data is placed at the forefront of process representations and task execution is data-driven instead of control-driven. In addition to process models, the notation (B2BPN) includes three other types of models, i.e. the architectural model, the collaboration models and the information model of the process. Data can transit between B2B processes through the interactions defined in the collaboration models and such models represent the relationships between the companies taking part in B2B systems. The notation is illustrated with an example concerning the order management of a distributor. [ABSTRACT FROM AUTHOR]

DfAnalyzer is a tool for monitoring, debugging, and analyzing dataflows generated by Computational Science and Engineering (CSE) applications. It collects strategic raw data, registering provenance data, and enabling query processing, all asynchronously and at runtime. DfAnalyzer provides lightweight dataflow components to be invoked by CSE applications using High-Performance Computing (HPC), in the same way computational scientists plug HPC (e.g., PETSc) and visualization (e.g., ParaView) libraries. We show DfAnalyzer’s main functionalities and how to analyze dataflows in CSE applications at runtime. The performance evaluation of CSE executions for a complex multiphysics application shows that DfAnalyzer has negligible time overhead on the total elapsed time.

Real-time neuron detection and neural activity extraction are critical components of real-time neural decoding. In this paper, we propose a novel real-time neuron detection and activity extraction system using a dataflow framework to provide real-time performance and adaptability to new algorithms and hardware platforms. The proposed system was evaluated on simulated calcium imaging data, calcium imaging data with manual annotation, and calcium imaging data of the anterior lateral motor cortex. We found that the proposed system accurately detected neurons and extracted neural activities in real time without any requirement for expensive, cumbersome, or special-purpose computing hardware. We expect that the system will enable cost-effective, real-time calcium imaging-based neural decoding, leading to precise neuromodulation.

Recently, an increasing number of cyber-attacks in the medical field has resulted in great losses in the health care industry, since medical information plays an essential role in human health. To introduce a comprehensive survey about possible cyber-attacks and solutions for these attacks, our paper first presents a brief overview of the necessary background of the dataflow in the medical domain and then identifies the vulnerabilities in each stage of the dataflow. Then, according to the weaknesses identified in the medical system, a classification of cyber-attacks is presented. Additionally, the paper presents research on previous work that focuses on solving these cyber-attacks and identifies the strengths and limitations of the solutions for each attack. More importantly, for data storage assurance, our paper discusses several cybersecurity architectures for the medical domain from the existing literature. The countermeasures from previous papers and architectures that are still weak in terms of resource depletion, attack reduction, applicability, etc. are addressed. Finally, the paper discusses and recommends solutions for future work to decrease cyber-attacks in the medical field so that human health can be guaranteed.

The widening of the complexity-productivity gap in application development witnessed in the last years is becoming an important issue for the developers. New design methods try to automate most designers tasks to bridge this gap. In addition, new Model of Computations (MoCs), as those dataflow-based, ease the expression of parallelism within applications, leading to higher designer productivity. Rapid prototyping design tools offer fast estimations of the soundness of design choices. A key step when prototyping an application is to have representative performance indicators to estimate the validity of those design choices. Such indicators can be obtained using hardware information, while new libraries, e.g.,Performance Application Programming Interface (PAPI), ease the access to such hardware information. In this work, PAPIFY toolbox is presented as a tool to perform automatic PAPI-based instrumentation of dynamic dataflow applications. It combines PAPIFY with a dataflow Y-chart based design framework, which is called PREESM, and its companion run-time reconfiguration manager, which is called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPiDER). PAPIFY toolbox accounts for an automatic code generator for static and dynamic applications, a dedicated library to manage the monitoring at run-time and two User Interfaces (UIs) to ease both the configuration and the analysis of the captured run-time information. Additionally, its main advantages are 1) its capability of adapting the monitoring according to the system status and 2) adaptation of the monitoring accordingly to application workload redistribution in run-time. A thorough overhead characterization using Sobel-morpho and Stereo-matching dataflow applications shows that PAPIFY run-time monitoring overhead is up to 10%.

Tasks and business entities are the major constituents of business processes but they are not always considered equally important. The activity-centric approach and the artifact-oriented one have radically different visions. The former focuses on the control flow, i.e., on the representation of the precedence constraints between tasks, and considers the dataflow an add-on. The latter emphasizes the states of the business entities and defines the transitions between states in a declarative way that makes it difficult to figure out what the control flow is. This paper presents the ELBA notation whose purpose is to integrate those different visions by leveraging the dataflow. The dataflow defines the input and output entities of the tasks in process models. Entities flowing through tasks change their states and then a process model results from the combination of the life cycles of the entities managed by the process. Process models are complemented by information models that show the attributes and relationships of the entity types handled by the processes. Life cycles are intertwined in process models but they can be separated by means of an extraction technique that is illustrated in this paper with the help of two examples.

The DataFlow paradigm has been existing for a long time, but good enough enabling technologies have been made available only very recently. The teaching of a different from the mainstream paradigm, such as the DataFlow paradigm, encounters a few problems. If a new paradigm is presented among experienced professionals, the presentation is often received with resistance. If a new paradigm is presented before students, the presentation is always received with enthusiasm, especially if tools and libraries that support the paradigm do exist. In order to overcome the problem with introducing the new paradigm, a series of courses was organized for Universities in the USA and Europe, to teach the DataFlow paradigm, using the Maxeler approach as the baseline for practical work. The course is organized in three different levels: (A) full-hour presentation that includes introducing the programming model with hands-on examples, which is most appropriate for research groups at Universities (B) a certified full-day short-course that students could use as an extension to diploma, (C) full-semester course for credits that is part of graduation requirement. This paper discusses different methods and their results, which could be used in order to efficiently introduce any different from the mainstream paradigm. The results presented in this paper are for 10 universities in the group A, 10 in the group B, and 10 in the group C. Where appropriate, the findings are backed with statistics data.

In this paper we draw our attention to several algorithms for the dataflow computer paradigm, where the dataflow computation is used to augment the classical control-flow computation and, hence, strives to obtain an accelerated algorithm. Our main goal is to experimentally explore various dataflow techniques and features, which enable such an acceleration. Our focus is to resolve one of the most important challenges when designing a dataflow algorithm, which is to determine the best possible data choreography in the given context. In order to mitigate this challenge, we systematically enumerate and present possible techniques of various data choreographies. In particular, we focus our interest on the algorithms that use matrices and vectors as the underlaying data structure. We begin with simple algorithms such as matrix and vector multiplication, evaluation of polynomials as well as more advanced ones such as the simplex algorithm for solving linear programs. To evaluate the algorithms we compare their running-times as well as the dataflow resource consumption.

Deep Neural Networks (DNNs) perform billions of computations in applications such as image classification, object detection, and image segmentation. In most well-known DNNs, an activation function follows a convolutional or a fully connected layer. Several popular activation functions involve setting all negative inputs to zero. In this brief, we propose a novel architecture in which the activation function is merged with the prior computational layer. Our proposed dataflow can reduce the computations needed to generate a specific output feature in convolutional and fully connected layers by reordering the computation to achieve early detection of the sign of the output feature. In addition, our computation engine supports zero computation skipping, which further accelerates the layer computation. In this brief, we build on a state-of-the-art DNN accelerator and modify it to perform early detection of negative output features. When compared to the original design, our method achieves a speedup of $\times 2.19$ and reduces energy consumption by $\times 1.94$. The average reduction in the number of multiply-accumulate (MAC) operations is 10.64% and the average reduction in the number of the load operations is 3.86%. These improvements are achieved while maintaining classification accuracy in two popular benchmark networks. [ABSTRACT FROM AUTHOR]

As general-purpose processors have hit the power wall and chip fabrication cost escalates alarmingly, coarsegrained reconfigurable architectures (CGRAs) are attracting increasing interest from both academia and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software. However, CGRAs are not yet mature in terms of programmability, productivity, and adaptability. This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed. Second, major challenges and the corresponding state-of-the-art techniques are surveyed and analyzed. Finally, the future development is discussed. [ABSTRACT FROM AUTHOR]

In this article, we introduce an automatic stream computing reoptimization flow from ASICs to field-programmable gate arrays (FPGAs). Complex VLSI designs need to be prototyped and/or emulated on FPGAs. The main problem that we address in this article is that configurations optimized when targeting ASICs are often, as we will show in this article, highly un-optimal when remapped onto an FPGA. Thus, this article proposes a method to first generate a variety of dataflow configurations targeting an ASIC given multiple behavioral descriptions for high-level synthesis (HLS) and then, based on a compositional predictive model, automatically reoptimize the dataflow when mapped onto an FPGA. The experimental results show that our proposed method works well and that it is very fast. [ABSTRACT FROM AUTHOR]

In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes among computations. The edges in the dataflow graph are single-input, single-output components that manage data transmission in a first-in, first-out (FIFO) fashion. In this paper, we formulate the vertices and edges into concepts called "active blocks" and "passive blocks", respectively in the graph representation. Computation in the dataflow graph is represented as "active blocks", while the concept of dataflow buffers is represented as "passive blocks". Like dataflow edges, passive blocks are used to store data during the intervals between its production and consumption by actors. However, passive blocks can have multiple inputs and multiple outputs, and can incorporate operations on and rearrangements of the stored data subject to certain constraints. We define a form of flowgraph representation that is based on replacing dataflow edges with the proposed concept of passive blocks. We present a structured design methodology for utilizing this new form of signal processing flowgraph, and demonstrate its application to improving memory management efficiency, and execution time performance. [ABSTRACT FROM AUTHOR]

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resources, pipelining optimization without (or with minimal) resource sharing can give significant advantages in performance. High-level synthesis of CAL-programs is particularly popular in computation intensive applications (e.g., image and video processing, cryptography, wireless communication, etc.) where feedback actors with data flows at input and output ports represent loop-like behavior. In this work, we propose techniques for transforming, analysis, speculatively pipelining and optimizing large branched feedback dataflow programs. We develop an accurate algorithm and introduce fast dynamic and mixed static / dynamic heuristics that firstly minimize the number of pipeline stages for a given pipeline-stage time-period, and secondly minimize the overall pipeline registers size by means of appropriate assignment of feedbacks and instructions to pipeline stages. We also propose a genetic algorithm for tuning the heuristics for a particular design. The experimental results show the algorithms we propose give quickly solutions that are very close to accurate solutions and overcomes the earlier developed algorithms regarding computing time and pipeline parameters. [ABSTRACT FROM AUTHOR]