Search

This paper presents a detailed investigation into the effect of pressure, temperature and particle size distribution (PSD) on the minimum fluidization velocity (Umf). A series of measurement of Umf were carried out under the pressure from 0.1 MPa to 0.5 MPa and the temperature from 300 °C to 850 °C on a lab-scale pressurized fluidized bed reactor for three narrow PSD and three wide PSD (binary, uniform, and Gaussian-type) silica sand particles. The results showed that the Umf for narrow and wide PSDs both decreased with increasing temperature and decreased slightly with rising pressure. Besides, the Gaussian-type mixtures had almost the same Umf as the reference narrow PSD particle, while the Umf of binary and uniform PSD mixtures was larger than these two. Based on the experimental data, a new simple relationship for predicting Umf of the different PSD particles at elevated pressures and temperatures was developed.

Breast cancer has been reported as one of the most frequently diagnosed malignant diseases and the leading cause of cancer death in women all around the world. Furthermore, this complicated cancer is divided into multiple subtypes which present different clinical symptoms and need correspondingly directed therapy. We took BECN1, a core gene in autophagy performing a tumor inhibitory effect, as a starting point. The study in this paper aims to identify genes related to breast cancer and its multiple subtypes by integrating multiple omics data using the least absolute shrinkage and selection operator (LASSO), which is a statistical method that can integrate more than two types of omics data. All the data is obtained from The Cancer Genome Atlas (TCGA) platform which stores clinical and molecular tumor data. The model constructed is based on three kinds of data including mRNA-gene expression with a dependent variable level, DNA methylation and copy number alterations as independent variables. Finally, we propose four subnets of four subtypes of breast cancer, and consider as a result of microarray analysis that AFF3 is associated with BECN1 in breast cancer, and may be a potential therapeutic target. This finding may provide some potential targeted therapeutics for the four different subtypes of breast cancer at the genetic level. In conclusion, finding out the major role Beclin-1 plays in breast cancer subtypes is of great value. The results obtained are instructive for further research and may provide excellent results in clinical applications, as well as testing in animal experiments, and may also indicate a new method to perform bioinformatics analysis.

To remove chlorine from chlorinated wastes efficiently, the hydrothermal treatment (HT) of PVC was investigated with a lower alkaline dosage in this work. Some typical operating conditions were investigated to find out the most important factor affecting the dechlorination efficiency (DE). The FTIR technique was employed to detect the functional groups in PVC and hydrochars generated to reveal the possible pathways for chlorine removal. The results show that the HT temperature was a key parameter to control the dechlorination reaction rate. At a HT temperature of 240 °C, about 94.3% of chlorine could be removed from the PVC with 1% NaOH. The usage of NaOH was helpful for chlorine removal, while a higher dosage might also hinder this process because of the surface poisoning and coverage of free sites. To some extent, the DE was increased with the residence time. At a residence time of 30 min, the DE reached a maximum of 76.74%. A longer residence time could promote the generation of pores in hydrochar which is responsible for the reduction in DE because of the re-absorption of water-soluble chlorine. According to the FTIR results, the peak intensities of both C=CH and C=C stretching vibrations in hydrochar were increased, while the peak at around 3300 cm−1 representing the –OH group was not obvious, indicating that the dehydrochlorination (elimination reaction) was a main route for chlorine removal under these conditions studied in this work.

This paper explores the lead-free (Pb-free) solder reflow process to achieve high assembly yield and solder joint quality for a 3-D silicon-on-silicon flip chip package. Three parameters, which included soak time, peak temperature, and time above liquidus (TAL), were investigated using statistical analysis to identify the nonlinear effect (quadratic effect) of each factor as well as the interactions among the factors. Different reflow ambient gases such as air and nitrogen were investigated to understand the sensitivity of the yield under ambient gases. This paper also revealed that 100% assembly yield can be achieved with a wide process window on the structured silicon-on-silicon flip chip package under nitrogen reflow environment, by investigating 15 reflow profiles designed following the response surface methodology. Within the reflow process window, the solder joint intermetallic compound (IMC) thickness was measured by calculating the average IMC thickness using a mathematical integration method. It was concluded that an increase in TAL results in an increase of IMC thickness.

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

An ultra-broad working temperature dielectric material, Bi4Ti[Formula: see text]O[Formula: see text]([Formula: see text] = 2.96, 2.98, 3.0, 3.02 and 3.04), prepared by a conventional mixed oxide route was investigated which is supposed to replace lead-containing ceramics for its outstanding dielectric properties. Microstructure and dielectric properties of well-sintered samples (at 1040[Formula: see text]C, 1060[Formula: see text]C, 1080[Formula: see text]C, 1100[Formula: see text]C and 1120[Formula: see text]C) were studied. X-ray diffraction analysis indicated that the new material was in a single Bi-layered perovskite phase. The dielectric constant and dielectric loss at different frequencies (10, 100 and 1000 kHz) were measured at 1100[Formula: see text]C. With the increasing frequency, the dielectric constant decreased and the dielectric loss was almost unchanged. While at 100 kHz, there is the highest relative permittivity ([Formula: see text]) of 2822.8 and the lowest dielectric loss of 0.0040 ([Formula: see text] = 2.98), the Curie temperature ([Formula: see text]) is 668.9[Formula: see text]C. At the frequency of 1 MHz, the highest relative permittivity ([Formula: see text]) is 1115.8 when Ti content is 3.02, and the Curie temperature is 672.2[Formula: see text]C. SEM can explain the results of the dielectric spectrum at different Ti content and sintering temperatures. [Formula: see text] plots show that Bi4Ti3O[Formula: see text] ceramics are a kind of dielectrics. Since it possesses large dielectric constant, low dielectric loss and stable temperature character, this material shows promising applications for the ultra-broad temperature range components, such as high-temperature multilayer ceramic capacitors and microwave ceramics.

A kind of lead-free dielectric materials, such as the bismuth layered perovskite-type structure of Bi[Formula: see text]Ti3O[Formula: see text], was prepared by the conventional solid-state method at 800[Formula: see text]C and sintered at 1100[Formula: see text]C. The variation of structure and electrical properties with different Bi concentration was studied. All the Bi[Formula: see text]Ti3O[Formula: see text] samples exhibited a single structured phase. SEM could be a better approach to present the microstructure of Bi[Formula: see text]Ti3O[Formula: see text] ceramics. It could be found that the grain size of Bi[Formula: see text]Ti3O[Formula: see text] sintered at 1100[Formula: see text]C was smaller than that of others among the five samples through grain size mechanics. Through impedance spectra analysis, we knew, when the Bi content was fixed, that the dielectric constant and the loss values increased with the decrease of frequency. The Curie temperature of the five samples was about 670[Formula: see text]C. In particular, while at the frequency of 100[Formula: see text]kHz, the lowest loss was 0.001 when Bi content was 3.98. The Bi[Formula: see text]Ti3O[Formula: see text] ceramics with the minimum grain size had highest dielectric constant and the relatively low loss. Due to its high Curie temperature, high permittivity and low loss, the Bi4Ti3O[Formula: see text] (BIT) ceramics have a broad application prospect in high density memory, generator, sensor, ferroelectric tunnel junctions and so on.

The hydrothermal treatment (HT) is an effective method to remove chlorine from chlorinated wastes under mild conditions. However, the alkali was required to improve the dechlorination efficiency. Meanwhile, the alkalis contents removed was necessary to realize the clean and highly efficient utilization of coal. This work was trying to investigate the feasibility of simultaneously removal alkalis and chlorine by co-hydrothermal treatment of PVC and high-alkali coal. The effect of operating conditions including the HT temperature, the holding time and particle sizes of coal on the dechlorination efficiency (DE) of PVC during the HT process was experimentally studied in this work. The results show that the DE increased with the rise of: 1) particle sizes (0.054~0.22mm), 2) holding time (30~90 min) and 3) temperature (240~300 °C). In detail, under 300 °C and 60min of holding time, the 85.18% of DE with first PS was lower than the 93.93% of DE with second PS and 100% of DE with third PS. The organic chlorine mainly transferred into chloridion in aqueous solution in HT process. All the results indicate that it is a prospective way to simultaneously removal alkalis and chlorine by co-hydrothermal treatment of chlorinated wastes and high-alkali coal.

Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.

Market demand is increasing for even higher packaging densities, smaller size, lower cost, and more heterogeneous functionality. As a result, three dimensional (3D) packaging has emerged as a leading packaging solution. This paper introduces a 3D Wafer Level CSP packaging architecture that provides a cost effective, rapid time to market alternative to emerging 3D die to wafer integration technologies.

A new low cost 3 dimensional wafer level chip scale package (3D-WLCSP) technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly is presented. This paper provides an overview of the new 3D-WLCSP technology including flip chip on wafer bonding assembly technologies required to produce the 3D face to face flip chip on wafer package. Development efforts are focused on high density flip chip placement forming the 3D-WLCSP and the associated innovations that this type of packaging and assembly includes. In this work, the flip chip pitch and bump size is varied as well as key assembly materials (including fluxes and underfills) used to attach the flip chip to the WLCSP. Processing innovations developed include flip chip fluxing methods for very fine pitch and small bump sizes, vision recognition of the chip and substrate during assembly, reflowing of the flip chips on a wafer, and underfilling a solder balled WLCSP wafer with chip components in close proximity. Initial reliability results are presented which highlight that even though the flip chip is mounted silicon to silicon, the pitch and bump size make it so that the underfill selection has a large impact on the reliability of the assembly. Various aspects of the die to wafer assembly process are explored including scaling issues with high volume assembly, utilization of low cost underfill approaches such as no flow underfills and wafer applied underfills, and underfill encroachment on the WLCSP balls. Flux and underfill material combinations are identified that enable high assembly yields and provide reliable 3D-WLCSP assemblies with respect to liquid to liquid thermal shock testing and unbiased autoclave aging.