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In this article, a nonlinear capacitance model for a large-signal compact model of partially depleted (PD) silicon-on-insulator (SOI) transistors is proposed. When the transistors are operated in the saturation and triode region, the gate–source capacitance ( $C_{\mathrm {gs}}$ ) and the gate–drain capacitance ( $C_{\mathrm {gd}}$ ) change with the gate–source voltage ( $V_{\mathrm {GS}}$ ) nonlinearly. $C_{\mathrm {gs}}$ will emerge a significant compression phenomenon in the triode region. This capacitance model adds a hyperbolic tangent function to the conventional model’s function to characterize this phenomenon. Besides, the nonlinear drain current model is obtained on the basis of a unified empirical model. To validate this improved large-signal equivalent circuit model, two different transistors are manufactured in a commercial 180-nm body-contact (BC) PD-SOI process. On-wafer measurement is implemented to obtain the experimental data. Then the calculated results of the model are compared with the measurement data. The relative root-mean-square-error (RRMSE) is less than 6.59% for output power, 9.03% for power-added efficiency (PAE), and 2.72% for the gain respectively.

A broadband SiGe power amplifier (PA) with double gain peaks for 5G applications is presented. The differential structure is widely adopted in millimeter-wave circuit design to decrease the impact of the source parasitic inductance that is induced by the bonding wires. Since differential PA results in a higher impedance transformation ratio of the matching network, differential PAs generally have narrower bandwidth than single-ended PAs. Through the bandwidth analysis of the matching network, the transformer used for interstage matching is elaborately designed to ease gain fluctuations. By controlling the stationary points of impedance transformation, the maximum available gain characteristic of a transistor, which decreases with increasing frequency, can be compensated. The gain curve of PA, thus, has double gain peaks within operational frequencies to make its frequency responses as flat as possible. The proposed PA for the frequency band from 27 to 37 GHz is fabricated in a standard 130-nm SiGe BiCMOS process, which occupies 0.36 mm2. Under the 2.5-V voltage supply, the SiGe PA exhibited a power gain of 33.5 dB and output power of 21.3 dBm with 24% power-added efficiency at 31 GHz. It achieves a 34% 3-dB small-signal $S_{21}$ bandwidth from 27.3 to 38.5 GHz.

This article presents a 60-GHz variable gain phase shifter (VGPS) with orthogonal phase and gain control technique and linear phase control technique in 65-nm CMOS. Using the orthogonal phase and gain control technique, the proposed VGPS has the ability of gain tuning without extra variable gain block, significantly reducing the size of conventional phased arrays. The linear phase control technique is proposed to greatly improve the accuracy and robustness of phase control against temperature variation. As results, the VGPS achieves 6-bit phase resolution across −25 °C to 110 °C and continuous gain tuning range of 14.8 dB. The measured 3-dB bandwidth is 52–64 GHz. As the gain of VGPS is −22.4 to –dB, the measured root-mean-square (rms) phase errors are 1.3°–3.3°, while the measured rms gain errors are 0.2–0.5 dB in 3-dB bandwidth. Across −25 °C to 110 °C, the variations of rms phase and gain errors are below 1.2° and 0.1 dB, respectively. With supply voltage varying from 1.0 to 1.2 V, the variations of rms phase and gain errors are below 1.1° and 0.2 dB, respectively. During the measurement with different combinations of temperature and supply voltage, no gain and phase calibrations are conducted. The measured input-referred $P_{\mathrm {1\,dB}}$ at the maximum gain state (−7.6 dB) is about −3.8 dBm. The chip consumes 16.4 mA from a 1.1-V voltage supply and the core area of the VGPS is $720\,\,\mu \text {m} \times 560 \,\,\mu \text{m}$ .

In this brief, a millimeter-wave (mm-Wave) wideband frequency quadrupler is demonstrated in a 55-nm CMOS technology. It cascades two injection-locked frequency doublers (ILFD). Each of them consists of an oscillator gain stage realized by an injection-locked oscillator (ILO) and a frequency doubler implemented by a push-push pair. A tail feedback loop is proposed and applied in the second ILFD. It effectively boosts the injection current for the second ILFD. Therefore, both the operating bandwidth and output power (Pout) of the circuit are prominently improved. In addition, transformer-based high-order resonators are used to reduce the phase variation of their impedance around 0° and hence extend the locking range of ILOs. According to the measurement results, a frequency range of 30.8 ~ 40 GHz is achieved. The maximum Pout is up to -7.1 dBm without additional buffers. The circuit also attains a wide 3-dB frequency bandwidth of Pout, which is from 32 to 38.4 GHz. The harmonic rejection ratios of the frequency quadrupler are 16.5 ~ 25.9 dBc at the second-order harmonic and 31 ~ 45 dBc at the fundamental and third-order harmonics over the entire operating bandwidth. The core area occupies only 0.24 mm2.

A 5-bit active digital step attenuator (DSA), which simultaneously achieves low amplitude and phase variations, is proposed for wideband phased-array applications. The input and output impedances for each attenuation unit under the reference state and the attenuation state can remain basically the same. Therefore, the amplitude and phase errors caused by a load impedance mismatch between each unit can be alleviated. Implemented in 130-nm silicon–germanium (SiGe) BiCMOS technology platform, the proposed DSA provides a maximum attenuation range of 15.5 dB with 0.5-dB steps. It exhibits an insertion loss (IL) less than 13 dB and input/output return losses less than −10 dB from 31 to 41 GHz. In addition, with the help of minimized amplitude and phase variations, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.2 dB and an rms phase error less than 2.5° at 33–41 GHz, which are the lowest such errors ever reported. The chip core area of the DSA is 0.22 mm2 (0.5 mm $\times0.44$ mm). It shows a suitable performance for 5G applications.

In this article, an improved surface-potential-based current model for MOSFETs is proposed to characterize the Gaussian distribution phenomenon of carrier concentration. First, the lumped parameter equivalent circuit model is established. Then, in order to improve the current model accuracy for the large width–length ratio (WLR) transistors, the channel carrier distribution is studied. Based on this, the conventional drain–source current model is modified. Besides, the parameters related to the carrier distribution along the channel are extracted. In order to validate the improved model, different WLR transistors were fabricated and measured. Furthermore, the model calculation results are compared with the measurement data. The root-mean-square error (RMSE) of drain–source current is reduced from 3.537 to $0.354~\mu \text{A}$ in the subthreshold region and decreased by 76% in the linear region. As a result, the proposed model is reliable and predictable, which is helpful for the RF circuits design.

A harmonic-tuned (HT) voltage-controlled oscillator in a 65-nm CMOS process is demonstrated in this letter. The oscillation frequency and harmonics are tuned independently by two separated high- $Q$ resonators. A novel F23 inductor–capacitor resonator resonating at the second and third harmonics simultaneously is introduced. The proposed F23 inductor has a high-quality factor of 15 and 24 in common-mode (CM) and differential-mode (DM), respectively. The simulation results show that a 4.3-dB phase noise (PN) improvement is achieved in the thermal noise region due to the high- $Q$ HT method. Meanwhile, less harmonic currents are injected into the fundamental resonator due to the source-degeneration principle, hence decreasing the Groszkowski effect and suppressing the flicker noise. The measured PN is −117.5 dBc/Hz at the 1-MHz offset, and the tuning range is 12% from 6.80 to 7.66 GHz. The flicker noise corner is around 220 kHz and the figure-of-merit is 187.2 dBc/Hz. The power consumption is 5 mW under a 0.55-V supply.

This article presents a $K$ -band frequency tripler with bandwidth enhancement techniques. A transformer-based self-mixing topology with peaking inductor (TSM-PI) is introduced to settle the drawbacks in DC distortion, bandwidth, and output voltage of the conventional self-mixing structure. Theoretical analyses compared with the conventional one are proposed, which shows the TSM-PI structure improves performances significantly. With these techniques, a $K$ -band ultrawideband frequency tripler is designed and implemented in a 0.11- $\mu \text{m}$ complementary metal oxide semiconductor (CMOS) process. It achieves a 50.6% fractional bandwidth from 17.7 to 29.7 GHz. With a very low-power consumption of 7.2 mW, the saturation output power and efficiency are 0.28 dBm and 15.2%, respectively.

An injection-locked local oscillator (LO) generation targeting mm-wave multiband 5G communication is presented. With a band-selective injection-locked frequency multiplier (ILFM), the LO generation can operate from 21.7 to 41.7 GHz with a narrowband 6.2-to-8.0-GHz input source. An injection-locked amplifier (IL-amp) is cascaded for harmonic rejection. Fabricated in a 65-nm CMOS process, the proposed LO generation consumes 74.4-mW power with 5.0-dBm output power. A 25.3% input bandwidth is extended to a 63.1% output operating bandwidth with no further phase noise degradation. A −105.6-dBc/Hz phase noise at 1-MHz offset is measured at 24 GHz with a −42.7-dBc integrated phase noise. The LO generation rejects the unwanted harmonics to more than 30.0 dB and occupies 0.52 mm2.

This letter presents a 51–73-GHz high-output power and efficiency frequency doubler, which is fabricated in a standard 65-nm CMOS process. The proposed frequency doubler adopts a fourth-order transformer-based balun and a dual- LC tank network to achieve wideband operating at input and output ports. In addition, a common-source amplifier with a Gm-boosting technique is used as an output buffer to improve the output power and efficiency. The measured results show that the doubler achieves input and output return losses below −10 dB from 26 to 36 GHz and 53 to 80 GHz, respectively. The measured maximum gain is 0.8 dB at 66 GHz with 22-GHz 3-dB gain bandwidth at an input power of 1 dBm. Furthermore, with an input power of 7 dBm, the proposed doubler also exhibits a high efficiency of 19.5% and an output power of 5.7 dBm at 66 GHz. The dc power consumption is 14 mW with 1-V power supply, and the chip size is $0.63\times0.52$ mm2 including all test pads.

An injection-current-boosting (ICB) locking-range enhancement technique is presented to increase the locking range (LR) of the millimeter-wave (mm-wave) injection-locked frequency triplers (ILFTs). With a transformer-based fourth-order injection-coupling network, the parallel capacitance from the injection devices is resonated out over a wide frequency range and the injection current is boosted greatly. Analytical models of the ICB–ILFT are introduced, based on which the current-boosting phenomenon is analyzed. Meanwhile, the design concepts of the ultra-wideband mm-wave ILFT are presented. With the proposed ICB technique, an ICB-ILFT is designed and fabricated in 65-nm CMOS process. With a 0-dBm RF injection source, the ICB-ILFT can be locked from 22.8 to 43.2 GHz without calibration, achieving a 61.8% LR. The power consumption is only 5.0 mW and a 9.5-dB phase noise difference is observed, which is close to the theoretical value.

Here, a Ku-band transmit/receive (T/R) differential switch using the 180-nm CMOS process is presented. The differential structure method is chosen to realise easy integration with other RF components. From 15–18 GHz, the measured insertion loss (IL) of the switch in the transmit (TX) and receive (RX) mode is 4.3 and 4.1 dB, respectively. The isolation is better than 20 dB in both modes. The design achieves a measured input 1 dB power compression point ( I P 1 dB ) of 13.5 dBm at 17 GHz. The differential T/R switch integrated in a Ku-band-phased array transceiver demonstrates that it is a promising technology for implementing fully integrated transceiver.

Because of the metal density requirement in the advanced CMOS processes, dummy metal fills (DMFs) are unavoidable. The DMFs degrade the performance of the on-chip inductors, especially for the ones in the microwave and millimeter-wave circuits. This paper analyzes the impact of the floating DMFs and proposes a scalable double- $\pi $ inductor model including a tunable dummy metal density factor. The metal density factor can be integrated into the process design kit and determined by the designers to pass the design rule check. The proposed model predicts the decrease in the quality factor $(Q)$ and self-resonance frequency $(f_{\mathrm {sr}})$ with the density of DMFs increasing accurately. Furthermore, a fully automatic model extraction method based on the genetic algorithm is presented, which increases the accuracy of models. Inductors with DMFs of different densities are fabricated in a standard 180-nm CMOS technology. Then, the parameters of the inductors’ models are extracted to verify the idea. The models’ calculation results are compared with the measurement results up to 67 GHz.

This paper presents two low-profile right-handed circularly polarized (RHCP) antennas operating at 11GHz based on half-mode substrate integrated waveguide (HMSIW) and quarter-mode substrate integrated waveguide (QMSIW). Firstly, a substrate integrated waveguide (SIW) resonant cavity operating at 11 GHz is designed. By cutting the SIW cavity in half, a HMSIW cavity with size of 1.59λg × 1.07λg is obtained. Next, a half-octagon slot is etched on the top surface of the HMSIW cavity. Then, two square patches are placed in the slot, which gives the HMSIW CP antenna. Finally, by bisecting the HMSIW antenna directly, QMSIW antenna design with one square patch is completed, which has size of 0.86λg × 1.07λg. The proposed HMSIW and QMSIW antennas have 1.9% impedance bandwidth at 11GHz. Both antennas can achieve 0.14 GHz (1.27%) 3-dB AR bandwidth. The gain of the HMSIW and QMSIW antenna are 5.56 dBi and 5.52 dBi respectively. Furthermore, the proposed antennas can radiate RHCP beamwidth of 20°. Compared with the traditional SIW antenna, HMSIW and QMSIW antennas can reduce the size nearly 50% and 75% respectively, which are good candidates for miniaturization techniques.

This paper presents a Ka-band variable gain amplifier (VGA) with high gain resolution and low phase variation for millimeter-wave (mm-wave) 5G communications in 65-nm CMOS technology. The VGA employs three-stage differential common source (CS) structure. The input and output stages provide fixed gain, while the middle stage provides variable gain control. Based on the capacitive cross coupled neutralization (CCCN) technique and asymmetric capacitor structure, the proposed three-stage differential VGA achieves a measured gain resolution of 0.2 dB with 7-bit digital gain control in $23 \sim 28$ GHz. It realizes the phase variation lower than 2.3° with 6.2 dB gain control range at 28 GHz. The measured peak gain is 29.4 dB with a 3-dB bandwidth of $23.5 \sim 27.5$ GHz. The core chip area is 0.36 mm2 excluding pads.

This paper presents a new scalable 2-π equivalent circuit model of on-chip spiral inductors. The model characterizes on-chip inductors of variable geometrical sizes and number of turns. The density distribution of the magnetic and electric field effect in the metal traces forms the bases for lumped circuit element characterization of the inductor parasitic. The study, therefore, uses the RLC network algorithm to compute a new equation for predicting the self-resonance frequency of on-chip inductors. Inductance, quality factor, and S-parameter plots are shown as the results of the different turns and sizes. The verification of the model illustrates good agreement with the measurement data up to 40GHz. Hence the root-mean-square error of the quality factor of the model with the measured data is 0.0332. The model further demonstrates sufficient reliability to predict the performance of the on-chip inductors in simple RFIC design.

In this paper, a fabrication method of bendable gallium nitride (GaN) high-electro-mobility-transistor (HEMT) with state-of-the-art power performance is demonstrated for microwave application. Firstly, in the thinning process, a 5 µm remained silicon carbide (SiC) is used as thermal transition layer by consideration of thermal transmission. Furthermore, a 30 µm Parylene-C film deposited on the SiC substrate by using CVD method at room temperature minimize degradation due to extra strain induced in the conventional transfer process. By using the methods above, the fabricated 10 × 100 × 0.25 µm2 devices exhibited 418 mW output power at 3 GHz with a power added efficiency (PAE) over 40% at flat condition. Under the maximum 0.75% strain condition, the output power degraded less than and the PAE degraded less than 3%. The proposed fabrication methods can be used for flexible microwave GaN amplifiers in flexible wireless systems.

This paper presents a multi-ratio injection-locked frequency multiplier (MR-ILFM) targeting millimeter-wave (mm-wave) multiband 5G communications. With only low-frequency narrow-bandwidth input signals required, difficulties in generating low-phase-noise mm-wave wideband signals can be solved by switching the multiplication ratio of the MR-ILFM for bandwidth extension. Issues on suppressing undesired harmonics in multi-ratio multipliers are considered, and an impulse sensitivity function (ISF) based analysis is adopted to show the superior harmonic rejection properties of injection locking. With the use of injection locking and ILFM cascading, the harmonic rejection reaches to 57.7 dBc. The proposed MR-ILFM has × 5 and ×7 multiplication ratio, and 24 switchable frequency bands for ratio switching. Fabricated in 65 nm CMOS process, the MR-ILFM consumes 10.0-mW power and can operate from 22.4 to 40.6 GHz with 4.3-to-5.8-GHz inputs.

Semiconducting single-walled carbon nanotubes (SWNTs) are potential active materials for fast-growing flexible/wearable applications with low-power dissipation, especially suitable for increasingly important radio-frequency (RF) wireless biosensor systems. However, the operation frequency of the existing flexible carbon nanotube field-effect transistors (CNT-FETs) is far below the current state-of-the-art GSM spectrum frequency band (typical 850 MHz) for near-field wireless communication applications. In this paper, we successfully conduct a 900 °C annealing process for the flexible CNT-FETs and hence significantly improve their operation frequency up to 2.1 gigahertz (GHz), making it possible to cover the current GSM spectra for integrated wireless sensor systems. The high-temperature annealing process significantly improves the electrical characteristic of the flexible CNT-FETs by removing the surfactant impurities of the SWNT materials. The obtained flexible CNT-FETs exhibit record transconductance (

In this paper, analytical gate capacitance models for a large-signal compact model of AlGaN/GaN high-electron mobility transistors are proposed. Different from the MOSFET devices, different depletion regions on either side of the gate are fully considered for high-voltage GaN devices. The depletion regions are bias-dependent to implement the capacitance models into the large-signal compact model. A transfer function is proposed to characterize the switching behavior of the capacitances between on- and off-states, which is essential to describe all the states of a device, for example, operating at Class-B. Different from previous works, the current saturation phenomenon is taken into account in determining the intrinsic capacitances which are induced by nonstatic channel charge. The capacitance models can be easily implemented into the virtual-source-based model to accurately predict the S-parameters and large-signal output characteristics.

Graphene field-effect transistors (G-FETs) on flexible substrates have demonstrated much higher strain limits than that on rigid substrates. In this letter, G-FETs with an extrinsic ${f}_{\textrm {max}}$ of 28 GHz on flexible polyethylene terephthalate (PET) substrates are presented. Polyimide film benzocyclobutene with 50-nm thickness is coated on a PET substrate surface for optimizing the carrier transport. The results show that the hole mobility can reach up to 1738 cm2/V.s. An Au-supported graphene transfer technology is used to facilitate the quality of graphene in G-FETs and reduce the output parasitic resistance to $50~\Omega $ . The measured figure of metric of “ ${f}_{\textrm {max}}\cdot {L}_{\textrm {g}}$ ” is $8.4~\textrm {GHz}\cdot \mu \text{m}$ , which is 105% higher than the highest reported results on polymeric substrates. The RF performance of flexible G-FETs under the bending condition is also studied. The results of the letter will be useful for developing the millimeter-wave flexible graphene integrated circuits.

A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW.

Nervilia fordii (Hance) Schltr. has been widely used as a medicinal and edible herb in Southwest China and Southeast Asia. In this study, NFP-1, a new water-soluble polysaccharidewith a purity of 97.8%, was purified from water extract of Nervilia fordii by DEAE-cellulose and Sephadex G-100 chromatography. NFP-1 has a relative molecular weight of 950 kDa determined by high performance gel-permeation chromatography (HPGPC). Its monosaccharide compositions were analyzed by high performance liquid chromatography (HPLC) after pre-column derivatizing its hydrolysate with 1-phenyl-3-methyl-5-pyrazolone (PMP). NFP-1 mainly consists of galactose, arabinose, rhamnose, and galacturonic acid. Based on FT-IR, methylation and GC–MS analysis, and NMR, the structure unit of NFP-1 was established as →4)-α-Rhap-(2→ 4)-α-GalpA-(1→2)-α-Rhap-(1→2)-α-Rhap-(4→1)-β-Galp-T containing two branch chains of →2,4)-α-Rhap-(1→5)-α-Araf-(1→3)-α-Araf-(1→, and →2,4)-α-Rhap-(1→4)-β-Galp-(1→. The immunomodulatory assays revealed the dual-functionalities of NFP-1. NFP-1 could significantly induce the secretion of nitric oxide (NO), and promote the secretions of TNF-α, IL-6, and IL-1β in RAW264.7 macrophages. NFP-1 could also significantly inhibit the production of NO, depress the secretions of TNF-α, IL-6 and IL-1β in RAW264.7 macrophages activated by lipopolysaccharide (LPS), and promote the production of IL-10 meanwhile. Our study suggested that Nervilia fordii could be an ideal medicinal or functional food due to its dual immunomodulatory activities., Graphical abstract Unlabelled Image

This paper presents an improved ultrawideband open-short de-embedding methodology. In contrast to the conventional measurement-based open-short de-embedding method, the presented method is a measurement-calculation hybrid method. First, the open and short de-embedding structures are measured, and the corresponding scattering parameters are obtained. Based on this, lumped-parameter models of the open and short de-embedding structures are established. Then, the established models are modified to solve the over de-embedding problem. Finally, the modified de-embedding structure models are implemented in the scattering parameters of device test structures to achieve ultrawideband de-embedding. To verify the proposed de-embedding method, the method is applied to active devices. The results before and after de-embedding are compared under multiple bias conditions. Furthermore, the results after de-embedding based on the conventional open-short method and the proposed method are compared up to 220 GHz. These results show that using the proposed method can achieve accurate ultrawideband de-embedding up to the terahertz frequency band.

This letter presents a 62–85-GHz high linearity upconversion mixer, which is fabricated in a standard 65-nm CMOS process. The proposed upconversion mixer adopts a transconductance stage which consists of a common-source path and a cross-coupled common-gate path to enhance the linearity. In addition, the transconductance stage can also be beneficial to realize a wide IF impedance matching. To achieve a compact layout, a transformer is used to serve as an inductive load stage, a balun, and output matching network. The measured input 1-dB compression point (IP1 dB) is 2.14 dBm at 77 GHz. The measured maximum conversion gain is −4.3 dB with a 3-dB RF bandwidth from 62 to 85 GHz. Furthermore, the proposed mixer also exhibits a wide 3-dB IF bandwidth of 18 GHz, which can sustain a high data-rate transmission.

An eight-core fundamental VCO with ultralow phase noise (PN) performance is presented. Eight VCOs are in-phase coupled for low PN, and a 9-dB PN improvement is achieved. A scalable layout methodology is presented to solve the layout difficulties in multicore VCOs. Two VCO cores are connected together directly to form a VCO cell. By simply connecting $N$ /2 VCO cells, the PN of the entire multicore VCO will achieve a 10 logN dB PN improvement compared with the single VCO core. The proposed eight-core VCO is fabricated in 65-nm CMOS and occupies 0.15 mm2. The measured PN is −105.5 dBc/Hz at 1-MHz offset, with the tuning range from 62.2 to 67.3 GHz (7.9%). The VCO consumes 61.2-mW power with the figure-of-merit of −183.5 dBc/Hz at 1-MHz offset.

This paper presents a high linearity and low noise mixer for millimeter-wave applications in 65-nm CMOS process. A noise-reduction transformer with harmonic suppression is utilized and inserted between transconductance stage and switch stage to improve the linearity and noise figure (NF). Benefitted from the transformer-coupling cascode topology, the mixer can operate at a low supply voltage without sacrificing the linearity. In addition, this topology provides a great freedom for the choice of biases in transconductance stage and switch stage. Thus, linearity and noise performance can be further improved by optimizing the bias conditions of the two stages. According to experimental results, the proposed mixer exhibits a maximum conversion gain of 9.5 dB and a minimum single sideband NF of 9.2 dB with a local oscillator (LO) power of −3 dBm. The 3-dB bandwidth ranges from 62 to 90 GHz. The input 1-dB compression point ( $P_{\mathrm {1~dB}}$ ) is −3.8 dBm at 77 GHz. Due to the compact and fully symmetrical layout, the LO-to-RF isolation is better than 48 dB.

In this paper, a wideband model for on-chip interconnects with different shielding structures is proposed. In order to improve the performance of interconnects, solid ground, floating shields, and parallel ground shields are often employed in real applications. Based on the transmission line theory and electromagnetic wave theory, these three different shielding structures are analyzed and discussed. Also, many parasitic effects such as eddy current, skin effect, proximity effect, and substrate loss have been taken into consideration to improve the precision of the proposed model. It is shown that the simulated results of the model are in good agreement with the measured ones up to 110 GHz. The validity of the proposed model has been proven.

A scalable electrothermal large-signal AlGaN/GaN HEMTs model for both fundamental and multiharmonics is presented based on the modified Angelov model. To obtain accurate scalability of the electrothermal model, a simple empirical expression is proposed for the geometric and power-dissipation-dependent nonlinear thermal resistance $R_{{\mathrm {th}}}$ . Only one additional parameter with linear scaling rule is needed in the drain-source current ( $I_{{\mathrm {ds}}}$ ) model for a scalable large-signal multiharmonic model. The proposed model has been validated by different AlGaN/GaN HEMTs characterized by on-wafer measurements. It shows that the presented scalable model can well predict the dc $I$ – $V$ , pulsed $I$ – $V$ , scattering (S) parameters, and large-signal performance up to third harmonic. Furthermore, to further validation, a C-band power amplifier is designed. The amplifier is realized using the second-harmonic tuned approach to enhance the efficiency. Measurement results show that the GaN high power amplifier (HPA) microwave monolithic integrated circuit (MMIC) exhibits more than 40% power-added efficiency and 60-W output power ( $P_{{\mathrm {out}}}$ ) with associated gain of 25 dB in 5–6 GHz measured at 28-V drain voltage and pulse signal with 100- $\mu \text{s}$ pulsewidth and 10% duty cycle. The area of the chip is 3.2 mm $\times5.3$ mm (16.96 mm2). These results show that the proposed model will be useful for high-efficiency HPA MMIC design.

In this letter, the channel current magnetic effect of complementary metal–oxide–semiconductor (CMOS) transistors is studied, and an improved small-signal equivalent circuit model (SSECM) is proposed. Silicon-on-insulator (SOI) CMOS transistors were fabricated and measured in a commercial 0.18- $\mu \text{m}$ process. Then, a series RL network is introduced into the classical transistor SSECM to characterize the channel current magnetic effect. To validate the model, the scattering parameters calculated by the model are compared with the measurement data. The results show that the root-mean-square error (RMSE) of the scattering parameters is less than 0.02 up to 2 GHz. And in the whole investigating frequency range, the RMSE is less than 0.063. Compared with the conventional model, which does not consider the channel current magnetic effect, the proposed model improves the accuracy in the lower frequency range remarkably.

An RF CMOS model incorporating an improved substrate coupling network is developed. The proposed model focuses on characterizing the nonlinear phase of S12 when a transistor is under zero-bias condition. In addition, a corresponding parameter extraction technique of the model is proposed. To validate this model, a set of transistors fabricated in a commercial 90-nm CMOS process is investigated under multibias conditions. Comparison between measurement and calculation results shows that good agreement has been achieved, which indicates that the proposed model can accurately characterize the performance of transistors up to 66 GHz.