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To deeply understand the charge trapping process in high-k gate stacks, we theoretically investigate the hole trapping characteristics of interfacial oxygen vacancies in (110) and (100) Si/SiO 2 /HfO 2 stacks. Si/SiO 2 and SiO 2 /HfO 2 interfacial defects are studied, and the hole trapping rate of each defect is calculated through ab initio simulation combining density-functional theory and Marcus theory. Among the possible hole traps considered in this work, it is suggested that the oxygen vacancies at SiO 2 /HfO 2 interface are the dominant under strong negative gate bias stress, and those at Si/SiO 2 interface can be effective traps only when hydrogen atom (H) or hydroxyl (OH) is induced at the vacancy. Moreover, the most dominant hole trap among the considered traps in the (110) structure locates at the Si/SiO 2 interface, while that in the (100) structure locates at the SiO 2 /HfO 2 interface.

Lithium sulfur (Li-S) batteries are very promising electrochemical storage system due to their high gravimetric energy density and low cost. Enormous efforts have been put on Li-S battery to achieve its commercialization. The function of electrolyte is a key issue in achieving the high performance of Li-S system, and several additives have been tried. But very few works have been working on the electrolyte optimization method with the consideration of over-all performance, including cycling stability, rate capability, especially self-discharge prevention ability, and the consideration of loading condition. In this work, we focus on the incorporation of room temperature ionic liquid (IL) as co-solvent, and the effect of IL in mitigating the polysulfide dissolution via systematical mechanism study of self-discharge phenomena. Moreover, the optimization of IL incorporation ratio is discussed for the sake of the better over-all electrochemical performance of Li-S cell by considering cycling stability, rate performance and self-discharge prevention ability, which is found to vary with loading condition. The improved understanding of the effect of IL on battery performance will help the development of electrolyte for Li-S batteries.

In this paper, we change terminal loads of a microstrip line to separate electric field coupling and magnetic field coupling between a microstrip line and a transverse electromagnetic (TEM) cell during radiated emission measurement. Such separation can also be validated by another terminal load. After validation, the effect of termination on both couplings is investigated, and the requirements of termination impedance to suppress the two couplings are revealed. In addition, we find that the linear physical models deriving both lumped coupling parameters only hold below a limited frequency.

Displacement damage induced degradations in four-junction solar cells are investigated by electron irradiation and TCAD simulation. It shows that In0.3Ga0.7As cell is the key sub cell to affect the radiation tolerance of four-junction solar cell. Although irradiation will introduce relatively uniform displacement damage in each sub cell of four-junction solar cell, the In0.3Ga0.7As cell show the most significant degradation under the same radiation damage conditions. The radiation harness of the four-junction solar cell can be promoted by increase the short circuit current of In0.3Ga0.7As cell before irradiation, which is verified by the TCAD simulations. The relationship between electrical characteristics degradations and the displacement damage dose is established for four-junction solar cells. Then, the equivalent displacement damage dose method has been used to predict the on-orbit degradation of four-junction solar cells. The degradations of the four-junction solar cells on typical geosynchronous earth orbit are calculated by combining Monte Carlo simulations and ground irradiation test data.

This paper presents a novel VSWR measurement system for high power electronic vacuum device such as traveling wave tube in working mode. The measurement principles of this VSWR measurement system have been presents. The feasibility of this VSWR measurement system has been analyzed.

In this paper, we investigated on -state electroluminescence (EL) characteristics in fresh GaN-based HEMTs under different on -state bias conditions. It demonstrated that: 1) the intensity of the on -state EL emitted by the GaN-based HEMTs with relatively high ${\rm V}_{\rm DS}$ $({\rm V}_{\rm DS}>10\ \hbox{V} )$ monotonically increased as the gate voltage increased; and 2) the distribution of the intensity of the on -state EL was uniform along the gate and across the device before stress tests. The degradation process and mechanisms of the devices in the high temperature operation (HTO) stress were also analyzed based on the on -state EL characterization, the electrical measurement, and failure analysis. It demonstrated the following. First, the on -state EL distribution of the device after step HTO (S-HTO) stress tests was no longer uniform along one of the fingers, which indicated that the degradation was related to this finger. This hypothesis was confirmed by the SEM observation after the deprocess of the gate metal and the SiN passivation layer. Second, a new degradation mechanism of AlGaN/GaN HEMTs that caused the abrupt degradation in the S-HTO stress was identified and related to the emergent, localized, and jagged crack under the gate metal. Third, there was no abrupt degradation in the long-term HTO (LT-HTO) stress test. However, the on -state EL intensity of the inner fingers in the device after the LT-HTO stress test decreased more than that of the outer fingers, which meant that the degradation of the inner fingers was faster than that of the outer fingers as a result of the higher temperature caused by self-heating in the inner region of the device. Finally, the gradual degradation in the LT-HTO stress test was ascribed to the gradual formation of structural damage along the drain side of the whole gate edge, which was confirmed by the SEM observation.

As we known, the measurement of junction-to-case thermal resistance (R th -JC) of semiconductor power devices is very important. In this paper, an approach of transient dual interface method (TDIM) with gate-source voltage (Vg s ) as the temperature sensitive electrical parameters (TSEP) was investigated for the measurement of R th -JC of packaged SiC MOSFET. The measured R th -JC value of packaged SiC MOSFET is in the range of 1.61 K/W to 1.76 K/W, and compared with the typical value of device specification, the maximum error is 5.29 %. The results show that the thermal resistance measurement of packaged SiC MOSFET by TDIM with Vg s as the TSEP is feasible, and it is of good accuracy and reproducibility.

Semiconductor technology and packaging is advancing rapidly toward system integration where the packaging is co-designed and co-manufactured along with the wafer fabrication. However, materials issues, in particular the mesoscale microstructure, have to date been excluded from the integrated product design cycle of electronic packaging due to the myriad of materials used and the complex nature of the material phenomena that require a multiphysics approach to describe. In the context of the materials genome initiative, we present an overview of a series of studies that aim to establish the linkages between the material microstructure and its responses by considering the multiple perspectives of the various multiphysics fields. The microstructure was predicted using thermodynamic calculations, sharp interface kinetic models, phase field, and phase field crystal modeling techniques. Based on the predicted mesoscale microstructure, linear elastic mechanical analyses and electromigration simulations on the ultrafine interconnects were performed. The microstructural index extracted by a method based on singular value decomposition exhibits a monotonous decrease with an increase in the interconnect size. An artificial neural network-based fitting revealed a nonlinear relationship between the microstructure index and the average von Mises stress in the ultrafine interconnects. Future work to address the randomness of microstructure and the resulting scatter in the reliability is discussed in this study.

Single-event performance of 65 nm CMOS SRAM technology was revealed by Monte-Carlo methods, with heavy ions energy ranging from 20 MeV/n to 2 GeV/n. By comparing the energy-deposition spectrums in sensitive volumes (SV) and single event upset (SEU) cross sections, it was found that secondary electrons and nuclear reactions of the 200 MeV/n incident ions have significant impact on the device response. Secondary electrons excited by the energetic space ions can spread beyond the SV of the 65 nm bulk CMOS SRAM and result into partial collection of the ion track. This mechanism causes the constant increase of SEU cross section with ion LET, even deviating from the surface area of the SV by 3.3×. Nuclear reaction can lead to unexpectedly large energy-deposition events in the SV by 10x than the initial LET, which create SEU cross sections in the sub-LET th region, although with lower probability than direct-ionization process by 104×∼105×. Higher ion energy seems to enhance the influence of secondary electrons and nuclear reaction. Moreover, soft error rates of the 65 nm bulk CMOS SRAM technology on GEO were predicted and discussed.

In this paper, a simulation tool named the neutron-induced single event effect predictive platform (NSEEP2) is proposed to reveal the mechanism of atmospheric neutron-induced single event effect (SEE) in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory (SRAM) device can be considered to calculate the real-time soft error rate (RTSER) in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP2, RTSERs of 90 nm–32 nm silicon on insulator (SOI) and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

The instabilities of indium–zinc oxide thin film transistors under bias and/or illumination stress are studied in this paper. Firstly, illumination experiments are performed, which indicates the variations of current–voltage characteristics and electrical parameters (such as threshold voltage and sub-threshold swing) are dominated by the stress-induced ionized oxygen vacancies and acceptor-like states. The dependence of degradation on light wavelength is also investigated. More negative shift of threshold voltage and greater sub-threshold swing are observed with the decrease of light wavelength. Subsequently, a negative bias illumination stress experiment is carried out. The degradation of the device is aggravated due to the decrease of recombination effects between ionized oxygen vacancies and free carriers. Moreover, the contributions of ionized oxygen vacancies and acceptor-like states are separated by using the mid-gap method. In addition, ionized oxygen vacancies are partially recombined at room temperature and fully recombined at high temperature. Finally, low-frequency noise is measured before and after negative bias illumination stress. Experimental results show few variations of the oxide trapped charges are generated during stress, which is consistent with the proposed mechanism.

The polarity effect of electromigration on the interfacial reactions of micro ball grid array (μBGA) solder joints was studied in terms of microstructural evolution. A dummy μBGA package with the same pair of solder joints was used to obtain reproducible results for a practical application. The μBGA package with Ni(P)/SnPb/Ni(P) structure showed a polarity effect on intermetallic compound (IMC) formation after stress by a current density of 3.0 × 10 3 A cm −2 at 120 °C, compared to the no-current case. Electric current enhanced the growth of Ni 3 Sn 4 at the anode and retarded it at the cathode because of the change in Sn diffusion induced by electromigration. The IMC growth at the anode was about one order of magnitude faster than that at cathode. The growth of IMC at the anode had a parabolic dependence on time since the square of thickness of IMC increases linearly with time. The real μBGA package has unique and more complicated geometry compared to ordinary diffusion couples. So not only the polarity growth of IMC but also the fast dissolution of Cu and Ni at specific positions was found with the μBGA package. The unique geometry of μBGA solder joints caused heat generation at the upside interfaces due to Joule heating. Because of the heat generation and the high interfacial energy at the triple point of upside interfaces, the electroless Ni(P) finishes and Cu trace are consumed rapidly in the region where the current is crowded. Thus electromigration induced the rapid dissolution of Ni and Cu into solder and then formed (Cu,Ni) 6 Sn 5 at the triple point of the current crowding region at high temperature. This is a rapid failure process because the localized fast dissolution of Ni and Cu accelerated the solid-state reaction between solder and electroless Ni(P) or Cu trace.

Based on a method combined artificial neural network (ANN) with particle swarm optimization (PSO) algorithm, the thermo-mechanical fatigue reliability of plastic ball grid array (PBGA) solder joints was studied. The simulation experiments of accelerated thermal cycling test were performed by ANSYS software. Based on orthogonal array experiments, a back-propagation artificial neural network (BPNN) was used to establish the nonlinear multivariate relationship between thermo-mechanical fatigue reliability and control factors. Then, PSO was applied to obtaining the optimal levels of control factors by using the output of BPNN as the affinity measure. The results show that the control factors, such as print circuit board (PCB) size, PCB thickness, substrate size, substrate thickness, PCB coefficient of thermal expansion (CTE), substrate CTE, silicon die CTE, and solder joint CTE, have a great influence on thermo-mechanical fatigue reliability of PBGA solder joints. The ratio of signal to noise of ANN-PSO method is 51.77 dB and its error is 33.3% less than that of Taguchi method. Moreover, the running time of ANN-PSO method is only 2% of that of the BPNN. These conclusions are verified by the confirmative experiments.

Single event effects (SEE) in two commercial-off-the-shelf (COTS) Ferroelectric Random Access Memory (FeRAM) technologies were investigated by heavy ions and pulsed laser irradiation. At least six SEE types were observed. The majority of the errors were caused by anomalies in the peripheral circuit, which was confirmed by the mirror SRAM technique, non-volatile test mode, and the detailed error information. Single event upset, single event functional interrupt and single event latchup cross sections were reported, with weak dependence on the supply voltage.

Hardware Trojan embedded by adversaries has emerged as a serious security threat. Until now, there is no a universal method for effective and accurate detection. Since traditional analysis approaches sometime seem helpless when the Trojan area is extremely tiny, this paper will focus on the novel detection method based on frequency spectrum analysis. Meanwhile, a failure physics model is presented and depicted in detail. A digital CORDIC IP core is adopted as a golden circuit, while a counter is utilized as a Trojan circuit. The automatic test platform is set up with Xilinx FPGA, LabVIEW software, and high precision oscilloscope. The power trace of the core power supply in FPGA is monitored and saved for frequency spectrum analysis. Experimental results in time domain and frequency domain both accord with those of theoretical analysis, which verifies that the proposed failure physics model is accurate. In addition, due to immunity to vast measurement noise, the novel method processing in frequency domain is superior to the traditional method conducting in time domain. It can easily achieve about 0.1% Trojan detection sensitivity, which indicates that the novel detection method is effective.

Electromagnetic interference effects in the bipolar voltage comparator was investigated in this paper. By using of bulk current injection (BCI), the coupling current stimulated by high power electromagnetic pulse was simulated. The experimental results shown that the aberrations such as pulse deriving and pulse width altering will come into being in the output waveforms of LM139 after current injection respectively. Furthermore, the coupling effect of pulse deriving and pulse width broadening were observed simultaneously in the higher level current injections.

Single event transient effect in the linear voltage comparator is investigated in this paper. The circuit level simulation is performed to analyze the output response of LM139 voltage comparators with single event transients (SETs). Simulation results show that input stage and two current sources are the most sensitive parts to the single event transient effects. The output responses were shown as transient pulses with different width. Based on the simulation results, the susceptive parts of a LM139 voltage comparator are acquired. Furthermore, the results above can also be helpful to further harden designs of linear ICs.

Malicious modification of integrated circuits referred to as Hardware Trojan fabricated in untrusted foundries pose a growing concern on reliable and security application. In order to ensure trusted in-filed operation of integrated circuits, many techniques are developed to authenticate Hardware Trojan often called trojan detection. Among these techniques side-channel signals analysis is a widely researched method to detect Hardware Trojan but suffer from sensitivity decreasing caused by increasing process variation effects. In this paper, we propose a non-invasive Hardware Trojan detection method which is immune to process variation effects. The method exploits the intrinsic relationship between transient current (I ddt ) and quiescent current (I ddq ) and I DDT of different test vectors that can eliminate the effects of process variation. The proposed method is verified by Hspice simulation carried on ISCAS 85 benchmark circuit. The 100 times simulation results with 130nm CMOS process using Monte Carlo method show that the suggested methods are capable of detecting the Hardware Trojan whose equivalent area is as small as 10"4 of the total size of the circuit in the presence of ±7% parameter(threshold voltage) variations.

Modern science is pushing Integrated circuits (IC) to higher level of integration, internal clock frequency and translation rates. In this context, the electromagnetic compatibility (EMC) of IC has gained more and more significance in the design stage, as well as the qualification. In this paper, the near field characterization is performed on a newly-built scanning system, in which a spectrum analyzer is used to detect the electromagnetic signal of the device under test. The scanning and detecting for the electromagnetic interference (EMI) is verified by a testing on the magnetic field above a microstrip. And then we apply the method to near field characterization of EMI for a microcontroller (C8051F120). The microcontroller is set to work at two different frequencies, 24.5MHz and 98MHz. The harmonic frequency is found in the range up to 500MHz. It is found that the excitation of phase lock loop module is significant for the whole electromagnetic radiation. The pins with higher EMI radiation are also identified in this paper.

Malicious modification of integrated circuits, namely Hardware Trojan, has emerged as a major security threat. Since it is extremely difficult to detect the presence of such small Trojan circuits using only logic test or side-channel analysis, this paper presents a novel test method combining logic test and side-channel test together. An 18-bit CORDIC IP core is adopted as a golden circuit, while a 2-bit counter is applied as a Trojan circuit. The automatic test platform is set up with Xilinx FPGA, LabVIEW software, and high precision oscilloscope. Meanwhile, the power traces of power supplies V ccint or V ccaux in FPGA are both monitored to enhance the detection sensitivity. The relevant test flow chart is also depicted in detail. Experimental results demonstrate that the novel test method can easily achieve about 0.1% Trojan detection sensitivity when principal component analysis approach is adopted as the data processing algorithm.

Total ionizing dose (TID) radiation effects in the bipolar voltage comparator with different biases and dose rates were investigated in this paper. The experimental results show that offset voltages shift after irradiation. Dominated by the current gain degradation of differential PNP transistors, the shifts of offset voltage and output characteristics were significantly affected by biases at high dose rate. Dominated by the current gain degradation of NPN transistors, the shifts of offset voltage and output characteristics were similar in all biases at low dose rate.

This paper proposed a two-dimensional thermal impedance model for amorphous silicon thin film transistors (a-Si:H TFTs) from a system of coupled energy equations, heat flowing equations and boundary conditions. By using of this model, the channel temperature distribution and thus the maximum channel temperature can be calculated. This model can be applied to describe the thermal behavior and thermal reliability of a-Si:H TFTS in the design phase.

The effect of Pb content in the rang of 0∼37wt.% on solidification behavior and shear performance of Sn3.0Ag0.5Cu/Cu joint was investigated. It was shown that Pb contamination showed a significant influence on the solidification behavior of Sn3.0Ag0.5Cu/Cu joint. A little amount of Pb resulted in the formation of ternary eutectic Sn-Pb-Ag phase with a low melting temperature and a mushy region between primary solidification phase and Sn-Pb-Ag phase during solidification stage of mixed joint. The mushy zone decreased with the increasing of Pb content and disappeared when Pb content in solder matrix of joint exceeded 18.34wt.% The addition of Pb in Sn3.0Ag0.5Cu/Cu joint has been shown to be beneficial to improve the shear force of SAC/Cu joint by using ball shear test method and the shear force of single interface mixed solder joint was in parabolic relationship with Pb content. The formation of ternary eutectic Sn-Pb-Ag phase and mushy zone in solidification stage had no obvious influence on the shear force of mixed solder joint.

Firstly, the storage failure mode and failure mechanism study of the klystron was carried out, the main failure modes of klystron in storage were summarized, and the failure mechanism and failure reasons of the main failure mode were analyzed. The results of the study showed that the vacuum degree decline is the main reason for the failure in long-term storage of klystron. The vacuum degree decline of tube is due to the residual gas of in seal manufacturing process or the deflation and shell leakage of the tube during the period of storage. Secondly, the generation process of residual gas was studied. At last, a failure sample of long-term storage klystron was analyzed; results showed that the failure mechanism was due to a large number of evaporation the cathode emission material which induced the serious degeneration of cathode, then the cathode emission current reduced and the out power declined. The reason of cathode degradation was vacuum degree decline in long-term storage process, ions back to the cathode surface that caused the huge evaporation of cathode emitting material.

When the Minimum channel length shrink to 0.13μιη, As the device geometry size scaling down while the operation voltage of the device decreased, but the electric field increase. The current density is still high in interconnect line, various failure mechanisms still exist in the process generation of copper interconnect/low k dielectric integrated, the reliability is still a very important problem. By using accelerated test, the reliability of the main failure mechanisms have been evaluated, the results showed that the lifetimes of main failure mechanism can achieve the requirements of more than 10 years lifetime. In the same time, NBTI effect will become the main failure mechanism in ultra deep sub-micron CMOS process when Minimum channel length becomes less than 0.13 μιη.

Experimental evidences are presented showing the variety of supply voltage dependence of single event upset (SEU) sensitivity in diverse SRAM devices. Devices under test (DUTs) from Alliance Memory, ISSI and IDT companies with different technologies were irradiated by several kinds of heavy ions at Heavy ion Research Facility in Lanzhou (HIRFL) cyclotrons. For the Alliance 256 kb SRAM device, SEU cross section increases by more than one order of magnitude as supply voltage decreases from 5.0 V to 3.0 V. SEU data of Alliance 64 kb SRAM also exhibits significant supply voltage dependence. The reduction of critical charge is the predominant factor worsening the device performance. While for the Alliance 8 Mb, ISSI 2 Mb and IDT 256 kb SRAM devices, no obvious trend was observed, which is attributed to the negligible net contribution of competing mechanisms. Those results suggest that the worst-case supply voltage for evaluation of SEU sensitivity depends on the test devices.

We have submitted the AlGaN/GaN High electron mobility transistors (HEMTs) to the high temperature reverse bias(HTRB) stress to assess their reliability for high voltage operations. The effects of HTRB stress as a function of the V DG and stress time on the DC parameters and trapping effects were investigated. The study was based on combined DC and pulsed characterization, transient measurement. It provides the following information: 1) the exposure to HTRB may result in a permanent degradation in on-state current, the transconductance, and a slightly positive shift of threshold voltage; 2) the high temperature (T A =175°C) step reverse bias (V DG stepped from 20V to 80V) stress tests revealed that the gate leakage current I GS increased abruptly after 50V stress voltage V DG ; 3) interestingly, the long term high temperature moderate reverse bias(V DG 40V) stress resulted in some positive effects such as the decrease of gate leakage current, improved gate lag characteristics and the decrease of current collapse in pulsed measurement during the whole test; 4) the reverse-bias voltage is the key factor but for reliability assessment of AlGaN/GaN HEMTs for high voltage application based on HTRB stress; 5) The degradation mechanism of the gate leakage current under relatively high voltage HTRB test has been ascribed to the degradation metal and semiconductor interface; 6) the improved I-V characteristic under moderately voltage HTRB test has been attributed to the reduction of lateral tunneling current.

This paper presents an equivalent circuit approach to evaluate the effect of near-zone electromagnetic interference on the shielding effectiveness (SE) of an apertured rectangular enclosure. The approach is an extension of Robinson's equivalent circuit formulation. The extension in this paper is carried out by using an electric dipole to represent the external interference and applying the electric field at the aperture caused by the dipole to replace Robinson's incident plane wave. The SE correlates to the dimensions of the enclosure and the aperture. The distance from the interference to the enclosure and the observed position within the enclosure are significant parameters on the SE evaluation. The shapes of the aperture also affect the SE. This equivalent circuit approach based on the available analytical formulation provides a fast means of investigating the effect of design parameters on the SE of an apertured enclosure for near-zone interference and can be used for designers of shielded enclosures.

This paper presents a novel optimization design method for the closed loop control of the sense mode of a MEMS gyroscope, which aims at improving the performances and reliability of the control system.

Along with the infrared technical rapid development, infrared radiation (IR) thermal imaging technology is widely applied in device and circuit reliability research. For device and circuit reliability study, IR thermal imaging technology is best for getting the peak temperature and temperature distribution. With the peak temperature and temperature distribution, the thermal information of the devices were evaluated and optimized to meet the design requirement. Secondly, IR thermal imaging technology is used to position hotspot for failures analysis, example for especially increases in elevated leakage currents. However, IR thermal imaging technology can provide evidence of excessive temperature rise due to power dissipation. It can identify root-cause of failures at temperatures below expectations.

Space traveling wave tube (TWT) is one kind of microwave vacuum tube for communication, which must have high reliability, high power. The life of the space TWT is requested for a long lifetime of 10–15 years. In order to shorten the testing process, accelerated aging tests are performed at higher than normal operating temperature and currents of cathode. But in the process of the actual test, the cathode degradation is very slow, the test time is too long for all samples failing to get the lifetime data. In order to obtain the lifetime of the long life tube in a short time, it is necessary to investigate a new method which can evaluate the long lifetime through short-term working data. This paper introduced how to solve the zero-failure test data with small samples. With no failure data in data processing of life test, parameter degradation extrapolation method is used to obtain the failure life time. All the expected life of the sample was estimated of each test samples by least-square method for linear fitting and the goodness of fit and the significance testing was done.

This work aims to characterize the microstructure and temperature field of the hermetic packaging structure by welding the cover made of Kovar alloy and the base made of a low-carbon low-alloy steel (i.e., #10 steel) using parallel seam welding (PSW) process. The microstructure of welded joints and distribution of elements were analyzed by scanning electron microscopy (SEM) equipped with energy dispersive spectrometer (EDS). Welding mechanism of PSW is discussed and temperature field of PSW is studied by a nonlinear transient finite element analysis. In FEM simulation, the surface contact pair is created to form weld beam and the heat generated by a pulse current is taken as a moving heat source. The results show that the maximum temperature in the weldment is 1105.3 °C, which is below the melting point of Kovar alloy and #10 steel (both in 1400∼1500°C). The cross-sectional microstructure analysis results of the welded joint show that welded junction is localized between the plating layers of two base materials, both Kovar alloy and #10 steel did not melt during the welding process. Numerical simulation value of the temperature at the plating coat layer on Kovar side is larger than that on #10 steel because of boundary conditions and thermal conductivity. Same phenomenon can be seen at the location 3 mm away from the weldment. The temperature on the node of Kovar with a distance of 5 mm from the weldment is 796 °C.

The total-dose-induced edge effect in SOI NMOS transistors with different layouts is presented. Experimental results show that the edge effect is very sensitive to their layouts. Among the transistors hardened by design, the H-gate and ringed-source transistors do not behave as expected. At high radiation doses, the edge leakage currents appear for both transistors. Compared to the unhardened two-edged transistor, their total-dose-induced edge leakage paths and the role of layouts on edge effect are discussed.

Electromigration has a potential to be used as a process for microstructural design in ultrafine interconnects such as TSVs and microbumps. This study investigates the relationship between the electromigration and the microstructural evolution in a Cu/Sn-microbump/Cu structures through a modeling and simulation approach. The electromigration-induced polarity effect on the interfacial Cu6Sn5 and Cu3Sn compounds as well as the acceleration of the Cu pad consumption are found, as previously reported in experimental studies. In addition, the simulation results predict that the Cu6Sn5 grains at the anode become finer when an current is applied. The polarity effect is weaker when the pad size increases from 10 μm to 20 μm. In the larger microbump, the growth of the interfacial Cu6Sn5 is slower, while the growth of the interfacial Cu3Sn and the consumption of the Cu pad is faster. The growth of the interfacial IMCs and the consumption of the Cu pad at both electrodes are faster in the hourglass-shaped microbump. The interfacial Cu6Sn5 layer at the anode in the barrel-shaped microbumps appears to be convex, while concave in the hourglass-shaped microbump. The polarity effect becomes more pronounced when bulk Cu6Sn5 grains in the Sn microbump are dissolved and redeposited onto the interfacial Cu6Sn5 at the anode. The bulk Cu6Sn5 grains are predicted to migrate towards the anode driven by the electric current.

Inherent reliability of Surface acoustic wave filters plays a key role for its application in the mobile communication systems. Construction analysis is an effective method for evaluating the inherent reliability of electronic components. This work provides a construction analysis process for the surface acoustic wave filters, which includes external encapsulation analysis, internal encapsulation analysis and chip-level analysis. The results show that oxidation occurs on the upper surface of the Al electrodes and leads to the formation of Al2O3. The break in the Al electrode stripe is observed.

Total Dose ionizing radiation response of substrate PNP transistors have been investigated as functions of biases and dose rates. The experiment result shown that emitter-base junction bias dominates dose rate effects in the SPNP transistors. By considering of radiation induced interface traps and oxide trapped positive charges, the degradation mechanisms have been discussed based on space charge model. In addition, the worst case biases in the SPNP transistor with different dose rates are also discussed in this paper.

This paper proposed a physical model for reverse subthreshold currents in the amorphous silicon thin film transistors. Firstly, an approximation for the band bending in the back interface as a function of gate-source voltage is derived. By considering of deep states, a current model based on electron conduction in the back channel is then developed. Finally, the proposed model was verified using the experimental data.

The failure rate for NMOS devices is modelled by sum-of-failure-rate, i.e., the one for HCI mechanism and the one for TDDB failure mechanism. The least squares method is used to estimate the unknown parameters in HCI failure rate model and TDDB failure rate model, respectively. The hypothesis tests show that the regression model for HCI (TDDB) has good fitness and high significance. These results are verified by a numerical example.

A prognostic circuit for electromigration failure of integrated circuit was proposed, and it was simulated on the base of the SMIC 0.18 um mixed-signal CMOS process model. The prognostic circuit is composed of stress and detection module, two-stage comparator, offset voltage cancellation module, non-overlapping clock generation module, and output module. When the increase amount of resistance for interconnect line exceeds a preset value due to electromigration, the output of the prognostic circuit designed to fail faster will jump from low voltage to high voltage. It indicates the impending failure of hosted circuit because of that the prognostic circuit experiences the same manufacturing process and operational environment as the hosted circuit. The research results are useful for the prediction of performance degradation and failure of integrated circuit.

This paper investigates the total dose effects of substrate PNP transistors through experiments. By considering of oxide trapped positive charges and interface traps, the radiation induced excess base current in the irradiated SPNP is simulated. The simulation results showed similar trends with the experimental results, thus the mechanisms of total dose effects in the SPNP transistors are verified.

Traveling wave tube (TWT) is a type of microwave vacuum electronic component. TWT often works under harsh mechanical environment stress, such as vibration, shock. The stress leads to the open circuit of filament in heater, which results in the change of inner structure and electric performances, even failure. This paper introduced a failure case of TWT in use. Failure mode and failure mechanism of filament in heater of a typical TWT was analyzed in this paper.

Ionization radiation causes ESD protection structure of integrated circuit degradation. A new method using Transmission Line Pulse (TLP) test is introduced in this article; this method gives more detailed information of the ESD protection structure's degradation. Turn-on voltage, hold voltage, turn-on resistance of two type ESD protection structures are measured before and after TID radiation test, results are discussed.

An investigation of thermal effects in a high power 3-5μm solid state laser pumped with different pump beam transverse profiles is carried out by COMSOL software based on the finite element method, and the temperature of the crystal center where the Super-Gaussian distributed light projected area is 81.8°C, and is bigger than that of Gaussian pump light mode and top plane pump light mode.