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This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time. Index Terms--BSIM3v3, high-frequency (HF) noise model, HF noise modeling, RF MOSFET, RFCMOS, Verilog-A.

A novel on-chip transformer configuration that gives an identical inductor pair, a higher individual coil self-resonant frequency (SRF), and excellent area efficiency are presented. This technique involves the unique way of inter-crossing the transformer's primary and secondary coils using multiple metallization layers. Truly symmetrical transformer configuration (100%) is demonstrated using minimum die size. Thus, a true 1:1 transformer has been realized on silicon. The effects of the parasitic within the transformer are represented by an equivalent-circuit model. Accurate semiempirical expressions describing the circuit components are provided based on the various layout parameters. Of all the transformer structures presented, the two designs occupying the minimum silicon area by a factor of > 2x have been selected for performance evaluation of the SRF, coupling coefficient, input impedance, quality factor, and inductance. The transmission line transformer mode has also been studied to examine the designs' performance in the differential mode. The second proposed design reported in this paper, with enhancements in $21 and k performance, is created by adding a unique routing technique onto the first proposed structure. The method presented is fully compatible with the standard foundry CMOS processes. The silicon data reported in this study are based on Chartered Semiconductor Manufacturing's 0.13-[micro]m RF CMOS technology node. Index Terms--Area efficiency, coupling coefficient, differential inductor, fully symmetrical transformer, identical inductor pair, inter-coil crossing, interleaved transformer, multidirectional coupling, RF CMOS, self-resonant frequency (SRF), stacked transformer, system-on-chip (SoC), transmission line transformer (TLT).

This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-[micro]m CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively. Index Terms--Analog-to-digital converters (ADCs), digital receiver, high-speed, operational amplifier (opamp), pipelined ADCs, sample-and-hold (S/H).

This paper presents two fully integrated CMOS transmit/receive (T/R) switches with improved body-floating operations. The first design exploits an improved transistor layout with asymmetric drain-source region, which reduces the drain-source feed-through for body-floated RF switches. In the second design, a switched body-floating technique is proposed, which reconfigures the body-floating condition of a switch transistor in the ON and OFF states. Both designs are fabricated in a standard 0.13-[micro]m triple-well CMOS process. With regard to 2-dB insertion loss, the switch with asymmetric drain-source achieves 28-GHz bandwidth, which is among the highest reported frequencies for CMOS T/R switches. The bandwidth of the switched body-floating design is 16.6 GHz. There is approximately 5 dB better isolation obtained in the switched body-floating design. With the resistive double-well body-floating technique, 26.5- and 25.5-dBm input 1-dB compression point ([P.sub.1dB]) are obtained, respectively. Both designs consume only 150 [micro]m x 100 [micro]m die area. The demonstrated T/R switches are suitable for high-frequency and wideband transceivers. Index Terms--Asymmetric drain-source, CMOS integrated circuits, MOSFET switches, RF switches, switched body floating, transmit/receive (T/R) switches, triple well.

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-[micro]m RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an [S.sub.11] of -19 dB while using 630 [micro]A of dc current. The measured noise figure is 5.2 dB. Index Terms--Front-end, low-noise amplifier (LNA), low power, subthreshold.

In this paper, we demonstrate a unit width ([W.sub.f]) optimization technique based on their unity short-circuit current gain frequency ([f.sub.T]), unilateral power gain frequency ([f.sub.MAX]), and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the [W.sub.f] change is different; hence, some tradeoff is required to obtain the optimum [W.sub.f] value. During the HF noise analysis, a new FOM is proposed to study the [W.sub.f] effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in [W.sub.f] does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum [W.sub.f] for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum [W.sub.f] for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies. Index Terms--Flicker noise, high-frequency (HF) noise, layout, optimization, RF, RFCMOS, unilateral power gain frequency, unity short-circuit current gain frequency.

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butter-worth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-[micro]m 1.8-V RF CMOS technology. Measurement data shows a -3-dB band-width of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dB[OMEGA] with a group delay of 80 [+ or -] 20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/[square root of (Hz)] up to 10 GHz. Index Terms--Bandwidth enhancement, broad-band, matching network, regulated cascode (RGC), transimpedance amplifier (TIA).

This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters characterizing the coupled interconnects have been examined. The influence of the process parameters on transmission, reflection, near-end, and far-end crosstalk capacities of the coupled interconnects are discussed. Index Terms--CMOS process, coupled interconnects, sensitivity.

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25 % reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-[micro]m CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications. Index Terms--CMOS integrated circuit, D flip-flop (DFF), frequency divider, frequency synthesizer, high-speed digital circuit, phase-locked loops (PLLs), true single-phase clock (TSPC).

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-[micro]m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7 [+ or -] 0.8 dB power gain with a good input match (S11 < -9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets. Index Terms--Common gate, low-noise amplifier (LNA), RFCMOS, ultra-wideband (UWB), variable gain.

This paper presents the characteristics of a miniaturized microstrip filter, which has two separate coupling paths: electric coupling path and magnetic coupling path between two resonators. Either magnetic coupling or electric coupling in two paths can be dominant in the total coupling coefficient of the inter-stage resonators with the similar configuration, but different positions of transmission zero points (ZPs). Based on the proposed filter topology, second- and fourth-order filters have been designed and fabricated for the first time. Advantages of using this type of filter are not only its low insertion loss and much more compact size, but also its controllable transmission ZPs. Index Terms--Bandpass filter (BPF), odd and even mode, separate electric and magnetic coupling paths (SEMCPs), zero point (ZP).

A new figure of merit, intrinsic factor for interconnects, is proposed to provide insights as to how back-end metallization influences the performance of radio frequency integrated circuits. An accurate and scalable double-[pi] radio frequency interconnect model, continuous across physical dimensions of width and length, is presented to demonstrate reliable predictions of interconnect characteristics up to 10 GHz. Using this interconnect model in gigahertz amplifier and voltage-controlled oscillator circuit simulations yields excellent correlations between simulated and on-wafer measured circuit results. Index Terms--Inductance, interconnects, intrinsic factor, metallization, parasitics, quality factor, radio frequency (RF), series resistance, skin effects, SPICE models, substrate loss.

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects. Index Terms--MIM capacitor, MOS varactor and interconnect, process monitoring, RFCMOS, scribe line.

A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18-[micro]m CMOS technology. The complementary cross-coupled differential topology is adopted in the design. The measured phase-noise is around -89 dBc/Hz at the offset frequency of 100 kHz from the center frequency of 9.83 GHz, the output frequency tuning range of the fabricated VCO is 1.1 GHz ranging from 9.3 to 10.4 GHz, and the power consumption of the core VCO circuit is 5.8 mW. The design is the first one that adopts the complementary cross-coupled circuit structure for 10-GHz-band oscillators, and whose performances of the VCO are the best ones for 10-GHz-band oscillators, compared with the 10-GHz-band CMOS oscillators reported earlier. Index Terms--Complementary cross-coupled differential topology, LC tank voltage-controlled oscillator (VCO), linear time variant (LTV), lower phase noise, lower power consumption, RF integrated circuit (RFIC), wide tuning range, 0.18-[micro]m CMOS technology.

Abstract--The impacts of metallization proximity for copper spiral inductors on silicon have been investigated in this paper. Performance of the spiral inductor versus area consumption tradeoff with respect to its core diameter is evaluated quantitatively for the first time. Effects of the inductor's proximate grounded metallization on its overall inductive performance are also analyzed. Index Terms--Core diameter, eddy-current and series resistance, inductance, quality factor, spiral inductor.

Scaled LDD pMOSFETS operating in the Bi-MOS hybrid-mode were studied to determine effective channel length and external series resistance.