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State-of-the-art SRAM FPGAs (Field Programmable Gate Arrays) are being increasingly considered for use in space applications, due to their reprogrammability and many dedicated resources that implement many common tasks at high speeds. However, the programmable fabric and resources are susceptible to ionizing radiation common in space, causing the device to fail. The radiation effects of all the components need to be known in order to develop effective mitigation techniques. This information, however, is difficult to obtain through typical broadbeam ion testing, due to low observability rates of the components. This paper present the results of a study to use a laser to study the radiation effects on a FPGA. Specifically, three studies were conducted to show the necessity of laser calibration as well as a case study using this calibration to test a specific component on the FPGA. This calibration technique will be used in the future to test many more components on the FPGA.

Scrubbing is a process in which a memory is systematically read, checked for errors, and corrected when an error is found. Scrubbing is used as a form of mitigation against data corruption that may be induced by internal or external stimuli. Radiation is an example of an external stimulus which can corrupt data values in semiconductor devices. Some environments, such as space, have high levels of radiation. When using semiconductor devices in a high radiation environment scrubbing can be used to help mitigate the effects the radiation has on the circuitry. The development of two FPGA configuration scrubbing architectures are discussed. The limitations of the first system are presented and a second system designed to resolve these issues is presented. A configuration scrubbing system suitable for space flight is also presented.

FPGA use in space-based applications is becoming more common. Radiation-hardened (rad-hard) memories are typically used to store configuration data for programming the FPGA and performing bitstream scrubbing to remove errors in the system that occur from single event upsets (SEUs). Since device densities for the latest FPGAs are growing at a faster rate than rad-hard memories, it is becoming more difficult to reliably store the FPGA configuration data without using a large number of memories. We present a method for cutting the use of rad-hard memories necessary to support the use of the latest FPGA technologies in space-based applications. This paper describes a solution to this memory problem which utilizes FPGA partial reconfiguration, with device self-scrubbing, and bitstream compression to create a minimally sized bootstrap design that has a memory footprint that is a fraction of the size of the original design. This bootstrap design is stored locally, and the remaining design elements can be reconfigured as necessary from a remote location. The resulting prototype design yields a compressed bitstream that at less than 2% the size of the bitstream for largest FPGA currently on the market.

This paper demonstrates the ability to reuse arbitrary IP as primitive cores in architectural synthesis algorithms for FPGA by encapsulating these IP in meta-data. This metadata is represented as a set of extensions to the IP-XACT XML specification and defines the high-level data types and the temporal behavior of IP. This paper describes how these extensions are used in the Ogre synthesis system to facilitate automatic synthesis of control and interface logic for homogeneous synchronous dataflow (H-SDF) designs.

This paper demonstrates improvements in design productivity for reconfigurable computing which are accomplished through a novel IP reuse strategy. It presents a set of extensions to the IP-XACT XML specification that define the temporal behavior of cores and describes how these extensions are used in the Ogre synthesis system to simplify design complexity and thereby reduce design time. Design productivity improvement is demonstrated by reducing design time for software radio designs from days to hours.

The Cibola Flight Experiment (CFE) is an experimental small satellite carrying a reconfigurable processing instrument developed at the Los Alamos National Laboratory that demonstrates the feasibility of using FPGA-based high-performance computing for sensor processing in the space environment. The CFE satellite was launched on March 8, 2007 in low-earth orbit and has operated extremely well since its deployment. The nine Xilinx Virtex FPGAs used in the payload have been used for several high-throughput sensor processing applications and for single-event upset (SEU) monitoring and mitigation. This paper will describe the CFE system and summarize its operational results. In addition, this paper will describe the results from several SEU detection circuits that were performed on the spacecraft.

Triple Modular Redundancy (TMR) is a common reliability technique for FPGA designs used in radiation environments. TMR consists of triplicating a design and inserting voters to mask errors using redundancy. This paper will investigate the automatic placement of voters in TMR designs. In particular, it will introduce three algorithms for determining where to insert synchronization voters and compare the area and timing impact of these algorithms on FPGA designs. It will be shown that the placement of synchronization voters in a triplicated design can have an important impact on the area and timing characteristics of the resulting design. The algorithms presented in this paper give results that increase the critical path length of a design when adding TMR voters by as little as 3% to as much as 50%.

The flexibility combined with the computational capabilities of FPGAs make them a very attractive solution for space-based computing platforms. However, SRAM-based FPGAs are susceptible to radiation effects, including Single Event Upsets. In order to increase the fault tolerance of FPGA designs, fault mitigation techniques, such as Triple Module Redundancy, can be applied. Such techniques, however, can be excessive in terms of hardware costs. This work investigates the tradeoffs between fault mitigation techniques for FPGA designs and the corresponding costs of such mitigation. A particular focus is placed upon identifying design components that serve to benefit most from the application of fault tolerance techniques, and investigating the tradeoffs associated with applying mitigation to these most sensitive design sections.