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An experimental study of forced convection in impinging flow, using fluorocarbon FX3250 and a simulated electronic chip, was performed. A test section consisting of a 35 mm long, 1 mm wide slot nozzle in a 2 mm thick plate offset 2 mm from the heat source was used. The simulated chip array consisted of five foil strip (4 mm wide) heaters, positioned with the center strip directly beneath the slot nozzle. The velocity of the coolant was varied from 0.53 to 5 m/s, and the subcooling in the range from 2 to 21 K. The experiments were conducted focusing on two cases. First, only the center strip was heated. Second, all the heaters were energized, and the strip-by-strip variations of heat transfer were measured. The critical heat flux (CHF) on the center strip, determined by sensing the onset of oscillations and subsequent rapid rise of foil temperatures, was found considerably lower than those predicted by the existing correlations. It is pointed out that the thermal mass of the test heater could be an important factor for the CHF. The heat transfer behavior of other strips showed channel-flow or jet-impingement mode depending on the strip location and the coolant flow rate. [S1043-7398(00)00202-4]

This report presents a study of microfabricated enhanced structures for enhancing the thermal performance of a two-phase thermosyphon loop. The structures used in this study have an array of channels and pores that make it highly porous. The structures were fabricated in silicon using wafer dicing, wet-chemical etching, and laser milling, and details are included in this report. The structures were employed inside the evaporator section of a thermosyphon loop for enhancing the boiling performance. Preliminary results show that the heat dissipation with these structures is at least three times better than that of a plain polished silicon surface, at a wall superheat of 30 degrees C. The results also indicate that increasing the channel width resulted in better thermal performance.

Heat transfer engineering is an indispensable discipline among those that support the rapid progress of electronics technology. Through applications to cooling design, the basic knowledge and the methodology of heat transfer engineering have contributed to the evolution of high-performance and reliable electronic equipment. The relationship between the technology and its building block disciplines, however, is not unilateral. Demands for higher performance and more diverse functions on electronic equipment have stimulated the growth of new research topics and methodologies of heat transfer engineering.

The study of optimization of finned heat sinks for impingement cooling of electronic components was undertaken. The procedure was based on a semiempirical zonal approach to the determination of thermal resistance as well as pressure drop. To test the validity of the model’s predictions, experiments and CFD (computational fluid dynamics) simulations were performed. The results provided support for the approach. The model enables cost-effective design calculations to be performed for the optimization of heat sinks. We performed such calculations to optimize an LSI heat sink in consideration of sixteen design parameters, including fin thickness, fin spacing, fin height, and flow-orifice dimensions. For the particular application considered in our study, the optimum fin thickness was found to be 0.15 mm. The characteristics and limitations of air cooling for such applications were investigated under various conditions.

Natural convection immersion cooling of two heat sources in a series of parallel interacting cavities filled with FC-72 has been numerically studied. Both low thermal conductivity (i.e. bakelite) and high thermal conductivity substrates (i.e. alumina-ceramic) have been considered. Comparison has been made between single and double heat source configurations. Non-dimensional temperatures and Nusselt numbers of the heat sources have been correlated as a function of the Rayleigh number.

We analyzed the seismic waves of the 1994 Sanriku-Haruka-Oki earthquake (Mw = 7.7), which occurred in the aftershock area of the 1968 Tokachi-Oki earthquake (Mw = 8.2). Applying a multiple-time window inversion scheme to near-source strong-motion data, we obtained a detailed spatiotemporal rupture process and compared it with that of the Tokachi-Oki earthquake. The fault geometry is constructed based on the aftershock distribution. The obtained rupture model is consistent with the CMT solution even for a non-double-couple component. The total seismic moment is 4.0 × 1020 N-m. Large slips are concentrated in three asperities: the first asperity centers about 40 km south and 50 km west from the hypocenter with a maximum slip of 4.4 m, the second one centers about 60 km west from the hypocenter with a maximum slip of 2.2 m, and the third one lies about 110 km west from the hypocenter with a maximum slip of 2.6 m. The obtained moment rate and the duration on the first and second asperities are lower and much longer than those on the third asperity, respectively. The first asperity does not overlap with an area of large slip during the Tokachi-Oki earthquake, but the second or third seem to overlap with or be adjacent to the asperity of the Tokachi-Oki earthquake. Our inversion result also shows an abrupt change of the rupture velocity (from 1.8 to 3.0 km/sec) at the central part of the fault plane. A difference of the seismic coupling between the oceanic and the continental lithospheres at the trenchward side and at the landward side of the 143° E meridian seems to affect the rupture process of this earthquake.

Since the advent of modern electronics technology, heat transfer science and engineering has served in the development of computer technology. The computer as an object of heat transfer research has a unique aspect; it undergoes morphological transitions and diversifications in step with the progress of microelectronics technology. Evolution of computer's hardware manifests itself in increasing packing density of electronic circuits, modularization of circuit assemblies, and increasing hierarchical levels of system internal structures. These features are produced by the confluence of various factors; the primary factors are the pursuit of ever higher processing performance, less spatial occupancy, and higher energy utilization efficiency. The cost constraint on manufacturing also plays a crucial role in the evolution of computer's hardware. Besides, the drive to make computers ubiquitous parts of our society generates diverse computational devices. Concomitant developments in heat generation density and heat transfer paths pose fresh challenges to thermal management. In an introductory part of the paper, I recollect our experiences in the mainframe computers of the 1980s, where the system's morphological transition allowed the adoption of water cooling. Then, generic interpretations of the hardware evolution are attempted, which include recapturing the past experience. Projection of the evolutionary trend points to shrinking space for coolant flow, the process commonly in progress in all classes of computers today. The demand for compact packaging will rise to an extreme level in supercomputers, and present the need to refocus our research on microchannel cooling. Increasing complexity of coolant flow paths in small equipment poses a challenge to a user of computational fluid dynamics (CFD) simulation code. In highly integrated circuits the paths of electric current and heat become coupled, and coupled paths make the electrical/thermal codesign an extremely challenging task. These issues are illustrated using the examples of a consumer product, a printed circuit board (PCB), and a many-core processor chip.

Heat conduction analysis is performed on a model system to survey the effects of geometric and thermal parameters on the temperature of an embedded heat source. A box model has the geometric characteristics of hand-held devices and has a laminar organization composed of a printed circuit board (PCB), air gap, and a system casing. Exploiting the laminar organization and thinness of the laminate an approximate solution is derived. The solution is used to produce a guide for thermal design analysts, which is concerned with the sensitivity of the heat source temperature to the effective thermal conductivity of the PCB. Numerical examples are shown for the models that have typical dimensions and material properties of actual equipment and PCB.

A system of temperature calculations is developed to study the conditions leading to hot spot occurrence on multicore processor chips. The analysis is performed on a physical model which incorporates certain salient features of multicore processor. The model has active and background cells laid out in a checkered pattern, and the pattern repeats itself in fine grain active cells. The die has a buried dioxide and a wiring layer stacked on the die body, and heat sources are placed at the wiring layer/buried oxide interface. With this model we explore the effects of various parameters on the target spot temperature. The parameters are the die dimensions, the materials' thermal conductivities, the effective heat transfer coefficients on the die surfaces, the power map, and the spatial resolution with which we view the power and temperature distributions on the die. Closed-form analytical solutions are derived and used to examine the roles of these parameters in creating hot spots. The present paper reports the details of mathematical formulations and steps of temperature calculation. The results for a particular example case are included to illustrate what can be learned from the calculations.

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

As electronic devices and equipment are finding their ways into diverse applications, their physical integrity becomes a matter of utmost concern. The thermal design criteria customarily assumed in many of previous heat transfer research programs have to be replaced by those on the thermomechanical load in compact systems. Attempts to find thermal and stress fields in critical parts of components, however, are beset by geometrical complexities and multiple length and time scales involved in transport processes in electronic equipment. Modeling of complex systems is the subject left for further rationalization. Also needed is the foresight about possible hardware morphologies taken by electronic equipment in the future. In view of possible saturation of 2D packaging technology, heat transfer studies for 3D packaging are worth being undertaken. Common to different scenarios of hardware development is the need to critically review the methodology and focuses of fundamental heat transfer research.

Conjugate heat transfer from a surface-mounted block (31 × 31 × 7 mm3) to forced convective air flow (1–7 m/s) in a parallel-plate channel was studied experimentally and analytically. Particular attention was directed to the heat flow from the block to the floor through the block support, which was eventually transferred to the air flow over the floor. The concepts of adiabatic wall temperature (Tad) and adiabatic heat transfer coefficient (had) were employed to account for the effect of thermal wake shed from the block on the heat transfer from the floor. The experimental data of Tad and had were used in setting the boundary condition for the numerical analysis of heat conduction in the floor. The accuracy of the numerical predictions of the thermal conductances for different heat flow paths was proven experimentally. The heat conduction analysis code was then used to find the heat transfer capability of various block-support/floor combinations.

It has been over fifteen years since this journal had an issue devoted to the subject of electronics cooling. In 1988, volume 9, issue 3 was published, containing nine papers in all: two papers rep...

This paper is one in a series of reports on the experimental and numerical study of heat transfer from a module mounted on the floor of a parallel-plate channel to forced convective air flow. In this study a numerical analysis is performed to predict conjugate heat transfer in paths from the module through the module support and the floor to the air flow. The effect of the thermal wake originating from the module on heat transfer from the floor surface is captured by the adiabatic wall temperature function. Also serving as the basis of the analysis is the local heat transfer coefficient obtained and reported in the previous report. The two-dimensional heat conduction analysis with convective boundary condition provides temperature distributions of the floor and macroscopic thermal conductance values for heat transfer through the floor. The predictions are compared with the experimental data, and their good agreement is confirmed.

This paper is one of the serial reports on an experimental study of heat transfer from a simulated module (31×31×7 mm3) mounted on the floor of a parallel-plate channel (20 mm high, 320 mm wide, and 650 mm long) to forced convective air flow (1-7m/s). In this report, particular attention is directed to the heat transfer from the floor which is under fluid mechanical and thermal influences of the module. Two combinations of the module and the floor are employed : a heated module on an adiabatic floor (HM/AF) and an adiabatic module on a heated floor (AM/HF). Liquid-crystal thermography is used to determine the adiabatic floor temperature (Tad) on the HM/AF floor, and the heat transfer coefficient based on the difference between the surface temperature and Tad on the AM/HF floor. Additional information is obtained through measurements of velocity and temperature of air in the channel. Plots of Tad and hw show marked effects of flow development from the module and dispersion of thermal wake near the module. The distributions of air temperature and velocity defect from the undisturbed channel flow velocity show similar features to those of Tad-isotherms.

Recently, liquid bridge heat switch has been suggested as effective thermal management solutions for the various thermal problems. The liquid bridge heat switch can control the thermal resistance and the temperature of desired position by regulating the liquid bridge between objective areas. The liquid bridge heat switch system is composed of hot plate as an upper plate, cold plate as a lower plate, and actuators. “On” state demand, the supplied liquid generates liquid bridge between two plates and conducts heat from hot plate to cold plate. The amount of conducting heat and thermal resistance are controlled by the diameter and height of generated liquid bridge. To be an “Off” state, the generated liquid bridge is retrieved and ruptured eventually. At that time, the heat switch system has maximum thermal resistance. This result decreased conduction of heat. In order to realize the desired switch operation, the precise liquid bridge control is required. In this research, the liquid bridge behavior was studied to design the heat switch system. The effects of channel geometry and clearance on the liquid bridge behavior were verified and the liquid bridge rupture conditions were found out. Based on the investigation, the liquid bridge heat switch system was designed for the high power LED cooling system. In a series of experiment, the stable liquid bridge operation was achieved by designed channel geometry. The results also showed that proposed heat switch system was able to decrease the LED junction temperature and regulate the thermal resistance between hot and cold plate.

An experimental study was performed to investigate the local characteristics of heat transfer from vertical simulated micro-chips to impinging submerged circular water jets. The effects of jet velocity, and nozzle-to-plate spacing were studied in the range of Re = 5.0 × 103 ˜ 3.6 × 104. Heat transfer rates at the stagnation point and local heat transfer distributions were correlated. Transition from laminar to turbulent flow was observed.

The accurate prediction of operating temperatures of temperature sensitive electronic parts at the component, package, board, and system level CFD simulations has engaged the engineering community for a number of years. The primary challenge has been that near-exact physical models of such components (known as detailed thermal models, or DTMs) are difficult or implement directly in system designs due toe the wide disparity in length scales involved, which results in large computational inefficiencies. A compact thermal model (CTM) attempts to solve this problem by taking a detailed model and extracting an abstracted, far less grid intensive representation that is still able to preserve accuracy in predicting the temperatures at key points in the package, such as the junction. In this paper, we present a compact thermal network model to represent the multi dimensional heat flow system as a network based on the thermal interface material (TIM) measurement apparatus. In order to estimate the heat flow division on each heat transfer path, thermal impedance and temperature difference between junction node and adjacent node are used. This model also can be extended to estimate the thermal interface resistance in joints and heat transfer coefficient variation of the multidimensional heat flow system.

The high-density interconnection substrate invariably poses enormous difficulty to thermal design analysts due to complex metal layout patterns embedded in the dielectric matrix. A modeling method is proposed, which produces effective thermal conductivity values for elements of the substrate under a specified boundary condition.

In recent years, thermal design of electrical equipment becomes importance and fast thermal design is required due to the fast development of electrical devices. We have proposed the flow and thermal resistance network analysis (coupled network analysis) as a fast thermal design method for electrical equipment. In this paper, we described analytical accuracy of the coupled network analysis of thin electronic equipment including the finned heat sink. We especially focused on the prediction of thermal performance on heatsink by using the coupled network analysis. For considering the accuracy of the coupled network analysis, we compared the results of the coupled network analysis with those of CFD analysis and the experiment. The results showed that the coupled network analysis can predict accurate thermal performance of heat sink and moreover accurate temperature distribution of electrical equipment.Copyright © 2010 by ASME

Various types of heat switch have been suggested as the promising solution of thermal management in the extremely low temperature condition. Recently, the heat switch based on the liquid for the room temperature condition has been investigated to control the thermal resistance of the electronic devices. The presented heat switch was composed of several micro channels. The key technology of the heat switch operation for room temperature is the fluid control. The existing studied indicates that the flow regulation was achieved by simple channel geometry design based on the burst pressure theory. In this research, the design of the liquid bridge heat switch was presented and the pressure characterization of the designed switch was carried out. The supplying liquid generates the liquid bridge between two plates. The thermal resistance between two plates depends on the liquid bridge diameter and height. The liquid bridge size control is achieved based on the pressure characterization.

Numerical simulation was conducted to study the thermal history of Czochralski growth of large silicon single crystals. The computations were performed for various crystal diameters and emissivities of the crucible inner wall. The analysis gives the change of temperature distribution in the crystal and the shape of the solid-melt interface. The computed results show the importance of the effects of radiation from the crucible inner wall and the melt free surface on crystal growth. Also, increasing crystal diameter decreases the pull speed and increases the concavity of the solid-melt interface into the crystal. The result of this analysis is in good agreement with measurement of the pull rate on production apparatus, and the shape of the crystal-melt interface showed a tendency to qualitatively agree with the observations of X-ray diffraction.

The Japanese industry has developed power electronics for railway trains, and now works to extend its experience to automobiles. The former part of the paper outlines the thermal issues pertinent to automobile applications as compared to railway applications. The discussion is developed for IGBT power modules and batteries. The latter part of the paper reviews the tools of thermal design analysis. A challenge to thermal design analysts is how to devise appropriate models of complex structures and thermal environment inside vehicles.

The issue addressed in the present study is how to model wiring substrates to perform heat conduction analysis on moderate computational resource. Equivalent thermal conductivity is a convenient measure in thermal modeling. However, its notion needs re-examination where higher accuracy of heat conduction analysis is pursued. Proposed is a scheme where the indexed volumetric metal contents are used to estimate the equivalent conductivity of representative volume element (RVE). The index is designed to reflect the effect of metal pattern on heat flow through RVE. In order to illustrate the core concept we report the analysis performed on template models of high-density interconnect (HDI) substrates. The element of HDI contains copper in several forms; through-via, continuous plane, and cross wires. Five heat flow directions are assumed; two are linear and three are right-angled turn. From combinations of the metal pattern and the heat flow direction twenty five templates are created, then, they are subjected to detailed numerical analysis. The values of equivalent thermal conductivity derived from the numerical solutions reveal that the gross volumetric metal content is totally inadequate as a parameter of thermal characterization. The paper also outlines the overall organization of our analysis system which is being developed in an industry-academia cooperative effort under the auspices of JSME.Copyright © 2009 by ASME

This paper presents the heat switch for electronic package to be operated at room temperature. The heat switch controls the thermal resistance between two objective plates using liquid pillar. By forming the liquid pillar, the temperature of the specific area can be controlled locally. In order to realize the desired switch operation, the heat switch should be provided with reservoir, switching channel and breathing channel. The channels are carefully designed to control the liquid pillar precisely. The liquid pillar formation depends on the liquid contact angle. The designed channel geometry can generate hydrophobic surface by using suddenly diverging shape like as capillary stop valve. Thus, the liquid pillar can be created at desired point with high stability. To verify the switch operation, the switch panel was designed and experiments were performed on a designed switch for the liquid pillar control and the heat flow regulation. The experiments show that the heat switch is able to work properly. Also, the temperature distribution and thermal resistance was changed in accordance with channel state as desired. As a result, the heat switch can be a good candidate of thermal management in the commercial electronics packages.Copyright © 2009 by ASME

A methodology for modeling and simulating the electrothermal behavior of an enclosed electronic package is presented and validated. The electro-thermal model is constructed using system dynamics. The system model, in which the electrical and the thermal domain are combined, is presented. The developed model describes the dynamic thermal behavior system that was an electronic device in the test enclosure. An effective way to identify the thermal parameters of the system, especially the thermal contact resistance, is suggested. Based on the proposed model, either the variation of the heat source or the ambient temperature can be estimated. Simulated results were in good agreement with the measured temperature in the transient state accompanying with the variation of the environment.Copyright © 2009 by ASME

An analytical model is developed to estimate the heat transfer performance of printed circuit board (PCBs). The PCB under study is the substrate for a ball-grid-array (BGA) package. Under the BGA, the PCB has a belt of densely populated through-vias that penetrate the laminate of horizontal copper and resin; outside the BGA-covered area the board is a copper/resin laminate and its surfaces are exposed to cooling air. Calculations are performed on a sample board having the dimensions 11×11 cm2 (footprint)×1.26 mm (thickness). The model of the board has two internal layers of continuous copper (0.03 mm thick) and through-vias under a 4.4×4.4 cm2 BGA package. The impacts of board design parameters on the temperature and the heat flow are presented; the parameters are the width of the insulation gap around the via, the area of copper coverage at the via bottom, and the population of vias.

The thermal switch is limited at the temperature range and the local heat transfer control due to their structures. This paper presents the development of a thermal switch for heat regulation based on the liquid column control using channel geometry effect. The most dominant factor of liquid column control is the contact angle of liquid. Therefore, the geometry of each channel was designed to affect contact angle of working fluid. Experiments were performed on a switch for the switching operation and the thermal resistance. The result shows the liquid column thermal switch can be used at the room temperature. And the heat transfer can be controlled by on/off state of the thermal switch channels.Copyright © 2008 by ASME

The object of the present study is a simulated heat spreader panel (80 × 100 × 0.8 mm3) which carries five distributed heat sources and a finned heat sink near one of its corners. The panel thickness is designed to minimize temperature variation over the heat sources. The panel and the wrapping insulation possess geometric and thermal characteristics commonly found in thin electronic products. Thin configuration increases the sensitivity of internal temperature to the variation of external thermal environment; that is, a significant level of uncertainties should be expected in the thermal design of such systems. The present study aims at the development of a methodology for thermal analysis of such thin systems. Uncertainties in the thermal environment demand the coverage of a wide range of relevant parameters by the analysis, and computations can be performed most efficiently with a thermal network model. To achieve the stated goal we performed CFD simulations and the experiments, and reduced the results into a thermal network model.Copyright © 2008 by ASME

This paper reports the design study performed on a heat conduction panel having several heat sources at separate locations and a heat sink on one of the panel corners. The panel is given a thickness distribution so as to provide spatially varying heat conduction paths from the heat sources to the heat sink. The objective of thickness distribution design is to reduce the variation among heat source temperatures and the maximum heat source temperature simultaneously. The genetic algorithm is used to search for an optimum thickness distribution. The problem is a generic representation of the situations that are becoming common in a compact electronic equipment.

Addressed in the present study is the required accuracy in assuming equivalent thermal conductivities of printed circuit boards (PCBs) in the thermal analysis of electronic equipment. The required accuracy depends on the morphology of PCB and the thermal boundary condition. Out of various PCB morphologies two are considered as representatives in the extreme ends of PCB size and thermal conditions; one is a JEDEC test board having a large convection-cooled area, and the other is a small board in contact with a large solid thermal mass. The major focus of the present paper is on the case of a JEDEC test board measuring 11 cm × 11 cm and carrying a ball grid array package (4 cm square). Geometric complexity in the through-via zone under the package needs to be reduced by suitable modeling in order to simplify the analysis. In exploring modeling strategies the analyses were performed on three models. Level-one model includes the details of through-vias, and the computation is resource intensive. Level-two model is composed of two orthotropic media having pairs of different equivalent thermal conductivities, one corresponding to the via zone and the other to the rest. Level-three model is a thermal resistance network model derived from numerical/analytical composite analysis. Comparison of the results on the three models proves that the accuracy of temperature prediction is in general insensitive to the equivalent thermal conductivity values due to the dominant role of surface heat transfer on the temperature level of PCB.

The PCB in high density packaging environment often provides a critical heat conduction path from the package to the electrical connectors or the system enclosure that serves as a solid heat sink at the edge of the PCB. Where convective heat transfer on the PCB surface is negligible, heat flow is almost unidirectional from the area under the package footprint to the solid heat sink. However, the heat conduction analysis requires a large computational resource, if the full details of PCB’s internal organization are taken into account. To perform the board and system level thermal analysis with available computational resources, it is imperative to replace the actual PCB’s internal structure by a simplified model. In the most popular modeling the PCB is replaced by a medium having orthotropic thermal conductivities. The assumption of equivalent thermal conductivities, however, is not a straightforward practice, as illustrated by the present study. Two samples are subject to heat conduction analysis; they are rectangular bar specimens cut out from the PCB, one measuring 6mm (L) × 0.5mm (W) × 1.27mm (HPCB), and the other 12.35mm (L) × 1.27mm (W) × 1.27mm (HPCB). The specimen contains two layers of continuous copper, and one row of through-vias in the zone under the package footprint. Numerical solutions are obtained taking into account the full details of the via zone structures. Classical solutions are also obtained for a two-zone continuum model having different sets of orthotropic thermal conductivities for the via zone and the remaining zone. The thermal conductivities in the continuum model are varied to bring the key temperatures to those obtained by the numerical analysis. Presented in this paper is a methodology to estimate the equivalent thermal conductivities for a given set of dimensional data and thermal boundary condition.

In April 2002, Tohoku University, Sendai, Japan, started offering educational programs from the cross-department Internet School of Tohoku University (ISTU). Electronic packaging is one of the pillar subjects of ISTU. The present paper summarizes its curriculum of internet-based electronic packaging education. Following the overall description, the curriculum concerning thermal management of electronic equipment is explained in some detail. The ISTU program is still under development, and some challenges are foreseen. The most visible among them is the need to lower the cost of wide bandwidth communications. The future of internet schooling is discussed.Copyright © 2003 by ASME

Because of its rapid pace of developments and interdisciplinary nature the microelectronic packaging technology poses enormous challenges to educators and learners alike. The education in campus is only a starting point of long learning process that spans the entire professional career of engineers. For post-college education, we need some channels that facilitate continuous exchanges between industry engineers and academia. The present paper describes such channels that have been incorporated in the projects sponsored by the Japan Society of Mechanical Engineers and the Japanese government.Copyright © 2003 by ASME

Computational Fluid Dynamics (CFD) codes have proved their high potential as a tool of thermal design of electronic equipment. However, as the product development cycle is shortened, the CFD-based thermal design needs a new format that allows the packaging designer fast and versatile searches for better design options. The most serious factor that slows the CFD-based design is geometric complexity created by various components packed in a tight space of the system box. In a proposed methodology coined ‘Build-up Approach (BUA)’ CFD simulations are conducted in advance of the start of actual hardware design to develop a body of temperature distribution solutions for possible components placements in the system box. Two algorithms are introduced before and after CFD simulations. One defines the geometric parameters through singular value decomposition (SVD) of components placement patterns, and the other identifies important geometric parameters for thermal management through application of the Taguchi method. A case study was conducted on a simple hardware model (benchmark model) that embodies essential features of portable electronic equipment. The results proved the effectiveness of these algorithms in measuring the relative importance of geometric parameters, and weeding out unimportant geometric details contained in actual equipment.

Numerical analyses of manifold microchannel (MMC) heat sinks were performed. The MMC differs from a traditional microchannel heat sink in that the flow length is greatly reduced to a small fraction of the total length of the heat sink. Alternating inlet and outlet channels guide the coolant to and from the microchannels. A silicon heat sink cooled by fluorocarbon liquid was studied. The repetitive nature of the manifold and microchannels results in many planes of symmetry. The thermal and fluid characteristics of a MMC assembly can modeled by a "unit cell" bounded by the centerlines of the manifold inlet and outlet channels and by those of the microchannels and heat sink walls. A general-purpose finite volume CFD code was used. Three-dimensional finite element models of single manifold microchannels were constructed and used to simulate fluid flow and heat transfer. Conjugate analyses suggested that an isothermal model would produce suitably accurate results. In addition to coolant flow rate, channel length, width and depth were varied. Regions of high heat transfer were found near the inlet. At higher inlet velocities, secondary maxims in heat transfer were seen at the base of the microchannel below the inlet, and at the top of the microchannel near the exit. The flow was found to accelerate to a greater extent than predicted by rectangular duct analysis.

The study presents a model for the two-phase flow and heat transfer in the closed loop, two-phase thermosyphon (CLTPT) involving co-current natural circulation. Most available models deal with two-phase thermosyphons with counter-current circulation within a closed, vertical, wickless heat pipe. The present research focuses on CLTPTs for electronics cooling that face more complex two-phase flow patterns than the vertical heat pipes, due to closed loop geometry and smaller tube size. The present model is based on mass, momentum, and energy balances in the evaporator, rising tube, condenser, and the falling tube. The homogeneous two-phase flow model is used to evaluate the friction pressure drop of the two-phase flow imposed by the available gravitational head through the loop. The saturation temperature dictates both the chip temperature and the condenser heat rejection capacity. Thermodynamic constraints are applied to model the saturation temperature, which also depends upon the local heat transfer coefficient and the two-phase flow patterns inside the condenser. The boiling characteristics of the enhanced structure are used to predict the chip temperature. The model is compared with experimental data for dielectric working fluid PF-5060 and is in general agreement with the observed trends. The degradation of condensation heat transfer coefficient due to diminished vapor convective effects, and the presence of subcooled liquid in the condenser are expected to cause higher thermal resistance at low heat fluxes. The local condensation heat transfer coefficient is a major area of uncertainty.

This study investigates the issues involved in the design of compact two-phase thermosyphon systems for high power chip cooling. In such systems, the locations of the evaporator and condenser need to be given a high degree of freedom. The key components used in the experiment are: an evaporator enclosure (20 mm × 20 mm × 20 mm internal volume), a simulated chip (20 mm × 20 mm) with an enhancement structure (10 mm × 10 mm × 6.8 mm) and a cartridge heater embedded in a copper rod (11.9 mm × 11.9 mm cross-section). A dielectric coolant (PF-5060, boiling point 56 °C @ 1 atm) is used as the working fluid. Also included in the loop are a natural convection cooled condenser of dimensions 58 mm × 60 mm × 432 mm and connecting tubing. The relative height between the evaporator and the condenser, the tubing length, and the heat input were systematically varied. In this study, the heat flux ranged from 0 to 40 W/cm2; the pressure within the system ranged from −68.9 kPa to +34.5 kPa; and the relative height of the condenser over the evaporator ranged from 15 cm to 45 cm. These ranges represent actual conditions for electronics applications. Experimental studies show that these parameters affect the evaporator thermal resistance from the chip to the boiling pool, and the overall thermal resistance from the chip to the ambient air in a complex way. However, close examination of the data suggests that there could be an optimum point in the parametric domain.

The issues involved in the design of miniaturized systems are reviewed. In several respects the design of miniaturized systems requires departure from traditional engineering design. The design has to cope with a host of uncertainties simultaneously. The sources of uncertainties are all associated with reduced physical size of components and systems. A methodology is proposed in that the knowledge base is developed well in advance of actual design work, and a fast-to-use design code is made ready by the time the design work starts. For the knowledge base development conventional numerical simulation tools are applied to ‘template models’.