Search

Ultra-low-loss waveguide fabrication typically requires high-temperature annealing beyond 1000°C to reduce the hydrogen content in deposited dielectric films. However, realizing the full potential of an ultra-low loss will require the integration of active materials that cannot tolerate high temperature. Uniting ultra-low-loss waveguides with on-chip sources, modulators, and detectors will require a low-temperature, low-loss dielectric to serve as a passivation and spacer layers for complex fabrication processes. We report a 250°C deuterated silicon dioxide film for top cladding in ultra-low-loss waveguides. Using multiple techniques, we measure propagation loss below 12 dB/m for the entire 1200–1650 nm range and top-cladding material absorption below 1 dB/m in the S, C, and L bands.

A novel piezoelectric actuator is fabricated on a suspended silicon nitride ring resonator to tune the optical resonance via mechanical deformation. Fabricated devices exhibit tuning across a full free spectral range by applying 16 V across the piezoelectric.

A 3D integrated hybrid silicon photonic external cavity laser was realized experimentally. The laser was characterized for thermal performance and demonstrates promising characteristics for high-temperature and reliable operation.

A 3D integrated hybrid silicon photonic external cavity laser was realized experimentally. Continuous wave lasing was demonstrated with a side mode suppression ratio of 30 dB and optical output power up to 1.4 mW.

Typical integrated optical phase tuners alter the effective index. In this paper, we explore tuning by geometric deformation. We show that tuning efficiency, Vπ L, improves as the device size shrinks down to the optimal bend radius, contrary to conventional index-shift based approaches where Vπ L remains constant. We demonstrate that this approach is capable of ultra-low power tuning across a full FSR in a low-confinement silicon nitride based ring resonator of 580 μm radius. We demonstrate record performance with VFSR = 16 V, Vπ L = 3.6 V dB, Vπ Lα = 1.1 V dB, tuning current below 10 nA, and unattenuated tuning response up to 1 MHz. We also present optimized designs for high confinement silicon nitride and silicon based platforms with radius down to 80 μm and 45 μm, respectively, with performance well beyond current state-of-the-art. Applications include narrow-linewidth tunable diode lasers for spectroscopy and non-linear optics, optical phased array beamforming networks for RF antennas and LIDAR, and optical filters for WDM telecommunication links.

Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by selectively applying feed-forward reinforcement to circuits based on use of existing invariant relationships. As reinforcement mechanism, we used a modification of the standard CMOS gates based on the Schmitt trigger circuit. SPICE simulations show our solution offers better noise immunity than both standard CMOS and fully reinforced circuits, with limited area and power overhead.

Many-core chip architectures are now feasible, but the power consumption of electrical networks-on-chip does not scale well. Silicon photonic NoCs (PNoCs) are more scalable and power efficient, but floorplan optimization is challenging. Prior work optimizes PNoC floorplans through simultaneous place and route, but does not address cross-layer effects that span optical and electrical boundaries, chip thermal profiles, or effects of job scheduling policies. This paper proposes a more comprehensive, cross-layer optimization of the silicon PNoC and core cluster floorplan. Our simultaneous placement (locations of router groups and core clusters) and routing (waveguide layout) considers scheduling policy, thermal tuning, and heterogeneity in chip power profiles. The core of our optimizer is a mixed-integer linear programming formulation that minimizes NoC power, including (1) laser source power due to propagation, bend and crossing losses; (2) electrical and electrical-optical-electrical conversion power; and (3) thermal tuning power. Our experiments vary numbers of cores, optical data rate per wavelength, number of waveguides and other parameters to investigate scalability and tradeoffs through a large design space. We demonstrate how the optimal floorplan changes with cross-layer awareness: metrics of interest such as optimal waveguide length or thermal tuning power change significantly (up to 4X) based on power and utilization levels of cores, chip and cluster aspect ratio, and laser source sharing mechanism. Exploration of a large solution space is achieved with reasonable runtimes, and is perfectly parallelizable. Our optimizer thus affords designers with more accurate, cross-layer chip planning decision support to accelerate adoption of PNoC-based solutions.