51. SMPS electromagnetic noise in System-on-Chip: Resonant frequency and amplitude dependencies
- Author
-
Feltrin, Eric, Chesneau, David, Vollaire, Christian, Ampère, Publications, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), STMicroelectronics [Grenoble] (ST-GRENOBLE), and Ampère, Département Méthodes pour l'Ingénierie des Systèmes (MIS)
- Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power ,Hardware_INTEGRATEDCIRCUITS ,[SPI.NRJ] Engineering Sciences [physics]/Electric power - Abstract
International audience; Electromagnetic noise (EMI) is always difficult to estimate especially inside complex System-on-Chips (SoCs) where multiple noise sources and victims share the same silicon. However when a Switch-Mode Power Supply (SMPS) power stage is integrated in a SoC, switching noise becomes an issue of concern. The use of Technology Computer Aided Design solutions (TCAD) such as Finite Element Method (FEM) solver to model the emission and propagation of this noise has become highly time consuming in large SoCs. Consequently it is necessary to understand noise mechanism to reduce model complexity and to set up adapted solutions. The source analysis is based on a Spice model of a test vehicle in CMOS bulk technology with a TCAD model extracted from the package and the PCB layout. Each state of the power stage is studied separately to understand the link between parasitic components and the noise frequency spectrum. A similar approach is applied to the transition between these states in order to understand noise level dependency. Compared to measurements, the model gives a good and pertinent approximation of the noise key parameters leading to an understanding noise mechanism to design a safer power stage architecture.
- Published
- 2018