51. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers
- Author
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Riko I Made, Viet Cuong Nguyen, W. A. Sasangka, Jurgen Michel, Kwang Hong Lee, Chuan Seng Tan, Bing Wang, Eugene A. Fitzgerald, Cong Wang, Kenneth Eng Kian Lee, Soon Fatt Yoon, Yue Wang, Eldada, Louay A., Lee, El-Hang, He, Sailing, School of Electrical and Electronic Engineering, and SPIE OPTO
- Subjects
Materials science ,Silicon ,Wafer bonding ,chemistry.chemical_element ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Substrate (electronics) ,01 natural sciences ,law.invention ,Gallium arsenide ,chemistry.chemical_compound ,CMOS Integration ,Hardware_GENERAL ,law ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Wafer ,InGaP LED ,Diode ,010302 applied physics ,business.industry ,021001 nanoscience & nanotechnology ,CMOS ,chemistry ,Electrical and electronic engineering [Engineering] ,Optoelectronics ,0210 nano-technology ,business ,Light-emitting diode - Abstract
The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems. Published version
- Published
- 2017
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