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This letter presents a computing-in-memory (CIM) static random-access memory (SRAM) using efficient data processing and conversion circuits to enhance the throughput, energy, and area efficiency performance. The proposed unified charge-processing network simultaneously provides both signal processing and data conversion functions with maximum resource utilization, realizing significant performance improvements in energy and area efficiency by 37.5% and 15.4%, respectively. Measurement results from a prototype fabricated in a 28-nm CMOS technology show that the proposed CIM SRAM achieves a high throughput of 186.18 GOPS, with energy and area efficiencies of 41.87 TOPS/W and 3288.4 GOPS/mm2, which demonstrates the performance improvements of $2.26\times $ , $1.12\times $ , and $2.89\times $ , respectively, when compared with the state-of-the-art results. The proposed CIM SRAM can achieve 88.87% classification accuracy on the CIFAR-10 dataset.

This work presents a FloatSD8-based system on chip (SOC) for the inference as well as the training of a convolutional neural networks (CNNs). A novel number format (FloatSD8) is employed to reduce the computational complexity of the convolution circuit. By co-designing data representation and circuit, we demonstrate that the AISOC can achieve high convolution performance and optimal energy efficiency without sacrificing the quality of training. At its normal operating condition (200MHz), the AISOC prototype is capable of 0.69 TFLOPS peak performance and 1.625 TOPS/W in 28nm CMOS.

STUDY OBJECTIVES: Reliable sleep staging is difficult to obtain from home sleep testing for diagnosis of obstructive sleep apnea (OSA), especially when it is self-applied. Hence, the current study aimed to develop a single frontal electroencephalography-based automatic sleep staging system (ASSS). METHODS: The ASSS system was developed on a clinical dataset, with a high percentage of participants with OSA. The F4-M1 signal extracted from 62 participants (62.9% having OSA) was used to build a four-stage classifier. Performance of the ASSS was tested in a holdout set of 58 patients (60.3% having OSA) with epoch-by-epoch and whole-night agreement for sleep staging compared with expert scoring of polysomnography. RESULTS: Mean all-stage percentage agreement was 75.52% (95% confidence interval, 72.90 to 78.13) (kappa 0.62; 95% confidence interval, 0.58 to 0.65), with mean percentage agreement for wake, light sleep, deep sleep (DS), and rapid eye movement of 78.04%, 70.97%, 83.65%, and 75.00%, respectively. The whole-night agreement was good-excellent (intraclass correlation coefficient, 0.74 to 0.88) for sleep onset latency, wake after sleep onset, total sleep time, and sleep efficiency. Compared to the non-OSA subset, the OSA subset had lower agreement for DS. CONCLUSIONS: Our results indicate that a single-channel F4-M1 based ASSS was sufficient for sleep staging in a population with a high percentage of participants with OSA. CITATION: Lee P-L, Huang Y-H, Lin P-C, Chiao Y-A, Hou J-W, Liu H-W, Huang Y-L, Liu Y-T, Chiueh T-D. Automatic sleep staging in patients with obstructive sleep apnea using single-channel frontal EEG. J Clin Sleep Med. 2019;15(10):1411–1420.

This paper presents an ultra-low-power dual-mode automatic sleep staging processor design using a neural-network (NN)-based decision tree classifier to enable real-time, long-term, and flexible sleep monitoring. The ultra-low-power feature is achieved by an algorithm-hardware co-design approach that jointly considers optimization opportunities across the algorithm, architecture, and circuit levels to minimize power consumption; consequently, the first sub-10- $\mu \text{W}$ NN-based automatic sleep staging processor is realized. The dual-mode NN models are trained by an open-source large-scale dataset. The default mode achieves 81.0% classification accuracy based on two signals of one electroencephalography (EEG) signal and one electromyography (EMG) signal, and the compact mode achieves 78.5% accuracy based on only one EEG signal. In addition, the proposed design was verified using the National Taiwan University Hospital (NTUH) dataset, for which 81.1% and 77.1% accuracy is achieved in the default and the compact modes, respectively. A prototype chip using a 180-nm CMOS process occupies a total area of 11.74 mm2 and operates at 10 KHz while consuming 4.96 $\mu \text{W}$ at 1.2 V.

In this paper, we propose a floating-point signed digit (FloatSD) format for convolutional neural network (CNN) weight representation and its update method during CNN training. The number of non-zero digits in a weight can be as few as two during the forward and backward passes of the CNN training, reducing the convolution multiplication to addition of two shifted multiplicands (partial products). Furthermore, the mantissa field and the exponent field of neuron activations and gradients during training are also quantized, leading to floating-point numbers represented by eight bits. We tested the FloatSD method using three popular CNN applications, namely, MNIST, CIFAR-10, and ImageNet. These three CNNs were trained from scratch using the conventional 32-bit floating-point arithmetic and the FloatSD weight representation, 8-bit floating-point numbers for activations and gradients, and half-precision 16-bit floating-point accumulation. We obtained FloatSD accuracy results very close to or even better than those trained in 32-bit floating-point arithmetic. Finally, the proposed method not only significantly reduces the computational complexity for CNN training but also achieves memory capacity and bandwidth saving of about three quarters, demonstrating its effectiveness in the low-complexity implementation of CNN training.

This chapter gives an overview to the processing of retrieved signals in holographic data storage systems. The information to be stored is arranged in a 2-D format as binary or graylevel pixels and recorded by interference patterns called hologram. The fact that multiple holograms can be superimposed at the same location of the recording medium leads to volume storage that provides very high storage capacity. Two important channel defects, misalignments and inter-pixel interferences, are major causes for degradation in detection performance and their model is formulated mathematically. Several misalignments compensation algorithms are introduced. One algorithm adopts decision feedback to handle misalignments and interference simultaneously. Pixels are detected one by one after cancelling interference from neighboring pixels. The scan orders should be carefully designed when misalignments may involve pixels coming from other directions. Another algorithm makes use of oversampling, and then resample at location. Another algorithm combines interpolation and rate conversion to compensate various misalignments effects.

In the training process of convolutional neural networks (CNN), a batch normalization (BN) layer is often inserted after a convolution layer to accelerate the convergence of CNN training. In this work, we propose a BN processor that supports both the training and inference processes. To speed up the training of CNN, the proposed work develops an efficient dataflow integrating a novel BN processor design and the processing elements for convolution acceleration. We exploited the similarities in the calculations required for the BN forward and backward passes by sharing hardware elements between both passes, therefore reducing the area overhead. In addition to functional verification of the BN processor, we also completed Automatic Placement & Routing (APR) and conducted post-APR simulation on neural network training. Finally, the proposed solution not only significantly speeds up the CNN training process, but also achieves hardware saving.

Latest simultaneous multi-slice (SMS) methods greatly benefit MR efficiency for recent studies using parallel imaging technique. However, these methods are limited by the requirement of array coils. The proposed Coherent Wideband method, which employs an extended field of view to separate multiple excited slices, can be applied to any existing MRI instrument, even those without array coils. In this study, the Coherent Wideband echo-planar imaging method was implemented on 7T animal MRI to exhibit comprehensive enhancements in neuro-architecture, including diffusion tensor imaging (DTI) and functional MR studies (fMRI). Under the same scan time, the time-saving effect can be manipulated to increase the number of averages for DTI SNR improvement, reducing fractional anisotropy difference by 56.9% (from 0.072 to 0.041) and the deviation angle by 64% (from 25.3⁰ to 16.2⁰). In summary, Coherent Wideband EPI will provide faster, higher resolution, thinner slice, or higher SNR imaging for precision neuro-architecture studies.

This paper describes new approaches to minimum variance distortionless response (MVDR) beamforming for coherent plane-wave compounding (CPWC) in ultrasound imaging. Imaging results based on actual received and simulated waveforms show improvements over the traditional Delay and Sum (DAS) method as well as other MVDR-based methods, in terms of spatial and contrast resolutions. We designed detail circuits that can be configured to implement several of the aforementioned ultrasound beamforming methods effectively. The simulated operating frequency for the circuits implemented in FPGA is up to 62. 5MHz.

With the new IEEE 802.11ah standard aimed at improving the existing WLAN standard for the machine-to-machine applications, there is a renewed interest from the research community to analyze and suggest improvements to the standard. With thousands of smart devices and sensors involved in an internet of things network, the interference from multiuser access becomes a serious issue. This paper presents an access point (AP) coordinated multiuser access mechanism for such applications, where the strategy to improve channel usage efficiency is based on analyzing interference present in the neighborhood. Interference experienced in such a system is a function of node location, transmitted power, traffic load and resource allocation. In our proposed system, each WLAN AP from the overlapping basic service sets employs multiple frequency sub-bands and associates user nodes to these sub-bands dynamically. We show that this proposed interference-aware dynamic frequency allocation (IDFA) scheme, which is based on neighborhood contention analysis, can significantly enhance the system throughput and improve the energy efficiency by about 30%. In dense user node deployments, the channel access efficiency of the IDFA multi-band scheme is 2–3 times higher than that of the single band legacy WLAN.

Inter-cell interference (ICI) may considerably degrade the detection performance of receivers in heterogeneous networks (HetNets). To increase the spectrum efficiency per area, the cell ranges of small cells may be expanded, making the ICI problem more severe. Furthermore, to pursue higher data rate, spatial multiplexing is often applied, incurring inter-antenna interference (IAI). This paper presents a turbo receiver with a dual-loop dual-list update (TRDDU) structure that efficiently detects data signal deteriorated by both ICI and IAI. The proposed lists maintained several likely data vectors and interference vectors, facilitating the receiver to more efficiently determine the most-likely solution. In addition, a dual-loop update algorithm was proposed to enhance the iteration efficiency. Moreover, two design techniques were proposed to reduce the detection complexity. Simulation results showed that the error rate performance of TRDDU is close to that of a receiver in the ICI-free scenario. The complexity needed by TRDDU is only 3.5% that of the receiver that considers all possible interference vectors. In addition, the TRDDU complexity is only approximately 1.56 times that of a successive-interference-cancellation-based receiver. Finally, an over-the-air experiment was conducted to validate the effectiveness of the proposed TRDDU, and the results demonstrated the feasibility of this receiver in the field.

Self-organizing feature map (SOFM) is a type of artificial neural network based on an unsupervised learning algorithm. In this work, we present a circuit for accelerating SOFM training, which forms the foundation for an effective, efficient, and flexible SOFM training platform for different network geometries, including array, rectangular, and binary tree. FPGA validation was also conducted to examine the speedup ratio of this circuit when compared with training using software. In addition, we applied our design to three applications: chromaticity diagram learning, MNIST handwritten numeral auto-labeling, and image vector quantization. All three experiments show that the proposed circuit architecture indeed provides a high-performance and cost-effective solution to SOFM training.

The inter-cell interference (ICI) may considerably degrade the system performance of heterogeneous networks (HetNets) and is generally tackled by the transmitters, which often leads to lower spectrum efficiency. To avoid such disadvantage, this work presents a new receiver function that identifies the precoders assigned to active users in interfering cells, and thus enables more effective ICI mitigation. We theoretically derive the design criterion and analyze the performance of the receiver equipped with the proposed active precoder identification (API) scheme. We also propose two low-complexity techniques: the recursive structure based on the Sherman-Morrison formula/matrix determinant lemma, and the mode-switching technique adapting the search space on-the-fly. Numerical simulations demonstrate that such receiver can achieve error rate performance close to a receiver with perfect knowledge of the active precoders. The recursive structure achieves 68% complexity saving, while the mode-switching technique further increases the saving to 83%.

Purpose: In this study, single-frequency excitation wideband magnetic resonance imaging (MRI) (SE-WMRI) was proposed to obtain high-quality accelerated images by reducing phase-encoding steps while applying separation gradients. Methods: A zig-zag k-space trajectory with reduced phase-encoding steps and an increased readout sampling rate was proposed. A unique gradient design with buffer intervals near the trajectory turns was employed to avoid undersampling and image artifacts. A gridding method and Fourier transform were used for image reconstruction. Quantitative analysis was performed on phantom images to investigate the characteristics of the acceleration method. Results: The proposed method showed evident improvements in the accelerated phantom images, substantially reducing the ringing and blurring artifacts found using previous methods. Furthermore, the accelerated images exhibited the same signal-to-noise ratio as standard imaging. The accelerated in vivo experiment also produced the same quality as standard imaging. Conclusions: The proposed SE-WMRI method can effectively remove image artifacts and acquire images of higher temporal or spatial resolutions with less compromise.

This study proposes a modified Shinnar-Le Roux method to synthesize the excitation radio frequency (RF) pulse for a 2D gradient echo (GRE) based simultaneous multi-slice (SMS) magnetic resonance imaging (MRI) with features of low specific absorption rate (SAR) and small out-of-slice ripple. This synthesis method for SMS RF pulses employs thinner slice bandwidth and lower multislice offset frequencies to reduce SAR values and adopts a weighted Parks-McClellan algorithm to reduce sidelobes. Formulas for estimating relative SAR values of the SMS pulses are also introduced. Relative SAR values and out-of-slice ripples of the proposed and typical RF pulses with different parameters are presented. In simultaneous 5-slice phantom and 3-slice human brain imaging, SMS pulses synthesized with the proposed method achieve 32% and 28% SAR values of standard pulses while providing similar image qualities. Typical RF pulses such as sinc x cos can also take advantage of the proposed method and offer lower SAR values for SMS imaging. The RF pulse synthesized using the proposed method features low SAR, small sidelobes, and consistent image quality for 2D GRE-based SMS MRI. This method is applicable to the synthesis of typical SMS RF pulses for significant SAR reduction.

In this letter, we propose an efficient algorithm for the detection of the integer carrier frequency offset (CFO) and sector identity used in the LTE cell search. For the conventional LTE cell search, the integer CFO and sector identity are jointly detected by utilizing the primary synchronization signal (PSS). By exploiting the symmetric property of the PSS, the integer CFO can be solely detected without the knowledge of sector identity, and thus, the joint detection of the integer CFO and sector identity is decoupled. Additionally, the proposed sequential integer CFO and sector identity detection (SISID) removes the effect of the channel frequency responses such that the detection accuracy is enhanced. We also design the SISID hardware architecture where the parts of the signals are processed in the polar coordinate so that all the multiplications are realized by additions/subtractions. The simulation results demonstrate that the proposed SISID achieves better detection accuracy than the conventional methods with only one third of the computational complexity.

In this letter, we propose a low-complexity recursive decoding algorithm for rateless RaptorQ codes, the next generation error correction codes adopted by several standards such as DVB-H. Conventionally, the decoding of RaptorQ codes requires inverting a huge receive code generator matrix (RCGM). Instead of such costly matrix inversion, we propose to calculate the inverse of the transmit code generator matrix (TCGM) beforehand. Then, based on this pre-calculated inverse, the Sherman-Morrison formula is applied to recursively compute the inverse of the RCGM at run time. Most computations are thus shifted offline. Moreover, this recursive decoding distributes the computations among different time slots, thereby significantly shortening the decoding latency and improving the hardware utilization. Numerical simulations demonstrate that the computational complexity of the proposed recursive decoding is as low as 6.5% of that required by the conventional method using direct matrix inversion.

This paper presents a turbo receiver using the proposed ICI-aware Dual-List (IDL) MIMO detection method that can efficiently detect signals deteriorated by both inter-carrier interference (ICI) and inter-antenna interference (IAI). These two interferences often occur simultaneously in mobile multiple-input multiple-output (MIMO)-orthogonal frequency division multiplexing (OFDM) communication systems. The IDL detector enhances ICI mitigation and avoids the notorious error propagation problem encountered in conventional interference mitigation/cancellation schemes. In addition, this study proposes three techniques to reduce the required computational complexity by 99.63% in complex additions, 99.69% in complex multiplications, and 67.25% in comparison operations. Simulation results confirm the theoretical upper bound and also show that the bit error rate performance of the receiver in high-mobility channels is comparable to that of a maximum-likelihood MIMO-OFDM receiver in stationary channels, i.e., the ICI-free scenario.

The recently-proposed channel-adaptive multiple-input multiple-output (CA-MIMO) detection significantly reduces the average complexity of MIMO detection. Aiming at the just-acceptable error rate (JAER), the detection methods are switched according to the channel condition. In this letter, we formulate the switching of detection methods as a multiple-choice knapsack problem (MCKP). Then, based on the linear relaxation MCKP, the lower and upper bounds of the potential complexity saving of CA-MIMO are derived, where the former comes from our proposed switching strategy. The simulations show that the lower and upper bounds are tightly matched, demonstrating our two contributions: the evaluation of the optimal performance of the CA-MIMO detection without solving the NP-hard MCKP, and the design of an efficient and practical switching strategy.

In this paper, we present the design and implementation of a high precision Indoor Positioning System (IPS), with average accuracy within 0.5 meter and 90% of positioning errors smaller than 0.9m in three trial environments. The transmitter continuously transmitted periodic PN code and the multiple receivers at fixed locations performed signal acquisition, tracking, and position calculation. Several techniques were also integrated to combat the severe multipath effect. Finally, a Software Defined Radio (SDR) platform with baseband processing implemented in FPGA was constructed for real-time demonstration and validation of the effectiveness of this proposed IPS solution.

In this paper, we present a low-complexity cell-search algorithm and architecture for secondary synchronization signal in 3GPP-LTE downlink systems. Differential correlations are computed to remove common channel effects so that two sets of synchronization signals can be combined to obtain enhanced detection quality. To achieve low complexity, we further adopt one-bit quantization and exploit the properties of limited offset in the indices of the two maximal-length sequences. The arithmetic complexity of the proposed algorithm is significantly reduced while attaining similar detection performance comparable to the conventional schemes. Finally, hardware architecture of the proposed algorithm is presented to demonstrate feasibility and efficiency in the implementation.

Chapter 10 provides two essential MIMO IC designs. First, a QR decomposition module that offers the capability of either channel pre-processing or linear MIMO detection is illustrated. The second example is a soft-output MIMO detector supporting antenna configuration from 2 ?? 2 to 8 ?? 8.