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Because of the chemical inertness of two dimensional (2D) hexagonal-boron nitride (h-BN), few atomic-layer h-BN is often used to encapsulate air-sensitive 2D crystals such as black phosphorus (BP). However, the effects of h-BN on Schottky barrier height, doping, and contact resistance are not well-known. Here, we investigate these effects by fabricating h-BN encapsulated BP transistors with cobalt (Co) contacts. In sharp contrast to directly Co contacted p-type BP devices, we observe strong n-type conduction upon insertion of the h-BN at the Co/BP interface. First-principles calculations show that this difference arises from the much larger interface dipole at the Co/h-BN interface compared to the Co/BP interface, which reduces the work function of the Co/h-BN contact. The Co/h-BN contacts exhibit low contact resistances (-4.5 kΩ) and are Schottky barrier-free. This allows us to probe high electron mobilities (4,200 cm2/(V s)) and observe insulator-metal transitions even under two-terminal measurement geometry. [ABSTRACT FROM AUTHOR]

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics. [ABSTRACT FROM AUTHOR]

Majorana zero modes (MZMs), prime candidates for topological quantum bits, are detected as zero bias conductance peaks (ZBPs) in tunneling spectroscopy measurements. Implementation of a narrow and high tunnel barrier in the next generation of Majorana devices can help to achieve the theoretically predicted quantized height of the ZBP. We propose a material-oriented approach to engineer a sharp and narrow tunnel barrier by synthesizing a thin axial segment of GaxIn1-xSb within an InSb nanowire. By varying the precursor molar fraction and the growth time, we accurately control the composition and the length of the barriers. The height and the width of the GaxIn1-xSb tunnel barrier are extracted from the Wentzel-Kramers-Brillouin (WKB) fits to the experimental I-V traces. [ABSTRACT FROM AUTHOR]

Majorana zero modes, with prospective applications in topological quantum computing, are expected to arise in superconductor/semiconductor interfaces, such as β-Sn and InSb. However, proximity to the superconductor may also adversely affect the semiconductor's local properties. A tunnel barrier inserted at the interface could resolve this issue. We assess the wide band gap semiconductor, CdTe, as a candidate material to mediate the coupling at the lattice-matched interface between α-Sn and InSb. To this end, we use density functional theory (DFT) with Hubbard U corrections, whose values are machine-learned via Bayesian optimization (BO) [ npj Computational Materials 2020, 6, 180]. The results of DFT+U(BO) are validated against angle resolved photoemission spectroscopy (ARPES) experiments for α-Sn and CdTe. For CdTe, the z -unfolding method [ Advanced Quantum Technologies 2022, 5, 2100033] is used to resolve the contributions of different k values to the ARPES. We then study the band offsets and the penetration depth of metal-induced gap states (MIGS) in bilayer interfaces of InSb/α-Sn, InSb/CdTe, and CdTe/α-Sn, as well as in trilayer interfaces of InSb/CdTe/α-Sn with increasing thickness of CdTe. We find that 16 atomic layers (3.5 nm) of CdTe can serve as a tunnel barrier, effectively shielding the InSb from MIGS from the α-Sn. This may guide the choice of dimensions of the CdTe barrier to mediate the coupling in semiconductor-superconductor devices in future Majorana zero modes experiments. z values to the ARPES. We then study the band offsets and the penetration depth of metal-induced gap states (MIGS) in bilayer interfaces of InSb/α-Sn, InSb/CdTe, and CdTe/α-Sn, as well as in trilayer interfaces of InSb/CdTe/α-Sn with increasing thickness of CdTe. We find that 16 atomic layers (3.5 nm) of CdTe can serve as a tunnel barrier, effectively shielding the InSb from MIGS from the α-Sn. This may guide the choice of dimensions of the CdTe barrier to mediate the coupling in semiconductor-superconductor devices in future Majorana zero modes experiments.

In this paper, nonlinear and low-power resistive switching characteristics of Si 3 N 4 -based RRAM embedding SiO 2 tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO 2 layer. Furthermore, we offer an optimized solution by modulating compliance current ( I CC ), read voltage ( V READ ), and TB thickness for higher selectivity. Low current operation tuned by I CC , V READ , and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications. [ABSTRACT FROM AUTHOR]

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics.

The two-dimensional atomically thin insulator hexagonal boron nitride (h-BN) constitutes a new paradigm in tunnel based devices. A large band gap, along with its atomically flat nature without dangling bonds or interface trap states, makes it an ideal candidate for tunnel spin transport in spintronic devices. Here, we demonstrate the tunneling of spin-polarized electrons through large area monolayer h-BN prepared by chemical vapor deposition in magnetic tunnel junctions. In ferromagnet/h-BN/ferromagnet heterostructures fabricated on a chip scale, we show tunnel magnetoresistance at room temperature. Measurements at different bias voltages and on multiple devices with different ferromagnetic electrodes establish the spin polarized tunneling using h-BN barriers. These results open the way for integration of 2D monolayer insulating barriers in active spintronic devices and circuits operating at ambient temperature, and for further exploration of their properties and prospects. [Figure not available: see fulltext.] [ABSTRACT FROM AUTHOR]