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A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (Vcc) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal Vcc or at least 17% Vcc reduction at equal throughput, corresponding to 31 %-37 % total power reduction. [ABSTRACT FROM AUTHOR]

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-VT CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10× better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits. [ABSTRACT FROM AUTHOR]

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm² experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W. [ABSTRACT FROM AUTHOR]

In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 µs, resulting in 37× reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2× with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75 °C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile. [ABSTRACT FROM AUTHOR]

Investigates the effectiveness of adaptive supply voltage and frequency binning of fabricated microprocessors. Description of a test chip fabricated in complementary metal oxide semiconductor technology; Measurement of the test chip; Distributions of frequency, active power, switched capacitance and standby leakage power.

Describes a five–gigahertz 32–bit arithmetic-logic unit (ALU) integer execution core in 130–nanometer dual-V[sub T] complementary metal oxide semiconductor technology. Requirements for out-of-order execution engines of superscalar processors; Evaluation of complex logic operations; Organization of both the ALU and scheduler as a loop in the execution core.

Examines the effectiveness of the bidirectional adaptive body bias (ABB) technique in reducing the effects of process parameter variations on the frequency and leakage of microprocessor dies. Significance of power density in microprocessor design; Results of measurement from the ABB test chip; Provision of bin split improvement in the presence of increasing process parameter variations.