Search

In the process of development in the Semiconductor Industry, Intellectual Property (IP) piracy has become a threat to innovation. To reduce this, logic encryption is found to be an effective solution. It is achieved by employing the concept of keys for the circuits. In this paper, logic encryption is a concept is applied to the previously proposed Least Transistor Count (LTC) full adder. The concept of least gates is taken for its advantage for its low power and delay when compared to conventional adders. The proposed work is compared with the LTC full adder and with similar encrypted full adders and has observed 1000 times decrease in power. Delay is recorded as 25ns for sum and 4.32ps for carry signal. The proposed work has 56 per cent more power and 80 per cent more area than the LTC adder. But it has achieved a drop of 59 per cent in transistor count than previous works and a strong level of encryption than previous works. The proposed encrypted full adder is extended to a Multiplier and Accumulator (MAC) unit design. An encrypted MAC design is proposed by focusing on the key combinations and positions.

Memory and Logic computing beyond Von Neumann architecture is of paramount importance in Artificial Intelligence data-intensive applications. To this end, we propose a novel concept of Logic with Built-in Memory. We intend to combine Crosstalk logic, a novel computing method that harnesses deterministic interference between interconnect metal lines for logic calculations, with data storage elements to generate neoteric Crosstalk circuits capable of storing the state of the computed data. In this paper, we present how Crosstalk Computing can be leveraged to implement basic and complex circuits with built-in memory at 16 nm technology node. We show a range of circuits and discuss both logic and memory characteristics through circuit simulations. In addition, we discuss comparison results with equivalent CMOS circuits. Our results indicate a 32% reduction in transistor count for a full adder (FA) circuit with respect to CMOS at 16nm. The average power for a FA is 3μW and the maximum propagation delay is 58 ns.

While square and square root are critical for vector operations, several challenges exist in their computation in the digital domain including power, area, and delay overheads. While selective computation in the analog domain is a longstanding alternative, tradeoffs of increased noise and reduced accuracy are prominent challenges. Herein, we propose a reconfigurable analog circuit which is capable of performing any nth-power and nth-root function and may be implemented within an analog or mixed-signal field programmable array. The resulting analog block of Magnetic Tunnel Junctions (MTJs) along with FET-based sensing and amplification circuits are circuit-switched-configurable with terminal-level control. Herein the design is configured to rapidly evaluate various arithmetic operations within acceptable error tolerances for selected applications. When compared to a state-of-the-art approximate digital multiplier, our design yields 97% reduction in transistor count and stable output within a period comparable to single-cycle execution. When compared to an alternative recently proposed analog multiplier, the proposed design yields improvement in error and versatility to perform generalized operations.

Near-threshold voltage (NTV) design has been proposed for low-power VLSI designs across a wide range of applications due to its optimal Energy-Delay Product. Dynamic Voltage and Frequency Scaling (DVFS) design has acquired recent interest to increase energy efficiency during runtime. During periods of low utilization, a chip’s performance and power consumption can be adjusted by slowing down the clock speed and decreasing the supply voltage, thereby bringing its operation to the NTV region. However, high dynamic variations at low voltage operation is the key design challenge and barrier for near-threshold adoption. Hence, it becomes mandatory to consider large timing margins during design to ensure high yield and robust operation. Error resilient circuits help to restore the timing margins, thereby improving performance with low power consumption. This paper presents EDTB (Error Detection with Time-Borrowing), a novel architecture for multi-stage timing error resilience which masks timing errors by borrowing time from successive pipeline stages, without slowing down the clock speed. The proposed error handling scheme doesn’t require error recovery mechanisms like instruction replay or roll-back; hence it doesn’t associate any error recovery penalty. EDTB-based error masking is resilient to glitches and spurious transitions due to its minimal hold time requirement. EDTB architecture shows a significant improvement of up to 34% in transistor count and 50% in clock routing over the previous architecture. The circuit schematic was prototyped in Cadence Virtuoso ADE in a 7-nm FinFET based predictive process design kit; followed by simulation, validation, and further comparisons.

The progress in the design of a charge pump (CP) circuit has noted some vital non-idealities such as current mismatch, phase noise and reference spur. Also, lock-in time is considered as one of the most important attributes for which a high-performance CP design always remains as an open challenge for potential application in high-speed mobile communication. This article explores an Operational Amplifier (Op-amp) based optimal gate count CP designed for 90nm CMOS using CADENCE Virtuoso platform at a supply voltage of 1.2Volt to burn as small as 226uW of power. The measured phase noise and reference spur are -117.3 dBc/Hz and -113.8 dBc/Hz at an offset frequency of 10MHz. The reported locking time of 9.15ns only with a current mismatch of 0.22% makes it competent enough for PLL driven communication modules.

In this paper, a novel low-leakage six transistor static random access memory (SRAM) is proposed in IGFinFET technology. This cell is a great candidate for “In-memory-computing” because of the minimum transistor count and decoupled read and write operations. According to simulations in 10 nm FinFET technology, the RSNM, and WM of the proposed cell is 2x and 1.7x higher than conventional 6T cells at 500 mV supply voltage. This results in enabling the ability to decrease the supply voltage of the memory array, without risking the stability, to save power. Besides, to further improve in-memory computing, a new polymorphic logic gate with eight transistors has been proposed. Using the proposed polymorphic gate decreases the latency of in-memory computation and enables the in-memory vector to compute with low overhead.

Computing-In-Memory (CIM) techniques which incorporate analog computing inside memory macros have shown significant advantages in computing efficiency for deep learning applications. While earlier CIM macros were limited by lower bit precision, e.g. binary weights in [1], recent works have shown 4-to-8b precision for the weights/inputs and up to 20b for the output values [2], [3]. Sparsity and application features have also been exploited at the system level to further improve the computation efficiency [4], [5]. To enable higher precision, bit-wise operations were commonly utilized [3], [4]. However, there are limitations in existing solutions using the bit-wise operations with SRAM cells. Fig. 15.3.1 shows the summary of challenges and solutions in this work. First, all existing solutions utilize 6T/8T/10T SRAM as a CIM cell, which fundamentally limits the size of the CIM array. In this work, we replace the commonly used SRAM cell with a 3-transistor (3T) analog memory cell, referred as dynamic-analog-RAM (DARAM) which represents a 4b weight value as an analog voltage. This leads to $\sim 10 \times$ reduction in transistor count and achieves an effective CIM single-bit area smaller than the foundry-supplied 6T SRAM cell. Secondly, as no bit-wise calculation is needed in this work, only single-phase MAC operations are performed, removing the throughput degradation associated with previous multi-phase approaches and digital accumulation in [3], [4]. Furthermore, analog linearity issues are mitigated by highly linear time-based activation, removal of matching requirements for critical multi-bit caps [4], [6], and a special read current compensation technique. Thirdly, to mitigate the power bottleneck of ADC or SA, this work applies analog sparsity-based low-power methods, which include a compute-adaptive ADC skipping operation when the analog MAC value is small (or “sparse”) and a special weight-shifting technique, leading to an additional $\sim 2 \times$ reduction in CIM-macro power. We demonstrate the proposed techniques using a 65nm CIM-based CNN accelerator showing state-of-art energy efficiency.

In this paper, two new efficient modular adders are implemented using basic logic gates. The designed modular adder consists of AND gates and OR gates. Modular addition is the most important and frequent operation applied to the components of Residues number systems. The technology used for designing these adders is Verilog coding in Xilinx ISE 14.7. The conventional mux’s based method consists of decoder and encoder to covert one of the operand to binary format in both the techniques. The small and medium dynamic range requirements of low-power embedded and edge devices make the usage of the thermometer coding and one-hot coding viable, reducing the power consumption and improving the energy efficiency of modulo addition in comparison to regular binary representations. The major problem with the conventional method is increase in transistor count, delay, power consumption and area. This research work principally concentrated to curtail the power consumption and to increase the performance of the mux based structure by replacing the multiplexers with the basic logic gates so as to reduce the delay. With the purpose of reducing power consumption, AND and OR gates are implemented using various logics such as Complementary metal oxide semiconductor (CMOS) logic, AND-OR Inverter (AOI), OR- AND Inverter (OAI) logic. Performance parameters of thermometer and one-hot coding such as conversion time as well as average power calculated and compared. It is verified obtained using logic gates are average power 14.68mW, 15.36mW and delay 7.915ns, 6.608ns and area i.e., LUTs used are less compared to the mux based structure and with other designs.

In this paper, an enhanced self-checking carry select adder (CSeA) architecture is introduced. However, we first show that the carry select adder design presented literature does not have the self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the self-checking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.

In the era of technological evolution and advancement, energy is the key element or ingredient of all sorts of development. Most of the electronic goods or appliances are based on a battery-operated system. The portable devices are extensively used in laboratories, offices, and industry and defense items. Long-life battery is the merit and an added advantage of any electronics appliances. Low power dissipation ensures the long duration of the stored energy. The arithmetic circuit is a preliminary element of many computing devices. Minimizing the power dissipation of fundamental arithmetic components such as full adders will severely reduce the power across the high-end electronic system. Thus, adiabatic logic is a promising technology that can generate a power-aware circuit with high switching activity. Hence keeping this condition into consideration, this paper introduces a novel circuit of low power 6-Transistors 1-bit adiabatic full adder circuit. The combination of low power and low transistor count makes the new 6-Transistors adiabatic full adder, an achievable option for an efficient design. This paper presents the design of an adiabatic technology-based full adder in 45 nm technology node. The proposed design outperforms over the existing circuits with an exceptional improvement of 33.3% for transistor count and 76% for power dissipation.

One of the most important hardware blocks in processors is the multiplier circuit module. Area, power, and delay rule as primary factors deciding VLSI design methodologies. The work presented in this paper focuses on these three factors using Vedic multiplication approach and gate-diffusion input (GDI) logic. The ancient system of Indian mathematics being the Vedic mathematics, rediscovered from the Vedas, is more simplified, faster and accurate as compared to normal multiplication methods. The primary advantage of gate-diffusion input (GDI) logic is helping in reduced transistor count. Hence, the combination of these approaches of Vedic multiplication implemented using GDI logic results in reduced propagation delay time, lower power consumption, and less silicon area. In this paper, the proposed 2-bit Urdhva cell used is implemented using AND gate, XOR gate, and an inverter unlike the existing literature in which it is implemented using two half adders. The results are validated for the comparative advantages of our approach. The circuit simulations are carried out using UMC 90 nm technology nodes in Cadence Virtuoso.

Gate Diffusion Input (GDI) is a technique of low-power combinational circuit design. Complex logic functions like F1, F2, OR, AND, MUX and NOT can be implemented using just two transistors. GDI reduces area, propagation delay and power consumption of digital circuits, and has lower logic complexity than traditional CMOS and existing pass transistor logic techniques. Low power dissipation is achieved by reducing transistor count. Reducing area lowers the interconnect effects. In this paper, first the logic gates (GDI and CMOS) were implemented in Cadence in 90 nm and gate-libraries were created for these. To estimate the complexity and scalability of GDI, ISCAS-85 benchmark circuits were synthesized using these libraries and compared in terms of area, power and delay. GDI circuits prove to be better in terms of area and power than their CMOS counterparts though slightly slower. They may be made faster by buffering logic after every few stages.

The increasing cost of manufacturing integrated circuits (IC) has forced many companies to go fabless. With the outsourcing of IC fabrication in a globalized/distributed design flow, including multiple (potentially untrusted) entities, the semiconductor industry faces several challenging security threats. This fragility in the face of weak state-of-the-art intellectual property (IP) protection has resulted in hardware security vulnerabilities, such as IP piracy, overbuilding, reverse engineering, and hardware Trojans. To address these issues at the hardware level, different design-for-trust (DfTr) techniques, such as IC metering, watermarking, IC camouflaging, split manufacturing, and logic locking have been proposed to secure digital circuits. Though there are many DfTr techniques to secure digital circuits, there is a great dearth of techniques for analog and mixed-signal (AMS) IP protection. However, analog ICs are more prone to supply-chain attacks than digital ICs as they are easier to reverse engineer. This high vulnerability is due to their low transistor count compared to their digital counterparts. To address the impact of process variations, they also have predefined layout patterns, e.g., common-centroid. Analog ICs are not simple, although they have less number of transistors. Even with only hundreds of transistors, analog IC design requires highly experienced designers and a long time, as analog behaviors are quite complicated.

As the time goes by binary logic is getting harder to implement on a smaller scale, so ternary logic becomes a better alternative of the same. Ternary logic has the simplicity over binary logic, and it is energy efficient also. Large number of interconnects and large chip area are the few problems of binary logic, which are reduced in ternary logic. This paper discussed a design of efficient ternary subtractor using carbon nanotube field-effect transistors (CNTFETs). The proposed design is compared with recent existing design on various performance parameters like transistor count, time delay, etc. The proposed design outmatches recent existing designs in all the parameters by 33.30%, 21.18%, and 47.32% in power consumption, delay, and PDP, respectively.

Energy consumption in embedded systems is becoming increasingly important especially with the increase in transistor count that needs to fit in smaller chip areas. This calls for a cross-layer effort to improve the energy consumption of an embedded design including design of energy-efficient algorithms. Consequently, we need to find ways for a programmer to quickly estimate the energy consumption of an algorithm at higher abstraction level. This work contributes towards the development of an assembly-level energy estimation framework for embedded processors. Our framework is based on a hybrid approach of instruction level power analysis (ILPA) and functional level power analysis (FLPA) techniques which results in a higher accuracy comparable to ILPA-based approaches while remaining at a higher abstraction level of FLPA for the modeling of processors. The proposed framework, therefore, provides rapid high-level energy estimation results with an accuracy consistent with the state-of-the-art approaches. As test-cases, we have used the proposed framework for two open-source IP-core processors i.e. MIPS R2000 and LEON3.

In the field of VLSI, enhancement is prominent. Arithmetic circuits are one of the influential sectors in today’s end products of electronics, where multipliers are one of the deciding factors of efficiency. Multiplier plays an important role in different applications such as digital signal processing in which it acts as a key hardware block. As time rolls down, the technology exposed the ways for the initiation of many hardware and software implementations of the faster multipliers. One among them is the Montgomery multiplier. The fundamental operation in the Montgomery multiplier is the modular multiplication. It is mainly used in FIR filters, which in-turn has numerous applications such as speech analysis, multi-rate signal processing, adaptive filters, and averaging filters. With the usage of proposed compressor in the conventional design of the multiplier, the number of transistor count has been declined by a significant amount and made the design into an optimal area design. This paper presents a modified Montgomery multiplier design and its implementation in the 5th order FIR filter. The entire design simulation is carried out using CMOS and PTL logic in 45 nm technology. There is an escalation in the result outcomes, and the multiplier has an area efficiency of 65% and a power reduction of about 68% in comparison with conventional design.

Different adder structures have been reviewed with CMOS logic and hybrid logic styles in this paper. XOR/XNOR cell, which is the key element in full adder design was also reviewed. Hybrid adders have advantage of low delay and low area occupancy due to less transistor count used. Lower value of PDP also can be achieved with hybrid structures. Adder structures are implemented in this paper by designing XOR and XNOR cells. Critical path estimations are made and number of transistors in critical path helps in estimating the critical path delay. Delay comparison for several adders was reviewed.

The rapid growth in the use of portable systems has sparked research and development in the field of microelectronics especially for power consumption. Since battery technology does not match the speed of microelectronics, Low-power technology has become an important technological factor. MGDI is a minimum-power architecture design, which is quite a Gate Diffusion Input (GDI) change and is the lowest design method optimal for rapid, low power circuitry model using a reduced number of a transistor. Here, primitive cells-AND, OR, and XOR gates, full adders, full subtractors, and 4×4 multiplier have been proposedusing the 180nm technology-dependent MGDI in Cadence Virtuoso device. The main downside associated with GDI is that this strategy cannot resolve the bulk terminal which is not sufficiently biased. So that the number transistor count and delay will be reduced.

The Vedic multiplier has a very fastest arithmetic operation and less complex than a multiplier. The Vedic multiplier is used to simplify the multiplication process and delay. If the Vedic multiplier is designed by using CMOS transistors, the circuit will raise problem. To overcome this issue, the Gate Diffusion Input (GDI) logic has been implemented in this paper using FinFET technology. Here, GDI logic is used to reduce the transistor count of the circuits. However, in these process, two types of design approaches are considered. The first type approach aims to implement the 4-bit Vedic multiplier (Design 1) using GDI based AND, half adder, and full adder circuits. Second type approach is intended to design a 4-bit Vedic multiplier (Design 2) by using GDI based 2-bit Vedic multiplier, half adder and 4-bit Ripple carry circuits. In these, the circuit performance factors like average power, delay and transistor count, and circuit area are considered.

This paper presents a modular design of Arithmetic Logic Unit based on memristor and CMOS logic. The proposal has been implemented using ThrEshold Adaptive Memristor model (TEAM). The functional verification is done using simulations on Cadence Virtuoso tool. There is significant reduction in transistor count using the proposed approach which will lead to significant decrease in overall implementation area. Comparison of this approach helps us to reduce the chip area as well as power utilization and it is reliable as well.

Conventional static CMOS design employing pull-up and pull-down network for implementing logic functions has been one of the most reliable and widely used design techniques over the years. However, high input impedance and transistor count remains a major problem which result in high silicon area, high power consumption and increased delay. This research focus on reducing power, delay and transistor count in Conventional Static CMOS based 4-bit Carry Look Ahead adder. The conventional static CMOS XOR and gates are replaced by Gate Diffusion Input technique and Pass Transistor logic based XOR and AND gates in the input side to enhance performance parameters and to reduce transistor count. Two new modified CLA adder have been proposed and their performance parameters have been compared with conventional circuit using Cadence simulation tools. The proposed designs showed significant performance improvement while keeping the advantages of static CMOS Logic.

This paper introduces the design of 2-4 and 4-16 line decoders using modified version of gate diffusion input (M-GDI) technique as it reduces the area that is the number of transistors and also it reduces the dissipation of power. The Combinational circuits like decoders which are used in the periphery circuitry of memory arrays like Static RAM are designed by using Modified Gate Diffusion Input (M-GDI) technique which eradicate the disadvantages of the pass transistor logic (PTL) and CMOS logic. The decoders which are designed using modified GDI technique offer better characteristics in terms of average power and delay, and also the transistor count is reduced compared to the decoders which are designed using mixed logic technology which are static CMOS, pass transistor logic and transmission gate logic. Finally, the decoders which are designed by using two techniques in 90 nm technology using Cadence Virtuoso compared in terms of transistor count, average power, delay and power delay product (PDP) show an improvement when compared to the decoders of mixed logic.

Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay.

Counters are a generally useful circuit that appear in many contexts. Because of this, the design space for clocked counters has been widely explored. However, the same cannot be said for robust clockless counters. To resolve this, we designed an array of constant response time counters using the most robust clockless logic family, quasi-delay-insensitive (QDI) circuits. We compare our designs to their closest QDI counterparts from the literature, showing significant improvements in design quality metrics including transistor count, energy per operation, frequency, and latency in a 28-nm process. We also compare our designs against prototypical synchronous counters generated by commercial logic synthesis tools.

In this paper, a 1-bit full adder is implemented using the Gate-Diffusion-Input (GDI) technique and its design analysis is carried out. The design parameters such as delay, power consumption, energy delay product, energy and transistor count are compared with the conventional static CMOS based design. The effect of parasitic capacitance is analyzed via post layout simulation. This reveals that the delay and power consumption of the GDI adder is around 19% and 94% less than to that of CMOS based approach along with reduced number of transistor count.

Since miniaturization of CMOS has taken place, speed and power are the most important parameters for any circuit, like speed of an adder is a critical parameter in the overall performance of an Arithmetic Logic Unit (ALU). In order to identify the best suitable 2-bit adder in terms of speed, power dissipation, area and leakage current acomparative study of five different kinds of standard 2-bit adder architectures, Ripple Carry (RCA), Carry Look ahead (CLA), Manchester Carry Chain (MCC), Carry Select (CSL) and Kogge Stone (KSA) adders has been done in this paper.The adders are re-designed, implemented and analyzed at supply voltages ranging from 0.6 - 1 V on 28nm CMOS Technology to improve the speed and power. Simulation results for the different adders show that MCC at 0.6V is 32.4% faster than RCA and 15.6% faster than CLA. RCA having minimum transistor count has the least power dissipation and CLA gives minimum leakage current for lower supply voltages, but as the supply voltage increases MCC produces the least leakage current.

Low power technology emerges with increasing transistor count in a miniaturized silicon chip. Power optimization in technology, circuit, layout, logic, architecture and algorithmic levels should be mandatory. Hierarchical level of testing in digital devices to meet the customer requirements will increase device power consumption. Increased test power is the result of built in testing structures embedded in the devices. Test vectors applied during testing suffers from increased transition of vectors from one stable state to another, which causes too much of power loss in digital devices. This paper is proposed to measure the switching activity and dynamic power consumption of the circuits implemented in AOI, NAND and NOR format. Peak and average switching activity and peak dynamic power consumption for the circuits at different implementation during normal and test mode are estimated. The resultant values are compared against each implementation and the best with minimum switching activity and dynamic power is preferred to design a low power circuit.

Redundant gates of 4-2 compressor (hereafter, it is referred as 42C) has been removed by simplification of compressor output Boolean expression, that results in power consumption minimization. Further, the proposed design is implemented in full swing gate diffusion input logic, a low-power design technique with minimum transistor count. To evaluate the performance of existing and proposed compressor designs, they are simulated using SPICE simulation at 45 nm technology model. Also, the area is calculated from their corresponding generated layouts for the same technology model. From the simulation results, it is observed that the proposed compressor has shown performance improvement in terms of power delay product by 45% than the recently reported compressor. Further, to study the performance of proposed compressor in an application environment, a 16-bit multiplier is implemented. Its simulation results confirmed that the performance improvement is consistent in the multiplier too.

A new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor's resistivity, which is used to define different weight values, and reduces significantly the transistor count. When considering an upper bound on transistor count, the proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45-nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption.

This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a $\Sigma \Delta$ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-inversion block, required by the correlated-double-sampling, is moved to the front of the adder. Following such a technique as this, more than six inverters and multiplexers can be reduced. This paper also proposes an adder scheme with only 118 transistors to implement the 13-bit dynamic range integrator. Moreover, the number of MSB cells inside the ripple counter is optimized to balance leakage current and active power consumption. Compared with the prior art, the proposed decimation filter core (without registers) can achieve a reduction of about 24% in transistor count. The proposed design is implemented with a 130-nm standard CMOS process. The total chip area of the digital decimation filter is only $4.5\times 145~\mu \text{m}^{2}$ per column, which is less than half area compared against the prior art. According to the post-layout simulation, the maximum operating frequency is 124 MHz, and the total power consumption, including the filter core and 13-bit registers, is less than 6.35 $\mu \text{W}$ under a typical 50-MHz clock frequency.

This paper targets to present energy efficient high speed true single phase clock dynamic circuit design technique, utilizing a novel body biasing tuner. The threshold voltage is controlled dynamically by dint of a novel body bias tuner so that performance of the circuit is enhanced in terms of power, delay, temperature, voltage, noise and corner variations. Power consumption and delay is computed and analysed for wide range of temperature and 40.78–95.5% saving in power delay product is obtained with the same. Quantification of bias voltage variation effect and process corners to find the effectiveness of the proposed design are examined and it is found to be performing consistently as compared with other techniques. Later on bouncing noise analysis is done for the valuation of noise in the circuit. Comparison of power delay product, transistor count and clock phase is done with several previously reported designs. Comprehensive simulation in cadence using 90 nm technology, shows that the proposed design vanquish conventional and other previously reported dynamic circuit design techniques in all aspect of circuit performance. Further, an arithmetic logic unit for measurement using sensors is implemented as a prolongation of the proposed dynamic circuit design technique.

Physical Unclonable Functions (PUFs) are devices which exploit manufacturing variability to uniquely distinguish individuals, thus preventing cloning for malicious purposes. With the increasing demand for low-cost devices, PUF designs which can effectively combine small silicon area and power consumption with high resistance to attacks have become of great interest. Unfortunately, many delay-based PUFs have revealed security weaknesses, making them less useful in such domains. This paper presents a novel delay-based strong PUF, the CRPUF (Cylindrical Reconvergence PUF). CRPUF is based on a carefully designed cylindrical XOR fabric, which allows for a large number of delay paths, thus producing a large combination of challenge-response pairs (CRPs) with relatively low transistor count. Simulations based on circuit delay variability models were performed to evaluate CRPUF with respect to well-known delay PUFs. The simulation results were then validated against an FPGA prototype to show that the desirable properties of the CRPUF can be obtained in a realistic physical implementation. Experiments show that CRPUF has Hamming Distance, Hamming Weight and Entropy comparable to the best results published so far, with acceptable levels of Bit Error Rate. Moreover, experiments also show that CRPUF is much more resistant to modeling attacks than other delay and some memory-based PUFs, making it a good candidate to systems which have stringent cost and security constraints.

In this paper, we introduce the Multiple-Output Monotonic CMOS (M2CMOS) logic style, which is applied on the design of a high-performance and energy-efficient 64-bit incrementer/decrementer circuit. M2CMOS is proposed as an enhancement to standard monotonic-static logic and a viable alternative to domino logic for high-performance applications. A simulation-based comparative analysis at the 32 nm concludes that, compared to other state-of-the-art designs, the proposed incrementer/decrementer achieves the best results in terms of gate/transistor count, delay, energy-delay-product and standby power.

An integer linear programming-based framework to identify the current-mode threshold logic functions is presented. The approach minimizes the transistor count and benefits from a generalized definition of threshold logic functions. It is shown that the threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of rational weights is proposed. Process variations, transistor aging, and circuit parasitics are taken into consideration. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of the existing threshold functions is reduced when comparing with the traditional CMOS-based threshold logic implementation.

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.

In this work, two dimensional six-contact phase change devices that can perform toggle logic operations is analyzed through 2D electrothermal simulations with dynamic materials modelling, integrated with CMOS access circuitry. Toggle configurations are achieved through a combination of isolation of some contacts from others using amorphous regions and coupling between different regions via thermal crosstalk. Use of thermal crosstalk as a coupling mechanism in a multi-contact device in the memory layer allows implementation of analog routing and digital logic operations at a significantly lower transistor count, with the added benefit of non-volatility. Simulation results show approximately linear improvement in peak current and voltage requirements with thickness scaling.

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods.

We propose a new multiplier design that fulfills the need for low-power circuit blocks used in error-tolerant applications on energy-constrained devices. The design trades accuracy for higher speed, lower energy consumption, and lower transistor count. The average relative error of an N-bit multiplier is modeled as a function of N and saturates at a constant (around 17%) as the multiplier width increases. An 8-bit implementation simulated in HSPICE achieved almost 90% energy savings for a random sample of operands as compared to a conventional parallel multiplier. The design is flexible whereby simple variations to the circuit structure lead to a perfectly accurate multiplier. Tests performed on multimedia applications such as JPEG compression showed a promising outcome.

The paper discusses a unique method to design low power circuits, which is called Gate Diffusion Input (GDI) method. Complex functions can be implemented using only two transistors by using this method. GDI technique allows for reduced power consumption, lower delay, lesser transistor count and decreased area of circuits. It also makes the system design less complex. Full adders and parallel adders, are major building blocks of different digital components like ALUs, DSPs etc. Hence, reducing power consumption of adders is very important. This work aims at building a parallel adder that consumes less power. A GDI based XOR gate is designed using which, a 10T full adder is designed which involves lesser number of devices compared to CMOS Full adder. The threshold loss in full adder is a major pitfall. A standard CMOS process compatible version of GDI cell, modified GDI, mGDI cell is proposed, using which a full adder is built. A 4-bit parallel adder is designed. The proposed technique consumes lesser area and has low power dissipation compared to CMOS design. Power consumption is reduced by 15% compared to CMOS design. Cadence tool at 180 nm is used to implement the designs.

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and im age processing.

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

The combination of Moore's law and Dennard's scaling laws constituted the fundamental guidelines that provided the semiconductor industry with the foundation of a technically and economically viable roadmap until the end of the previous century. During this time, the transistor evolved from bipolar to PMOS to NMOS to CMOS. However, by the mid-1990s it was clear that fundamental physical limits of the MOS transistor were going to halt Dennard's scaling by 2005, at best. Eventually the power consumed by a single IC, under the relentless growth in the number of transistors and the continuous increase in operating frequency, pushed the IC temperature beyond reliable limits. Several new memory devices operating on completely new physics principles have been invented in the past 10 years and have already demonstrated that computing performance can be substantially improved by monolithically integrating several of these new heterogeneous memory layers on top of logic layers powered by a combination of CMOS and "new switch" transistors. This new phase, called 3D power scaling, will continue to support increase in transistor count at Moore's law pace well into the next decade.

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.

Multipliers are used in the building blocks of several processors. Conventional multiplication is time consuming and lengthy process; to overcome these drawbacks the circuit designers must develop speedy multipliers. Vedic multipliers can be utilized for high speed multiplication process. In Designing of CMOS circuits an issue of area is always there, to reduce this Gate Diffusion input (GDI) technique can be used. The GDI concept assist in reduction of Transistor Count (TC), due to this power dissipation is minimized. In this study the design of fast speed 4×4 Vedic Multiplier has been presented using GDI technique. The power dissipation of proposed multiplier is reduced as compared to conventional CMOS multiplier.

While the physical design steps introduced in Chaps. 4 and 5 are universal, analog integrated circuits present further challenges that require additional layout techniques. There are many differences between analog and digital, and as such, the design flows and tools vary in both cases. Analog circuits are generally less complex in terms of transistor count and are designed in a manual fashion. The distinct lack of design automation means that manual design is still in widespread use today, requiring specialist knowledge that is unique to analog design. This specialist knowledge is covered in this chapter. We discussed analog design flows in Chap. 4 (Sects. 4.6 and 4.7), previously. Now we present layout techniques that accompany these analog flows, which an analog layout designer must be fully aware of. We start with an introduction to sheet resistances and wells (Sects. 6.1 and 6.2) as this knowledge is needed for the sizing and understanding of analog devices, which we then cover in Sect. 6.3. The methodology for cell generators, which produce such analog devices, is presented in Sect. 6.4. An explanation of the fundamental importance of symmetry and a treatise of resulting matching concepts (Sects. 6.5 and 6.6) conclude this chapter.

This paper proposes an approximate circuit design for 4:2 compressor which shows a significant amount of improvement in performance metrics (area, power consumption, delay, transistor count and error metrics) concerning the conventional 4:2 compressor. Subsequently, this paper also presents the hybrid architecture for the Dadda multiplier design, which enhances the efficiency of the system. This hybrid Dadda multiplier architecture is utilized in a modified median filter for image de-noising application. With the help of this technique, a significant amount of improvement is observed in the peak signal to noise ratio (PSNR) of the system. For circuit and system-level simulation is done in Cadence Virtuoso using gpdk 45nm library and MATLAB, respectively.

A multi-function fractional-order filter topology, realized through the utilization of the partial fraction expansion tool, is introduced in this paper. Thanks to the employment of the log-domain technique, the topology offers the benefit of the electronic tuning of the filter characteristics and, also, reduced MOS transistor count in comparison with the corresponding already published structures. The evaluation of the behavior of the filters has been performed using the Cadence software and MOS transistor models provided by the Austria Mikro Systeme $0.35\mu m$ CMOS process.

Crosstalk is an innovative computing technology that utilizes unwanted interferences between interconnects to compute useful logic. Engineering of coupling capacitance, circuit scheme and integration are core features. This paper presents scalability aspects of Crosstalk technology to compete/co-exist with CMOS for digital logic implementations below 10nm. Scalability is a key requirement for any emerging technologies to continue chip miniaturization. Our scalability study is with Arizona State Predictive (ASAP) 7nm PDK and considers all process variation aspects. We present primitive gate designs and their performance under variations. We discuss design constraints to accommodate worst-case variation scenarios. Finally, utilizing primitive gates, we show larger designs such as cm85a, mux, and pcle from MCNC benchmarking suits and detailed comparison with CMOS at 7nm. Our benchmarking revealed, averaging all three above mentioned circuits, 48%, 57% and 10% improvements against CMOS designs in terms of transistor count, power and performance respectively.