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Smart systems are enabled by artificial intelligence (AI), which is realized using machine learning (ML) techniques. ML algorithms are implemented in the hardware using fixedpoint, integer, and floating-point representations. The performance of hardware implementation gets impacted due to very small or large values because of their limited word size. To overcome this limitation, various floating-point representations are employed, such as IEEE754, posit, bfloat16 etc. Moreover, for the efficient implementation of ML algorithms, one of the most intuitive solutions is to use a suitable number system. As we know, multiply and add (MAC), divider and square root units are the most common building blocks of various ML algorithms. Therefore, in this paper, we present a comparative study of hardware implementations of these units based on bfloat16 and posit number representations. It is observed that posit based implementations perform 1.50x better in terms of accuracy, but consume 1.51x more hardware resources as compared to bfloat16 based realizations. Thus, as per the trade-off between accuracy and resource utilization, it can be stated that the bfloat16 number representation may be preferred over other existing number representations in the hardware implementations of ML algorithms., Inteligentní systémy jsou umožněny umělou inteligencí (AI), která je realizována pomocí technik strojového učení (ML). Algoritmy ML jsou implementovány v hardwaru s využitím reprezentace s pevnou řádovou čárkou, celými čísly a plovoucí řádovou čárkou. Výkonnost hardwarové implementace je ovlivněna velmi malými nebo velkými hodnotami kvůli jejich omezené velikosti slova. K překonání tohoto omezení se používají různé reprezentace s plovoucí desetinnou čárkou, například IEEE754, posit, bfloat16 atd. Navíc pro efektivní implementaci ML algoritmů je jedním z nejintuitivnějších řešení použití vhodné číselné soustavy. Jak víme, nejběžnějšími stavebními prvky různých ML algoritmů jsou jednotky pro násobení a sčítání (MAC), dělička a odmocnina. V tomto článku proto předkládáme srovnávací studii hardwarových implementací těchto jednotek založených na reprezentaci čísel bfloat16 a posit. Bylo zjištěno, že implementace založené na posit mají 1,50x lepší výkon z hlediska přesnosti, ale spotřebují 1,51x více hardwarových prostředků ve srovnání s realizacemi založenými na bfloat16. Z hlediska kompromisu mezi přesností a využitím zdrojů lze tedy konstatovat, že v hardwarových implementacích ML algoritmů lze upřednostnit reprezentaci čísel bfloat16 před ostatními existujícími reprezentacemi čísel.

Nowadays demand for artificial intelligence (AI) enabled mobile platforms is increasing. From healthcare services to defense and from remote to urban area, there is a huge demand of secured and power efficient devices. The performance of these platforms can be enhanced by providing an efficient compute engine. These compute engines perform a huge amount of matrix operations. The most popular choice for large matrix computation is a systolic array. In general, the systolic array performance degrades for the large input matrices, due to the trade off between resource utilization and computation delay. To address this issue, we need a systolic array with a control unit to re-configure the array according to the requirement of the computation. Computation array can be further improved by handling the negative weights and reduce the MAC operations. In this paper, we proposed a generalized bfloat16 based systolic array in which the sign of the partial sum (PS) is predicted before computation. The PS sign aids in network pruning which enhances system performance. The proposed system is implemented on a Virtex-7 FPGA board and it performs 2.21 similar to and 4.19x better in terms of area and power compared to single-precision based systolic array., V současné době roste poptávka po mobilních platformách s umělou inteligencí (AI). Od zdravotnických služeb až po obranu a od vzdálených až po městské oblasti existuje obrovská poptávka po zabezpečených a energeticky účinných zařízeních. Výkon těchto platforem lze zvýšit poskytnutím efektivního výpočetního jádra. Tyto výpočetní motory provádějí obrovské množství maticových operací. Nejoblíbenější volbou pro velké maticové výpočty je systolické pole. Obecně platí, že výkonnost systolického pole se pro velké vstupní matice zhoršuje v důsledku kompromisu mezi využitím prostředků a zpožděním výpočtu. K řešení tohoto problému potřebujeme systolické pole s řídicí jednotkou, která by změnila konfiguraci pole podle požadavku výpočtu. Výpočetní pole lze dále vylepšit zpracováním záporných vah a omezit operace MAC. V tomto článku jsme navrhli zobecněné systolické pole založené na bfloat16 , ve kterém se před výpočtem předpovídá znaménko částečného součtu (PS). Znaménko PS pomáhá při ořezávání sítě, což zvyšuje výkonnost systému. Navržený systém je implementován na desce Virtex-7 FPGA a ve srovnání se systolickým polem založeným na jedné přesnosti má výkon 2,21 podobný a 4,19x lepší z hlediska plochy a výkonu.

Base erosion and profit sharing (BEPS) explain the process when multinational enterprises take advantage of the gaps, mismatches or loopholes in the international tax regulations for artificially shifting profits to lower tax jurisdictions or no tax jurisdictions. Tax avoidance strategies were legal in most cases and overlooked until the OECD G20 BEPS project was done in 2013. Multinational companies were exploiting tax outdated taxation rules and uncoordinated with the other nations. BEPS is not exactly beneficial for all parties. Governments, citizens and businesses all bear the brunt of it. The government loses required tax revenue from the largest corporations in the world, approximately 4-10% of the global corporate tax revenues which could be allocated to infrastructure, health care facilities, education, pensions etc. The population loses out by paying higher taxes for services which could be funded through the corporates or going about without those services. Domestic or home-grown businesses find it challenging to compete with multinationals that could lower their tax by shifting profits offshore. Profit shifting behaviour of multinational enterprises is no new phenomenon. Around 135 jurisdictions working together at present in the inclusive framework on BEPS. Additional to implementation of the minimum BEPS standards, they are tackling income tax challenges emanating from the digital economy to ensure that not just digitally operating businesses, but all pay a fair share of tax returns[1]. On the tax administrations’ perspective, the goal is to minimize the cost of goods sold for imported goods and thus the import prices, resulting in higher taxable profits, as direct tax income is directly related to taxable basis, which is naturally influenced by costs incurred with imported goods. Consequently, the taxation department’s interest would be to verify whether the value declared by a resident should be decreased in order to limit the tax-deductible amo

The present investigation was aimed to isolate banana starch (BS), synthesis of banana starch tartrate (BST), characterization, and application as a novel disintegrant in telmisartan tablets. Starch tartrate was synthesized by the esterification process by the treatment of tartaric acid on the backbone of the BS. Synthesized BST was found to be fine, slightly free-flowing and crystalline powder. The synthesized BST was subjected to Scanning Electron Microscopy (SEM) and micrometric evaluation. Flow properties of BS and BST were determined as an angle of repose, bulk density, tapped density, Carr’s index, Hausner’s ratio, etc. BST exhibited good swelling properties and showed no gelling at 100°C but it was transformed into a clear solution. Fourier transform infrared spectra (FTIR) did not show the presence of any significant interaction between BST and Telmisartan(T). The direct compression technique was employed in formulating telmisartan tablets using BST sodium starch glycolate and crospovidone as a disintegrant.  Tablets were comparatively evaluated for weight variation, thickness, hardness, friability, and disintegration. The tablets formulated using BS and BST passed prescribed evaluation tests for weight variation, friability, hardness, and thickness. The tablets formulated using BST as disintegrant gave optimum disintegration compared to those tablets containing sodium starch glycolate and crospovidone sodium super disintegrants. Evaluations indicated that synthesized BST shows qualitatively and quantitatively good disintegration characteristics in comparison to super disintegrants in telmisartan tablet formulation. These results suggest that the synthesized BST could be used as a novel semi-synthetic disintegrant in dispersible tablet formulations. Keywords: Banana Starch, Banana Starch tartrate, Telmisartan, Superdisintegrant