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Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). Though the gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) interconnect delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnect layers in the BEoL (Back-end-of-line). Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of SiO2 (k= 3.9) to reduce the capacitive component in the RC delay. Low-k dielectric materials have characteristics such as low mechanical strength, hardness and adhesion, thereby making it imperative to characterize their thermo-mechanical response. Integration of Cu/low-k interconnects has become a critical reliability issue from the foundry's standpoint as well as package reliability. The thermo-mechanical stresses are induced inside the chip during various fabrication processes, field use, etc. The CTE mismatch between the various components leads to significant warpage and stresses in the metal/dielectric region of the die. In this study, a 3-D multi-level finite element (MLFE) approach has been used to examine the mechanical integrity of the Nano-scale inter-layer-dielectric (ILD) when the package is subjected to thermal shock. Since thickness of each layer in the metal/dielectric region is few orders of magnitude lower than that of the chip/substrate (at least 3 orders) it is almost impossible to analyze it at the global level. Therefore, sub-modeling technique has been leveraged to conduct a relatively accurate estimation of the mechanical behavior of the Cu/low-k region under thermal shock condition. A comparative analysis of the mechanical response of the Cu/low-k region is done for 2 cases - 1) ILD taken as linear material (commonly used industry practice to save computational time) 2) temperature dependent non-linearity of the ILD is implemented and creep and plastic response is captured. The creep model was implemented to represent its realistic mechanical behavior. This study demonstrates the variation in the thermo-mechanical response between the 2 cases thereby addressing the importance of a non-linear analysis for such systems. The developed framework is further utilized to perform a parametric analysis for the number of BEoL layers and to study the effect of underfill properties on the structural integrity of the dielectric layers.

The convergence and miniaturization of the consumer electronic products such as cell phones and digital cameras has led to the vertical integration of packages i.e., 3-D packaging. 3-D chip stacking is emerging as a powerful tool that satisfies such Integrated Circuit (IC) package requirements. 3-D technology is the trend for future electronics, especially hand-held, hence, making it an important research area. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide better inter-chip and chip-substrate electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D electronics. TSV is one of the key enabling technologies for 3-D systems. TSVs allow 3-D chips to be interconnected directly and provide high speed signal processing. Electrical interconnection and heat dissipation improves with the number of TSVs. But, there is a trade-off; silicon efficiency of a 3-D package decreases with the TSV count. There are studies for thermo-mechanical analysis of TSVs both at wafer and package level but there is limited data on the electrical aspects of TSVs, i.e., effect of TSV temperature and layout/size on the interconnect delay. In this paper, interconnect delay is determined for various TSV configurations at the package level. Interconnect delay is primarily driven by the interconnect size and temperature. The objective of this work is to determine the optimal number/size of TSVs as a function of silicon efficiency, junction temperature and the interconnect delay. Chip real estate (CRE) - actual chip area available to lay down devices, is varied from 98% to 96% with an interval of 2% (2 cases). For each CRE case, sub-cases are formulated by varying the TSV count/size (keeping the CRE constant) and chip temperature and the interconnect delay is determined and compared. It is seen that for all the TSV configurations at constant CRE, the junction temperature remains constant, however the interconnect delay varies significantly. The work provides design guidelines based on CRE, junction temperature and the interconnect delay for varied applications in the electronics industry.

As the work load on the single core processor increases, its power density and the die temperature increases as well. The increase in the die temperature results in decreased performance, reliability and increased leakage currents and cooling cost. Also, the non-uniform power distribution across the die results in hot spots. In order to decrease the work load and the cooling cost on the single core processor, multi-core processors have been implemented. Multicore Processors also known as Chip Multi Processors (CMP's). CMPs are processors which contain two or more independent cores on a chip. In CMPs, if one core reaches its critical temperature, the workload is transferred to the other. This phenomenon is termed as core hopping. Core hopping facilitates uniform distribution of the work load among the many cores and leads to improvements in the performance and reliability. The demand for greater performance in applications involving high levels of computing has resulted in many cores being put on a single chip. Every succeeding processor is predicted to hold double the number of cores than the previous one. In this study, core hopping for CMPs is analyzed and the thermal analysis of the chip with core hopping is performed using ANSYS Fluent. The hop sequence is analyzed as a function of chip temperature distribution and a numerical methodology to analyze the coupled thermal and structural integrity of the CMPs is demonstrated.

Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). While gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnects. Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of Silicon dioxide (k = 3.9) to reduce the capacitive component in the RC delay. Recent research has shown low-k materials to have characteristics such as low mechanical strength and adhesion. In this paper, thermo-mechanical analysis of a single chip flip-chip module (SCM) consisting of a die integrated with low-k dielectric medium, substrate, solder balls, and a printed circuit board (PCB) is performed. The analysis is done in two steps within the ANSYS finite element software to account for thermally induced stresses due to mismatch in thermal expansion coefficient. In the first step, the thermal analysis is carried out to derive the steady state temperature distribution within the package under the imposed power rating. In the second step, the evaluated temperature field is utilized in a coupled thermo-mechanical structural analysis. The developed framework is utilized to study the thermo-mechanical behavior of various low-k dielectrics, wherein the stresses and strain distributions within the chip region are quantified. The analysis has shown no change in the temperature distribution between the base case of Silicon dioxide (SiO2 ) and low-k materials. The maximum equivalent stress in the package, for all the four dielectric cases (SiO2 , polyimide, Hydrogen Silsesquioxane, and Black diamond) is seen in the silicon region of the die and that it does not change with the dielectric materials. However, the maximum equivalent stress in the low-k/metal layers varies with the materials but is always few orders of magnitude less than their corresponding yield strengths. Comparative analysis between Silicon dioxide (SiO2 ) and different low-k materials will help in identifying the weak spots in low-k dielectric when exposed to standard user environments.Copyright © 2011 by ASME

Neuronal differentiation involving neurite growth is dependent on environmental cues which are relayed by signalling pathways to actin cytoskeletal remodelling. C3G, the exchange factor for Rap1, functions in pathways leading to actin reorganization and filopodia formation, processes required during neurite growth. In the present study, we have analyzed the function of C3G, in regulating neuronal cell survival and plasticity. Human neuroblastoma cells, IMR-32 induced to differentiate by serum starvation or by treatment with nerve growth factor (NGF) or forskolin showed enhanced C3G protein levels. Transient over-expression of C3G stimulated neurite growth and also increased responsiveness to NGF and serum deprivation induced differentiation. C3G-induced neurite growth was dependent on both its catalytic and N-terminal regulatory domains, and on the functions of Cdc42 and Rap1. Knockdown of C3G using small hairpin RNA inhibited forskolin and NGF-induced morphological differentiation of IMR-32 cells. Forskolin-induced differentiation was dependent on catalytic activity of C3G. Forskolin and NGF treatment resulted in phosphorylation of C3G at Tyr504 predominantly in the Golgi. C3G expression induced the cell cycle inhibitor p21 and C3G knockdown enhanced cell death in response to serum starvation. These findings demonstrate a novel function for C3G in regulating survival and differentiation of human neuroblastoma cells.

Hemocyte mediated phagocytosis is one of the vital components of innate defence mechanisms in crustaceans and this phagocytic process is aided by serum agglutinins. However, literature on agglutinin mediated opsono-phagocytosis is unclear in the case of Macrobrachium rosenbergii hemocytes. Further, very few studies in the case of superoxide anion generation and none with regard to nitric oxide generation during phagocytosis exist among crustaceans. We investigated the occurrence of agglutinins in the serum and the role of serum agglutinins in mediating phagocytosis by the hemocytes. We show that the prawn serum possesses agglutinins that function as opsonins during phagocytosis of HB RBC by the hemocytes. Hemagglutination-inhibition assays revealed the specificity of serum agglutinins for N-acetylated hexoses, namely GalNAc, GlcNAc and ManNAc, with a higher affinity for ManNAc. In addition, ManNAc was able to inhibit the phagocytic response (by about 60%) of the hemocytes against serum pretreated HB RBC, wherein the serum was previously treated with ManNAc. We next investigated the ability of the hemocytes to generate superoxide anion and nitric oxide during HB RBC phagocytosis and results show generation of both these free radicals. In addition, there was an enhancement in generation (75% increase) of these free radicals during agglutinin mediated opsonophagocytosis, when compared to buffer treated targets and interestingly this enhanced generation was inhibited by ManNAc (27% for superoxide anion and 36% for nitric oxide), an inhibitory sugar for phagocytosis. Inhibition of phagocytosis induced superoxide anion generation by DPI (53%), sodium azide (56%) and tropolone (61%), reveals the possible involvement of NADPH-oxidases, peroxidases and probably phenoloxidases, respectively, in the generation of superoxide anion. Similarly, decrease in nitric oxide generation in the presence of l-NIO (47%) during phagocytosis lends support to the role of nitric oxide generation during cellular immune processes. These findings thus suggest a role for superoxide anion and nitric oxide in the innate defense mechanism, namely phagocytosis, in Macrobrachium rosenbergii.

TNFα blockade is a common treatment for rheumatoid arthritis (RA). Our hypothesis was that some of the pathological effects of TNFα involved signaling through hematopoietic TNFR1. We tested this using bone marrow transplant. The TNFR1 knockout mouse was backcrossed into the DBA background for 6 generations. DBA mice were irradiated, rescued with bone marrow derived from either DBA mice or from TNFR1-/- mice, and input into the collagen arthritis model. Surprisingly, we found that TNFR1-/-/DBA chimeras developed more intense disease as compared to controls. Increased disease was not caused by an increased immune response to collagen, insufficient backcrossing, or increased TNFα secretion. During intracellular bacterial infections, curiously, TNFα switches function from inflammation to resolution. A central aspect of this switch in function involves inhibition of the secretion of the IL-12/IL-23 cytokine family. We tested this in our system and found that long term culture of DBA/1 macrophages with TNFα resulted in the inhibition of IL-12 p40 subunit secretion and that serum IL-12 p40 subunit levels were elevated in TNFR1-/-/DBA mice at late stages of disease. These data are consistent with the concept that this switch in TNFα function also occurs in chronic inflammatory disease states such as RA. We propose that the genetic strength of this switch may correlate with response to therapy.

Low vision and blindness are important health problems that affect millions of people throughout the world. The most common and important pathologies are diabetic retinopathy, age-related macular degeneration, glaucoma as well as cataracts. The latter consists of an opacification of the lens of the eye which impedes the passage of light and represents one of the most important causes of vision loss. Among the risk factors for cataract development, there are life-style factors such as the use of tobacco, abuse of alcohol and unhealthy diet. In light of this, dietary components that possess anti-oxidant activity, such as polyphenols for instance, can be considered good candidates for human studies in the prevention and or treatment of such diseases. Among dietary components, the antioxidant capacity of certain polyphenols is well known, and these could be good candidates. In this review we focus our attention on the current scientific literature regarding to the effects of resveratrol on cataracts and other ocular diseases, along with its potential mechanism/s of action. A large number of preclinical studies support the involvement of resveratrol in clinical trials for the prevention and treatment of eye diseases induced by oxidative stress and inflammation, such as age-related cataract.

Curcumin is the yellow-colored bioactive constituent of the perennial plant, Curcuma longa L., which possesses a wide range of physiological and pharmacological properties such as antioxidant, anti-inflammatory, anticancer, neuroprotective and anti-diabetic activities. Anti-diabetic activity of curcumin may be due to its potent ability to suppress oxidative stress and inflammation. Moreover, it shows a beneficial role on the diabetesinduced endothelial dysfunction and induces a down-regulation of nuclear factor-kappa B. Curcumin possesses a protective role against advanced glycation as well as collagen crosslinking and through this way, mitigates advanced glycation end products-induced complications of diabetes. Curcumin also reduces blood glucose, and the levels of glycosylated hemoglobin in diabetic rat through the regulation of polyol pathway. It also suppresses increased bone resorption through the inhibition of osteoclastogenesis and expression of the AP-1 transcription factors, c-fos and c-jun, in diabetic animals. Overall, scientific literature shows that curcumin possesses anti-diabetic effects and mitigates diabetes complications. Here we report a systematical discussion on the beneficial role of curcumin on diabetes and its complications with emphasis on its molecular mechanisms of actions.