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Thermal oxides on 4H-SiC (0001) (Si-face) and (000-1) (C-face) grown at 1100°C were characterized by Fourier transform infrared spectroscopy attenuated total reflection method. For the films thicker than 5 nm, the structure of oxide was almost the same as that of the thermal oxide on silicon irrespective of film thickness. For the films thinner than 3 nm, structural transition regions were observed near the interface on both faces, and structural difference was clearly detected between the oxides in those transition regions on (0001) and on (000-1) faces.

International audience; In the present work, mechanical features of different thermal oxide films growing on metals have been investigated at different temperatures. An adapted model is performed to describe the stresses evolution within the oxide films. These predictions are compared with experimental results obtained by different experimental techniques. In order to obtain some accurate mechanical characteristic parameters of the system, both an asymptotic approach and an optimization procedure have been developed and presented through a general methodology. In respect to the chosen assumptions, the present model enables to give a precise mechanical description of each considered layer.© 2013 Elsevier B.V. All rights reserved.

International audience; In the present work, mechanical features are investigated in the case of ZrO2 thermal oxide films growing on a Zr alloy at the temperature of 550°C. The effects of a nanocrystallisation treatment on high temperature oxidation of a zirconium alloy are specifically studied. High temperature oxidation is performed in order to show benefits of such a nanocrystallisation on corrosion resistance and its influence on the mechanical fields. Experimental results obtained by Raman spectroscopy give the growth stress evolution in ZrO2 films. Using a modelling of the system, both asymptotic forms and an optimization procedure are developed to determine the mechanical characteristic parameters of the system. © 2012 Elsevier Ltd.

International audience; This paper presents the methodology for the design of a novel 4H-SiC JFET structure able to sustain 3.3 kV. Comparisons between simulation and haracterization res will be made. Taken into account the process limitation, we will also discuss the critical steps and their impact on the electrical haracteristics. A design methodology based on Baliga's criterion is proposed to obtain the optimal structure. A 50 nm thick thermal oxide grown above vertical channel and the use of a buried p+ layer as second gate electrode are brand new in front of what is found in literature.

Micro-Raman spectroscopy was employed to study the near-surface stress distributions and origins in Si around through silicon vias (TSVs) at both room temperature and elevated temperatures for Cu-filled and carbon nanotube (CNT)-filled TSV samples. From observations, we proved that the stresses near TSVs are mainly from two sources: (1) pre-existing stress before via filling, and (2) coefficients of thermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress is shown to dominate the compressive regime of the near-surface stress distribution around the two types of Cu-filled TSV structures in this work and in previous work, while pre-existing stress dominates the full range of the stress distribution in the CNT-filled TSV structures studied. These results show the importance of the pre-existing stress and support the use of a liner technology with lower stress introduction such as deposited oxide instead of thermal oxide. It is specifically important for CNT-filled TSVs, where the pre-existing stress is much larger than the CTE-mismatch-induced stress as observed in this work.

Removal of gold particles (40 nm and 100 nm) from fused silica and thermal oxide surfaces in dilute ammonium hydroxide solutions has been investigated. The particle removal efficiency (PRE) from fused silica surface has been found to be a strong function of ammonium hydroxide concentration and bath temperature. PRE increases from 0 to 85 % with increase in bath temperature from 30 to 80 °C for ammonium hydroxide concentration of 1 %. Addition of megasonic energy to the ammonium hydroxide bath at 30 °C has also shown to improve the PRE significantly. In the case of thermal oxide, the removal of gold particles is much easier compared to that from fused silica. Even for cleaning at 30 °C, the PRE for oxide surface increases from 10 to 90 % with increase in ammonium hydroxide concentration from 0 % to 4 %. Atomic force microscopy measurements reveal that an adhesion force of 10 mN/m exists between fused silica and gold particles in 4 % ammonium hydroxide solution as opposed to only repulsive force in the case of thermal oxide.

The effect of ammonia (NH3) post-oxidation annealing (POA) technique on the reliability of thermal oxides grown on a n-type 4H-SiC (0001) face by dry oxidation has been investigated. Comparing other POA techniques using hydrogen and nitrous oxide gases, it was indicated that the NH3 POA after dry oxidation remarkably improves the insulating properties of thermal oxides. The mode value of field-to-breakdown for thermal oxides prepared by NH3 POA was 12.1 MV/cm. The charge-to-breakdown (QBD) in the NH3 POA sample was the highest in all samples, and the QBD value at 63% cumulative failure rate was 19.1 C/cm2. In addition, the NH3 POA maintained excellent electron trapping characteristics of thermal oxides against the electron injection.

Mechanical features have been investigated in the case of α - Cr 2 O 3 thermal oxide films growing on NiCr 30 alloy in the temperature range 700–900 °C. From previous experimental results obtained by Raman spectroscopy and giving the growth stress evolution in α - Cr 2 O 3 films, and based on a modelling of the system, both asymptotic forms and an optimization procedure have been developed which give values for the mechanical characteristic parameters of the system and also its evolution with the oxidation temperature.

A theoretical study of the structural and electronic properties of the interfaces between a set of III-V compound semiconductors of technological interest and their native oxides is reported. First-principles techniques have been applied to model the reaction of oxidation of the GaAs(001)-@b2(2x4) surface and to generate a set of representative models of the atomic structure of a thermally grown GaAs/native oxide interface. The obtained models have been extended to the InAs/ and In"0"."5Ga"0"."5As/native oxide interfaces case. The impact of indium on both the structural changes occurring during the oxidation of the substrate and the resulting electronic properties has been quantified.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

In this work, the correlation between thermal oxide breakdown and dislocations in n-type 4H-SiC epitaxial wafers has been investigated. Thermal oxide was grown by oxidation in N2O at 1250°C followed by annealing in NO atmosphere. The electron beam induced current (EBIC) technique was employed to find correlations between the electrically active defects in epitaxial layers and regions where the oxide breakdowns occurred. The test measurements of leakage currents in MOS devices were performed in order to correlate the leakage currents with number of defects in the epi-layer detected by EBIC technique.

The reliability of CVD gate oxide was investigated by CCS-TDDB measurement and compared with thermally grown gate oxide. Although the QBD of thermal oxide becomes smaller for the larger oxide area, the QBD of CVD oxide is almost independent of the investigated gate oxide area. The QBD at F = 50% of CVD oxide, 3 C/cm2, is two orders of magnitude larger for the area of 1.96×10-3 cm2 at 1 mA/cm2 compared to that of thermal oxide. More than 80% of the CVD oxide breakdown occurs at the field oxide edge and more than 70% of the thermal oxide breakdown in the inner gate area. These results suggest that the lifetime of CVD oxide is hardly influenced by the quality of SiC, while the defects and/or impurities in SiC affect the lifetime of thermally grown oxide.

We report an experimental investigation of the pits formed at oxidation. The pits were formed by a long time oxidation in a dry or wet atmosphere at high temperature (~ 1200 oC). Although they were observed in (0001) face, they were not in (000-1) face. Comparing the points of oxidation pits to those of molten KOH etching pits on the same area of the substrate, we show that the oxidation pits are formed by oxidizing defects. In addition, the influence of the oxidation pits to the reliability of thermal oxide was researched.

Reliability of thermal oxides grown on n-type 4H-SiC substrates using an area-scaling rule has been investigated, and an influence of dislocation defects on the TDDB characteristics was examined. Using the area-scaling rule, tBD distributions of thermal oxides with different gate-area were converged to one distribution under the same breakdown factor. Finally, the reliability prediction method of thermal oxides on 4H-SiC eliminating the effect of dislocation defects has been established.

The effects of two types of postoxidation annealing (POA) techniques on the reliability of thermal oxides grown on a 4H–SiC(0001) wafer have been investigated. Hydrogen POA at a high temperature of 800 °C is carried out for 30 min after dry oxidation at 1200 °C and it results in an improvement of the insulating properties of thermal oxides. The mode values of the field-to-breakdown (EBD) and charge-to-breakdown (QBD) of thermal oxides prepared by high-temperature hydrogen POA are 10.6 MV/cm and 0.39 C/cm2, respectively. On the other hand, pyrogenic reoxidation annealing (ROA) with a water vapor content above 25% at 950 °C for 180 min adversely affects the reliability of thermal oxides. Also, it is found that the reliability of thermal oxides on a 4H–SiC wafer prepared by pyrogenic ROA degrades with an increase in water vapor content in wet ambient.

A novel x-axis tuning fork gyroscope with “8 vertical springs-proofmass” structure is presented. Wafer-thick proofmasses are made out of (111) silicon with bulk micromachining processes to achieve lower thermo-mechanical noise. Each proofmass is supported by 8 vertical springs, which are symmetrically distributed around the proofmass. The dimensions of 8 vertical springs are precisely confined by thermal oxide protected sidewalls and the extreme slowly etched (111)-planes in KOH etching. A mode mismatch of less than 30 Hz is achieved before tuning. Initial test shows a sensitivity of 0.15 mV/(deg/s) and a rate resolution around 0.1 deg/s under atmosphere pressure.

The physical and electrical properties of Ge/GeO2/high-κ gate stacks, where the GeO2 interlayer is thermally grown in molecular oxygen, are investigated. The high-κ layer (ZrO2, HfO2 or Al2O3) is deposited in-situ on the GeO2 interlayer by atomic layer deposition. Detailed analysis of the capacitance-voltage and conductance-frequency characteristics of these devices provides evidence for the efficient passivation of the (100)Ge surface by its thermal oxide layer. A larger flat-band voltage hysteresis is observed in HfO2-based gate stacks, as compared to Al2O3 gate stacks, which is possibly related to the more pronounced intermixing observed between the HfO2 and GeO2.

Even though the MOS technology was developed originally on the (0 0 1)-Si surface, some studies have shown that several MOS parameters can be optimized using other silicon orientations [1-3]. (1 1 4) and (5 5 12) Si surfaces presents a periodical surface roughness that may have technological applications [4]; however, the oxide grown on these surface orientations has not been studied. In this work we investigate the behavior of the oxide thickness in high index Si and compare it to oxides grown on standard surface orientations.

Germanium possesses higher bulk mobilities than silicon and was used for the first transistors. However, by the 1960s its use was largely supplanted with Si due largely to Si's high quality thermal oxide. Today, with the 45 nm technology node in production, high k dielectrics are beginning to replace SiO2 in the gate, and as such, one of the key reasons for using Si is no longer as relevant. This, combined with performance concerns for Si based devices for and beyond the 22 nm node has made Ge a worthy area for research for high performance devices. In this paper, we give an overview of some of the major issues for Ge MOSFETs, illustrating recent progress using data from IMEC. Key results include a factor of 10 reduction in threading dislocations for epi Ge on Si by the use of an ~850{degree sign}C anneal, the first successful use of As halo implants, progress on optimization of activation anneals, the use of a thin epitaxial Si passivation and its impact on threshold voltage, a 2-step anneal NiGe process flow to drastically reduce defects, and the importance of a hydrogen anneal following metallization.

Over the last years many new materials have been introduced in advanced CMOS processes in order to continue the scaling and increase the device performance. Much work was performed to introduce deposited high-k gate dielectrics as a replacement for the thermally grown SiO2 to reduce the gate leakage. This is a major challenge since the special properties of the Si/SiO2 system has been the major key to the success of the MOS technology. However, the introduction of deposited high-k dielectrics also provides exciting opportunities for further performance gains since it allows the use of channel materials that have a very high intrinsic mobility but do not form a stable high-quality thermal oxide. In this presentation results will be shown on how these high-mobility materials can be introduced on a Si-wafer platform for use in future CMOS applications. The progress on surface passivation, high-k deposition and the performance gains that can be expected from short channel devices on these new materials will also be discussed.

4H-SiC MOS capacitors were used to characterize the effect of reactive-ion etching of the SiC surface on the electrical properties of N2O-grown thermal oxides. The oxide breakdown field reduces from 9.5 MV/cm with wet etching to saturate at 9.0 MV/cm with 30% reactive-ion over-etching. Additionally, the conduction-band offset barrier height, φB, progressively decreases from 2.51 eV with wet etching to 2.46 eV with 45% reactive-ion over-etching.

Non-contact corona-voltage metrology is utilized to characterize as-grown thermal oxide films on 4H SiC substrates. Contact potential difference mapping is coupled with incremental application of corona charge to provide whole-wafer images of process related effects and multiplepoint capacitance-voltage characteristics respectively. Correspondence between wafer VCPD images and process details is suggested along with examples of fast electrical dielectric thickness determination and non-contact C-V characteristic acquisition.

Electrochemical oxidation of diethylenetriamine (DETA) charged with 0.1 M LiSO3CF3, leads to a polymeric coating (polyethyleneimine film: PEI) on the porous silicon (PS) surface. The obtained passivated electrode is characterized through IRTF spectrometry and through C(V) curves on PS/PEI structures showing good insulating properties of the PEI film. The passivated electrode presents a linear pH sensitivity close to 62 mV per pH unit. Such sensitivity is higher compared to flat PEI passivated silicon electrode. The results were fitted with the generalized site-binding theory and the following parameters were found: the surface site density Ns was found to be equal to 3.6 × 1016 cm− 2 and pKH (KH acido-basic constant of the amino group) is − 5.54.

In this work, we present results on the study of bonding and concentration of carbon in 4H-SiC MOS structure by x-ray photoelectron spectroscopy (XPS). The XPS spectra were fitted by several Gaussian lineshape functions. It is found that the so-called carbon clusters (C-C bonds) appear at the interface of SiO2/SiC, but are not seen in the oxide bulk. However, there are still some SiOxCy and Si-C bonds inside the oxide and the integrated area ratio of SiOxCy/Si-C bonds increases when further away from the SiO2/SiC interface. These observations can be interpreted in terms of the dynamic oxidation process that transforms Si-C bonds into SiOxCy bonds, which are then further oxidized to form SiO2 bonds.

The Ge depth profile and generation of dislocations associated with oxidation of SiGe-on-insulator (SGOI) substrates are examined from the viewpoint of the temperature dependence. It is found that Ge profiles in SGOI layers after oxidation are strongly dependent on the oxidation temperature. This fact is explained by the competitive process between the accumulation of Ge atoms at the SiGe/thermal oxide interface, determined by the oxidation rate, and Ge diffusion toward substrates during oxidation of SGOI substrates. While the abrupt Ge profile obtained by low-temperature oxidation causes the generation of dislocations, SGOI layers with high Ge content and no dislocations can be achieved by high-temperature oxidation.

The kinetics and mechanism of probe-induced oxide growth on an octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) passivated native-SiO2/Si surface have been investigated using atomic force microscopy (AFM). It was found that oxidation strongly depends on tip polarity and the local chemistry of OTS molecules. At negative tip voltage, oxide grows and the oxidation involves a decomposition and depletion of OTS SAM. While under positive tip bias, OTS molecules are partially degraded. The dielectrical properties of the oxide were characterized by I–V measurements using current sensing AFM. The barrier height of AFM grown oxide, in comparison with thermal oxide and OTS SAM, was determined. Current spikes relating to the release of single charge were also observed on the I–V curves of AFM oxide.

The instantaneous switch-off of the gas precursors during the ramp-down cycle in a spike ramp process is demonstrated to be an effective method to enhance the reliability of rapid thermal oxide. Due to the slow ramp-down rate (60/spl deg/C-90/spl deg/C/s) of a rapid thermal process, the oxidation during the slow ramp-down cycle may produce the inferior oxide, especially for ultrathin oxide. To avoid the oxidation in the slow ramp-down cycle, the oxidation precursor (oxygen) is switched off during the ramp-down cycle. The reliability of resulting oxide without oxidation during the ramp-down cycle is enhanced as compared with the conventional oxide, which is still oxidized during the ramp-down cycle.

This brief proposes possible a replacement of shallow p-n junction with insulated shallow extension (ISE) structure for bulk MOSFET. The shallow extension is defined by the sidewall thermal oxide rather than the implanted p-n junction. With this insulator for extension and main junction, a heavier halo doping concentration can be used. Thus, the threshold-voltage roll-off and the junction leakage current can be minimized simultaneously. This structure can be a good alternative for junction structures in sub-100-nm regimes.

The inverted blister test was used to study the adhesion of chromium-rich oxide scales thermally grown on several ferritic stainless steels. With this technique, a quantitative determination of the adhesion energy of the oxide on its substrate was possible. The adhesion energy is found to vary between 3 and 170 J m−2 depending on the specimens. It appears that the parameters influencing adhesion are oxide thickness and the nature of the minor alloying elements present in the alloy. The microstructural observation of both sides of the oxide/alloy interface after debonding provides important information on adhesion and spallation.

Most recently low-dose (4E17 ions/cm2) SIMOX technology has been developed in order to restrain the dislocation density and the production cost. However, in- and out-diffusion of oxygen and internal oxidation (ITOX) phenomena have never been understood during high-temperature annealing process as yet. In this study, we use the sample, which was implanted 18 O + with the dose of 4E17 ions/cm2 into silicon substrate and then non-oxidizing anneal was done at around 1300 °C. As the results, it was proven that the diffusion of oxygen into thermal oxide layer above 1300 °C was not in agreement with the Deal–Grove theory. The mechanism of oxygen in- and out-diffusion in SIMOX wafer is discussed.

Secondary ion mass spectrometry analysis of ultra-shallow (sub-200 eV) B implants is complicated by the presence of native oxide on the surface of Si. Knowledge of the type of oxide present on the surface as well as accurate oxide thickness is very important for correct data reduction in extra-low energy depth profiling. Sputter rate (SR) variation approach based on the accurate SR measurement in Si and SiO2 can be successfully applied to B implants done through thermal oxides of various thicknesses. Lowest profiling energy should be used to achieve the least profile distortion in the case of de-channeled B implants: the rule of half of the implant energy used for profiling energy is confirmed. Profiling energy that is equal to the implant energy can be used if implantation is done through native oxide or into the stripped Si. If no thermal oxide is present on the surface, the most consistent result will be obtained when implants are done into the pre-stripped Si thus eliminating uncontrollable and variable native oxide-related issues. Copyright © 2012 John Wiley & Sons, Ltd.

Thermal oxide covered silicon wafers were polished with slurries containing either nano-sized ceria (CeO2) or newly prepared uniform colloidal silica particles coated with ceria. The polish rate of the latter was significantly higher than that of pure ceria. The experiments were carried out using different concentrations of the abrasives at pH 4 and 10. Little effect on the polishing rates was noted when the conditions of the slurries were varied, which was explained by the compensation of two opposite polishing mechanisms.

A complete optical characterization in the visible region of thin copper oxide films has been performed by ellipsometry. Copper oxide films of various thicknesses were grown on thick copper films by low temperature thermal oxidation at 125 °C in air for different time intervals. The thickness and optical constants of the copper oxide films were determined in the visible region by ellipsometric measurements. It was found that a linear time law is valid for the oxide growth in air at 125 °C.

The behavior of charge in a buried oxide of the silicon-on-insulator structures obtained using the Dele-Cut technology was studied by keeping the structures under a voltage with an electric-field strength of 2–5.5 MV/cm. A mobile positive charge drifting under the effect of applied voltage was detected in the oxide. The expected charge accumulation in the oxide was not detected. It may be assumed that both of the observed effects are caused by the interaction of residual hydrogen, which is present in the oxide during the preparation of the structures, with traps in the thermal oxide. As a result, the traps become passivated in the buried insulator of the structure; in addition, the charge, which is mobile at room temperature, is introduced into the insulator.

International audience; The presence of residual stresses in thermal oxide layers has been recognized for a long time. In the present work, the mechanical fields for chromia oxide are determined either by XRD or Raman spectroscopy. In addition, the microstructure of the chromia films is investigated ant its influence on the evolution of the stress release processes is analyzed. © (2014) Trans Tech Publications, Switzerland.

Recently, interest has risen in silicidation through oxide (SiTOx). For CoSi2, it has been reported that the presence of a thin, chemically grown oxide results in the formation of epitaxial CoSi2. The method is known as oxide mediated epitaxy (OME). In this paper, results are reported on CoSi2 formation in the Co/SiO2/Si, Ti/Co/SiO2/Si and Co/Ti/SiO2/Si systems for both chemically and thermally grown oxides. Chemically grown oxides were formed in HCl, NH4OH and HNO3-based solutions. The influence of the type and thickness of the oxide on the silicidation reaction is discussed. In the presence of a thin HCl oxide, the reaction proceeds in a layerwise fashion. For thicker oxides (both HNO3 and thermal oxide), the reaction is initiated at weak spots in the oxide layer. We have observed that Ti can reduce the interfacial oxide, especially if the Ti is deposited directly on top of the oxide (Co/Ti/SiO2/Si structure). This is the case both for chemically and thermally grown oxides, although the thicker the oxide, the thicker Ti layers are needed. In the presence of a Ti capping layer (Ti/Co/SiO2/Si), Ti diffuses through the unreacted Co towards the SiO2. In case of a thin oxide, the supply of Ti that can reach the oxide by fast grain boundary diffusion is sufficient for reduction of the SiO2. In case of a thicker, thermal oxide, Co3Ti is formed.

The results of investigating the morphology and protective properties of surface layers obtained on chromium steel Х18Н10Т by oxidizing in air at a temperature of 140 to 950°C are considered. After a special digital treatment, the scanned optical images of a small surface area probed allow one to introduce and determine those parameters of the morphological nonuniformity of the thermal oxide layer which affect its protective ability. Corrosion tests of oxidized specimens confirmed the applicability of the scanner morphological control to predicting the protective properties of thermal coatings against pit corrosion in chloride-containing electrolyte solutions.