226 results on '"TAOUIL, MOTTAQIALLAH"'
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52. Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks
53. Defect and Fault Modeling Framework for STT-MRAM Testing
54. Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
55. Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
56. Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM
57. Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
58. GRINCH: A Cache Attack against GIFT Lightweight Cipher
59. Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
60. RNN-Based Detection of Fault Attacks on RSA
61. Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs
62. G-PUF: An Intrinsic PUF Based on GPU Error Signatures
63. Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level
64. Testing Scouting Logic-Based Computation-in-Memory Architectures
65. Modeling Static Noise Margin for FinFET based SRAM PUFs
66. LiD-CAT: A Lightweight Detector for Cache ATtacks
67. Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures
68. eSRAM Reliability: Why is it still not optimally solved?
69. A Security Verification Template to Assess Cache Architecture Vulnerabilities
70. Impact of Magnetic Coupling and Density on STT-MRAM Performance
71. A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs
72. Mitigation of Sense Amplifier Degradation Using Skewed Design
73. Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects
74. A Classification of Memory-Centric Computing
75. The Power of Computation-in-Memory Based on Memristive Devices
76. Public-Key Based Authentication Architecture for IoT Devices Using PUF
77. Testing Computation-in-Memory Architectures Based on Emerging Memories
78. Reliability Modeling and Mitigation for Embedded Memories
79. Device-Aware Test: A New Test Approach Towards DPPB Level
80. Cost modeling for 2.5D and 3D stacked ICs
81. A computation-in-memory accelerator based on resistive devices
82. Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme
83. Challenges and Solutions in Emerging Memory Testing
84. Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM
85. Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing
86. DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs
87. Hardware-Based Aging Mitigation Scheme for Memory Address Decoder
88. Methodology for Application-Dependent Degradation Analysis of Memory Timing
89. Applications of Computation-In-Memory Architectures based on Memristive Devices
90. Time-division Multiplexing Automata Processor
91. System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation
92. Cost Modeling for 2.5D and 3D Stacked ICs
93. Enhancing PUF Based Challenge–Response Sets by Exploiting Various Background Noise Configurations
94. Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era
95. Testing Resistive Memories: Where are We and What is Missing?
96. Electrical Modeling of STT-MRAM Defects
97. Memory and Communication Profiling for Accelerator-Based Platforms
98. Device aging: A reliability and security concern
99. Ionizing radiation modeling in DRAM transistors
100. Degradation analysis of high performance 14nm FinFET SRAM
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