51. An LPC cepstrum processor for speech recognition
- Author
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In-Chul Hwang, Sung-Nam Kim, Young-Woo Kim, and Soo-Won Kim
- Subjects
Gate array ,24-bit ,Computer science ,Pipeline (computing) ,Speech recognition ,Clock rate ,Cepstrum ,Frame (networking) ,Real-time computing ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Linear predictive coding ,Auxiliary memory - Abstract
An LPC cepstrum processor for speech recognition is implemented on CMOS gate array. The processor that we designed contains a 24 bit floating-point MAC unit, which computes a correlation rapidly, the majority of operations in the algorithm. This processor has 22 register files to store temporary variables, which enable one to reduce access to external memory. For the purpose of fast operations, the floating-point MAC consists of a pipeline structure with 3 stages and uses a branched postnormalization scheme proposed in this paper. Experimental results show that it takes approximately 266 /spl mu/s to process a frame of 20 ms at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of transistors is 55,520.
- Published
- 2002
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