439 results on '"Shi-Yu Huang"'
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52. Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects.
53. Monitoring the delay of long interconnects via distributed TDC.
54. Cell-based programmable phase shifter design for pulsed radar SoC.
55. Temperature-aware online testing of power-delivery TSVs.
56. Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.
57. Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.
58. Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.
59. On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs.
60. Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction
61. A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL.
62. The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop.
63. General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.
64. Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.
65. The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems.
66. At-speed BIST for interposer wires supporting on-the-spot diagnosis.
67. Delay testing and characterization of post-bond interposer wires in 2.5-D ICs.
68. Mid-bond Interposer Wire Test.
69. Worst-case IR-drop monitoring with 1GHz sampling rate.
70. A unified method for parametric fault characterization of post-bond TSVs.
71. Programmable Leakage Test and Binning for TSVs.
72. Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.
73. Small delay testing for TSVs in 3-D ICs.
74. Natural Berberine-derived Azolyl Ethanols as New Structural Antibacterial Agents against Drug-Resistant Escherichia coli
75. Test strategies for the clock and power distribution networks in a multi-die IC.
76. A fully cell-based design for timing measurement of memory.
77. Black-box leakage power modeling for cell library and SRAM compiler.
78. A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
79. PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs.
80. AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
81. Power aware SID-based simulator for embedded multicore DSP subsystems.
82. PAC duo system power estimation at ESL.
83. Performance Characterization of TSV in 3D IC via Sensitivity Analysis.
84. QC-Fill: An X-Fill method for quick-and-cool scan test.
85. PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning.
86. Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs.
87. Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.
88. Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration.
89. Two-Gear Low-Power Scan Test.
90. Paeoniflorin and albiflorin regulate P-gp-mediated aconitine and hypaconitine transport through an Madin Darby canine kidney-multi drug resistance protein 1 cell model
91. RT-level vector selection for realistic peak power simulation.
92. Built-In Speed Grading with a Process-Tolerant ADPLL.
93. A network security processor design based on an integrated SOC design and test platform.
94. A low-power SRAM design using quiet-bitline architecture.
95. Quick Scan Chain Diagnosis Using Signal Profiling.
96. Power estimation starategies for a low-power security processor.
97. A Fading Algorithm For Sequential Fault Diagnosis.
98. Cell-based delay locked loop compiler.
99. Combinational circuit fault diagnosis using logic emulation.
100. Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults.
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