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This paper presents an analysis of optical properties of cubic titanium dioxide (TiO2) using Orthogonalized Linear Combinations of Atomic Orbitals (OLCAO) basis set under the framework of Density Functional Theory (DFT). Many optical properties such as refractive index, extinction coefficient, reflectivity, absorption coefficient, photoconductivity, and loss coefficient have been studied and analyzed thoroughly. From the analysis of optical properties, it is seen that cubic TiO2 supports interband transition between states. The reflectivity of pyrite structure TiO2 lies within IR- visible- UV region due to which it qualifies for coating industry. Furthermore, the results are compared with previous theoretical as well as with experimental results. It is found that DFT based simulation produces results which are the close approximation to experimental results.

Structural, electronic, and optical properties of ferroelectric material, Lithium niobate (LiNbO3) are explored and studied using two different techniques namely, OLCAO-MGGA-TB09+c and OLCAO-GGA-PBES + U under the framework of density functional theory (DFT). The electronic properties such as band diagram, the effective mass of charge carriers, the total density of state (TDOS), and partial density of state (PDOS) are investigated in depth. Band gap values obtained using MGGA-TB09+c is 3.79 eV whereas, it is 3.78 eV for GGA-PBES + U. Furthermore, several optical properties such as dielectric constant, reflectivity, refractive index, optical conductivity, loss function, and absorption coefficient have also been extracted. It is seen that the results so obtained are consistent with experimental data which shows the soundness of our calculations. From the statistical analysis, it is found that both the techniques provide very good results on electronic and optical properties of LiNbO3 compared to existing computational work as both give an approximation of experimental data. The methods presented here will be useful for researchers to get accurate results on structural, electronic, and optical properties of other materials.

In this paper, the effect of pressure on various properties of brookite and rutile TiO2 has been investigated along with a phase transition study. It is seen that brookite gets transformed to rutile TiO2 at 5 GPa pressure. The band gap of brookite and rutile TiO2 are direct in nature with values of 3.41 eV and 2.98 eV. Pressure-dependence of the Elastic compliance coefficients, elastic stiffness coefficients, bulk modulus, shear modulus, Young modulus, Poisson's ratio, B/G ratio, Vickers hardness, Lame constant has been calculated at 0, 3, 5 GPa pressures for brookite TiO2 and at 0,5,10,15, and 20 GPa pressures for rutile TiO2. The shear anisotropy factors (A100, A010, and A001) along {100},{010}, and {001} planes have been estimated at different pressure for brookite TiO2 as well as the shear anisotropic factors along {100} and {001} shear planes is estimated for rutile TiO2. Moreover, anisotropy factors (AB),(AG), and (AU) have been estimated at different pressure for brookite TiO2 and rutile TiO2. Furthermore, the dielectric constant is determined to investigate other optical properties for both the structures at different pressures. A pretty good agreement has been obtained between our findings and experimental data.

In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF performances of the proposed device. Through TCAD simulations, it has been shown that donor and acceptor ITCs existing at the interface between drain region and dielectric pocket (i.e. Si/DP) have significant impact on the parameters such as OFF-state current, ambipolar conduction, parasitic capacitances, output resistance, and cut-off frequency of DP SOI-TFET. Furthermore, a comparative analysis has been carried out between the conventional and DP SOI-TFET under influence of traps, and it has been found that performances of the proposed device are further improved by the existence of acceptor ITCs at higher negatively biased gate. Even though, the existence of donor ITCs at Si/DP interface has been found degrading the performances of the proposed DP SOI-TFET, simulation results suggest that dc and analog/HF figure of merits are still superior in the proposed device as compared to those in the conventional SOI-TFET.

Multilevel thresholding is one of the most important areas in the field of image segmentation. However, the computational complexity of multilevel thresholding increases exponentially with the increasing number of thresholds. To overcome this drawback, a new approach of multilevel thresholding based on Grey Wolf Optimizer (GWO) is proposed in this paper. GWO is inspired from the social and hunting behaviour of the grey wolves. This metaheuristic algorithm is applied to multilevel thresholding problem using Kapur's entropy and Otsu's between class variance functions. The proposed method is tested on a set of standard test images. The performances of the proposed method are then compared with improved versions of PSO (Particle Swarm Optimization) and BFO (Bacterial Foraging Optimization) based multilevel thresholding methods. The quality of the segmented images is computed using Mean Structural SIMilarity (MSSIM) index. Experimental results suggest that the proposed method is more stable and yields solutions of higher quality than PSO and BFO based methods. Moreover, the proposed method is found to be faster than BFO but slower than the PSO based method.

A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages.

In literature, oriented filters are used for low-level vision tasks. In this paper, we propose use of steerable Gaussian filter in image quality assessment. Human visual system is more sensitive to multidirectional edges present in natural images. The most degradation in image quality is caused due to its edges. In this work, an edge based metric termed as steerable Gaussian filtering (SGF) quality index is proposed as objective measure for image quality assessment. The performance of the proposed technique is evaluated over multiple databases. The experimental result shows that proposed method is more reliable and outperform the conventional image quality assessment method.

This paper investigates on the structural stability and electronic properties of titanium dioxide (TiO2) nanowires of different novel shapes using first- principle based density functional approach. Out of linear, ladder, saw tooth, square, triangular, hexagonal, and octahedron shaped atomic configuration, the ladder shape atomic configuration is energetically most stable. After computation of lattice parameters as well as various mechanical properties of nanowire TiO2, it is seen that highest bulk moduli is obtained for triangular TiO2 nanowire which shows the highest mechanical strength for the structure whereas hexagonal configuration has lowest Bulk moduli which shows the lowest mechanical strength for the structure. Analysis of various electronic properties show that different configurations of TiO2 nanowires can have different utility as solid state materials.

In this work we have studied the impact of variation of k dielectric constant on Silicon Nano Tube FET for low power and high speed applications. The Silicon Nano tubular structure offers better immunity towards short channel effects (SCE‘s) because of the better control of channel region due to the double gate all around. By cause of gate engineered structure high K value structures possess high value of electron velocity as compare to low k dielectric structure, which helps in improving the efficiency of carrier transport. In this work we have considered a Silicon Di-oxide(SiO 2 ), Silicon Nitride(Si 3 N 4 ), Hafnium Oxide(HfO 2 ), Hafnium Silicate (HfSiO 4 ), Tin oxide (SnO 2 ) and Titanium Oxide (TO 2 ) as a gate dielectric. It has been found that when the high k is replaced with SiO 2 then the switching performance of the device is enhanced which makes it suitable for the SOC applications. From the analysis it has been found that HFO 2 in SINTFET will be a superior alternative for future tubular FET devices

In this brief, the reliability of SOI-TFET with dielectric pocket (DP SOI-TFET) has been investigated in the presence of fixed trap charges at the interface between dielectric pocket (DP) and drain region. During numerical simulation, both types of trap charges like donor (i.e. positive) and acceptor (i.e. negative) have been considered to analyse the impact on the performance of SOI-TFET having DP in drain region used for reduction of ambipolar conduction. We have compared the device performances such as ambipolar conduction, and OFF-state current of conventional SOI-TFET with both low and high- $\pmb{k}$ DP SOI-TFET in the presence of interface trap charges (ITCs). It has been found that SOI-TFET is more immune to interface trap charges when high- $\pmb{k}$ material is used as DP compared to low- $\pmb{k}$ . Since, high- $\pmb{k}$ provides even more reduction in ambipolar conduction as compared to low- $\pmb{k}$ , it can be preferred to be used a dielectric pocket in SOI-TFET.

This paper investigates on the structural stability and electronic properties of titanium dioxide (TiO 2 ) nanowires of different shapes using first-principle based density functional approach. Out of linear, ladder, and saw tooth shaped atomic configuration, the ladder shape atomic configuration is energetically most stable. After computation of lattice parameters as well as various mechanical properties of nanowire TiO 2 , it is seen that highest bulk moduli is obtained for linear TiO 2 nanowire which shows the highest mechanical strength for the structure whereas ladder configuration has lowest bulk moduli which shows the lowest mechanical strength for the structure. Analysis of various electronic properties show that different configurations of TiO 2 nanowires can have different utility as solid state materials.

In this brief, we have investigated a novel structure of double-gate TFET with extended back gate (EBG-DG-TFET) to improve the device performances. In the proposed device, the extended back gate is found to create an overlapped region with both source side as well as drain side which improves the overall performances of DG-TFET. Through two-dimensional numerical simulations, it is demonstrated that the overlapped gate-source region enhances the ON-state current due to reduction in the barrier width at input tunneling interface between source and channel regions, thus improving the current switching ratio of DG-TFET. In addition to improvement in ON-state current, the overlapped gate-source region also improves the subthreshold slope which is found to be lower than that of the conventional DG-TFET. Furthermore, the overlapped gate-drain region is found to remove the ambipolar conduction in DG-TFET when gate is biased with opposite polarity than drain terminal.

Metal oxide semiconductor field-effect transistor (MOSFET) is the main building block in low-power and high-performance very large-scale integration (VLSI) chips for the last few decades. Device scaling is the guiding force toward technological advancements, which allows more devices to be integrated on a single die thereby allowing greater functionality per chip. The ultimate goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consuming low power. We see an exponential growth in device complexity in today's nanoscaled chip. However, device scaling to deep nanometer regime leads to exponential increase in leakage current and excessive heat generation. Moreover, process variability has caused a serious limitation to further scaling. It is believed that with a mix of chemistry, physics, and engineering, nanoelectronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nanotube (CNT) and nanowire (NW)-based FETs (CNTFET and NWFET) have been analyzed and characterized in the laboratory and also been demonstrated as prototypes. This work first presents, a detailed explanation on chemical bonding and crystalline structures of these new devices and then an extensive simulation and analysis of CNTFET and NWFET devices and compared the results with conventional MOSFET and double gate MOSFET. From this study, it reveals that these new devices have got some excellent properties and favorable characteristics, which will definitely lead the future semiconductor devices in the post-silicon era.

A multiplier circuit is one of the most important functional blocks of many nano-electronic, control and automation applications. In this work, an energy-efficient multiplier is reported based on a 3:2 compressor. The multiplier has been designed in three different parts. In the first part, a partial product (PP) generator is used. In the second part, the partial products are reduced which is termed as PPP (partial product processing). Whereas in the third step final addition is performed. PPs are produced by using AND gates. The PPP is designed in two-phase. In the first phase, the Wallace tree logarithm has been used to reduce the PPs. Whereas, in the second phase the PPs are reduced by using energy-efficient half adder and 3:2 compressor. At last, in the third step, by using a carry-save adder final addition has been computed. The performance analysis of the designed multiplier is evaluated and compared with other multiplier circuits. The multiplier shows performance improvements by 20.55%-46% for the power supply variation from 1.2 V to 0.6 V. All the simulations and analyses have been carried out by using the Synopsys EDA tool.

Leakage power dissipation is a serious concern in deep nanometer devices. Low power design methodology is often adopted in VLSI circuits and systems to minimize power; however, this is achieved at the cost of performance penalty. In this paper, we first review the existing circuit techniques for leakage minimization. A new circuit technique is then proposed which is designed intelligently by mixing a pair of dynamic threshold sleep transistors and a pair of helper transistors. The performance of the proposed technique is investigated in terms of area, power, delay and power---delay product. Extensive SPICE simulation with 32 nm process technology shows a significant reduction in power, delay and power---delay product.

A dynamic threshold voltage control strategy is presented in this paper to minimize leakage power while enhancing the speed and stability. The threshold voltage of driver and access transistor are tuned dynamically through a novel body-bias controller circuit. The word line signal level controls the action of the proposed body-bias controller. In order to reduce subthreshold leakage current, the threshold voltage of NMOS access and driver transistors are adjusted to a high value by applying a reverse body-bias. On the other hand, forward body-bias lowers the threshold voltage of NMOS access transistor thereby enabling faster read and writes operation. Simulation results shows that the proposed design is much better than conventional and other SRAM cells such as, NC SRAM, PP SRAM, WRE8T. The amount of leakage power reduction is as high as 41.071 % over conventional 6T SRAM cell when tested on (8 × 16) SRAM array. Whereas, the improvement in read and write delay is 30 and 15.81 % respectively.

Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage power especially during standby mode. Here in this paper, at first we review some of the existing techniques for leakage minimization and pointed out their merits and shortcomings. We then propose a novel transistor level approach called leakage control NMOS transistor (LCNT) for leakage minimization. The proposed technique inserts two leakage control transistors (all N-type) within a standard CMOS logic circuit. The gate terminal of the leakage control transistors are connected with the drain of the pull-up transistors. Performance of the proposed technique is investigated in terms of area, power, delay, and power-delay product applying on some basic gates and benchmark circuits. The performance metrics of the proposed LCNT are then compared with other existing techniques. Extensive SPICE simulations were carried out using 32 nm predictive technology model. Simulation results indicate that the proposed technique is quite efficient in minimizing the leakage power which is found out to be 48.4 %.

Ever increasing demand for portable and battery-operated systems has led to aggressive scaling. While technology scaling facilitates faster and high-performance devices, at the same time it causes excessive power dissipation especially the leakage. Leakage power dissipation is now a dominating component of total power consumption in today's high-performance chip. So there is a tremendous need to limit the power dissipation in high-density chips, which has initiated many innovative techniques to develop in the design of low power circuits and systems. Nano-scaled very large-scale integration (VLSI) chips have ultra-thin gate oxide, very low threshold voltage, and have short channels. Therefore, leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. In this paper, we present a general review of the state-of-the-art circuit level leakage minimization techniques since 1995. It also conceptually classifies the different techniques for leakage minimization. Furt...

In this paper, a detailed study and analysis on the electronic and optical properties of anatase, rutile and brookite titanium dioxide (TiO2) which are the naturally occurring phases of TiO2 have been carried out. We have obtained these properties using the self-consistent orthogonalized linear combination of atomic orbitals with meta-generalized gradient approximation (MGGA) and Tran and Blaha (TBO9) as exchange–correlation under the framework of density functional theory. Obtained results on band gap value (E g), dielectric constant and refractive index as calculated by considering the optimal value of c (system-dependent parameter) have been analyzed statistically and are found to be much closer to the experimental values and are better than the other approaches published in the literature. It is seen that optical absorption for all the three phases of TiO2 occurs in UV region of EM spectrum. Using statistical analysis in correlation with other effective methods such as mBJ, GGA + U, GGA + Ud + Up, LSD + U, GW and HSE06 functional, it is found that MGGA-TB09 gives a better description of electronic structure and optical properties with less computation time. This work provides good understanding of electronic and optical properties of TiO2, stems a foundation for its possible applications in photo catalytic activities of dye sensitized solar cells.

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

In this paper we studied the impact of variation of dielectric constant and alternation of gate work function on silicon nanotube FET for low power and high speed switching applications. The silicon nano tubular structure offers better immunity towards short channel effects. Due to the gate engineered structure high K value structures possess high value of electron velocity. In this paper we have considered a silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), hafnium silicate (HfSiO4), tin oxide (SnO2) and titanium oxide (TO2) as a gate dielectric. Further by tuning the gate work function of the device we can able to achieve multiple threshold voltages and optimise the performance of the device. In this paper we discuss the impact of work function variation on ON-current, OFF-current and threshold voltage. From the analysis it has been found that HfO2 in SINTFET will be a superior alternative for future tubular FET devices and by tuning the gate work function nearby to 4.8 eV the silicon nano tube shows optimised better performance among all other values.

In this paper, a novel structure of double-gate TFET (DG-TFET) is proposed with graded-channel and dual-metal configuration showing huge reduction in ambipolar conduction. Using TCAD simulations, it is shown that a heavily-doped channel region along with gate metal with lower work-function adjacent to drain region modulates the alignment of band energy at output tunnelling interface in such a manner that an increment in the tunnelling width is occurred. Eventually, a huge reduction in ambipolar conduction is observed in the proposed device. However, performance of the proposed device is shown to be degraded if length of the channel region adjacent to drain is increased beyond a certain value. Through simulations, length-ratio and doping concentration of two channel regions is optimized to achieve the minimum ambipolar current. Additionally, it is demonstrated that ambipolar conduction is completely eliminated in the proposed device even if drain region is doped as heavily as source region.

An effective way to get multiple threshold voltage modulation scheme in Silicon nano tube FET combining unbalanced halo doping is proposed and verified by 3D TCAD Simulator. The typical choice to accomplish multiple threshold voltages is by choosing the appropriate gate work-function for each device. But this results in higher process complexity. In this report we demonstrate the multiple V t solution for Si-NTFET at 14 nm technology node. Using HALO at source side, the simulated DIBL (Drain induced Barrier Lowering)characteristics shows notable improvement.

In the presented work, a Tunnel FET device with dual-metal graded-channel structure is proposed and investigated showing the influence of energy band modulation at channel-drain interface on the ambipolar conduction. Through two-dimensional numerical simulations, it is demonstrated that a heavily-doped channel region adjacent to drain terminal along with lower work function gate material modulates the alignment of energy band profile of channel and drain regions at drain-channel interface which, further, increases the tunneling width in Tunnel FETs. Eventually, it leads to a significant reduction in band-to-band generation of charge carriers tunneling at drain-channel interface, thus causing a noticeable suppression in the nature of ambipolarity. The device performances of the presented structure is analysed through TCAD simulations to optimize length and doping concentration of two channel regions. Additionally, it is shown that the presented structure does not deteriorate subthreshold swing and ON-state current of Tunnel FETs.

With the advancement in CMOS technology, process related limitations, power dissipation, leakage etc. are main challenges for VLSI. So, in the field of VLSI an alternative device technology is the need of the time. Many new next generation devices have come up very recently, especially, the Carbon Nanotubes (CN)Field Effect Transistor (CNTFET)which has many advantages over conventional MOSFETs. MOSFETs like CNTFETs are the best for high-performance VLSI design as it fits well with the traditional MOS-VLSI design. This work presents an inclusive study and analysis of the results of simulation on different logic families. Moreover, the effect of technology nodes on leakage, power and delay are also highlighted in this simulation study. The logic families considered here are the conventional Complementary-Metal-Oxide-Semiconductor (CMOS)and Complementary-Pass-transistor-Logic (CPL)logics along with the CNTFET based logic. Based on these logic styles, NAND, NOR, XOR and multiplexer are implemented. An analysis is carried out to calculate power, worst delay and power delay product (PDP). This work will give the best select of logic style for VLSI applications useful for low power and high speed. The simulation is done by using Synopsys HSPICE tool with 90nm and 32 nm CMOS technologies and whereas for CNTFET 32 nm CNTFET model is chosen. The results show that the performances of the CNTFET based logics are superior compared to other logic families at different CMOS technology nodes.

The primary objective of the paper is to design a nonlinear control technique for a nonlinear intravenous model of Type 1 diabetes mellitus (T1DM) patient. Input–output feedback linearisation is utilised for deriving the nonlinear control law based on a modified version of Bergman’s minimal model augmented with the dynamics of the insulin pump and the meal disturbance. The results depict that the proposed control technique avoids severe hypoglycaemia and postprandial hyperglycaemia in the presence of exogenous meal disturbance as well as parametric uncertainty within a population of 100 virtual T1DM patients (inter-patient variability). The efficacy of the proposed control technique is investigated through variability grid analysis.

This paper presents an analysis of structural, electronic, and optical properties of pristine anatase titanium dioxide (TiO2) using orthogonalized linear combinations of atomic orbitals (OLCAO) basis set under the framework of density functional theory (DFT). The lattice constants such as a and c, band diagram, density of states (DOS) have also been studied. The band gap shows indirect nature around the fermi level in anatase TiO2. Density of states shows a contribution of Ti3d and O2p orbitals in conduction and valence band regions. From the analysis of optical properties, it is seen that the anatase TiO2 supports the interband indirect transition from O2p in valence region to Ti3d in the conduction region. All the optical properties are discussed in detail under the energy range of 0–16 eV. Further, we have compared the results with previous works as well as with the experimental results. We found that DFT-based simulation results are approximation to the experimental results.

Adders are the integral part of arithmetic logic units in digital system. Performance of the adder circuits decides the performance of those circuit and systems. Full adders are designed either in conventional approach or hybrid approach. In conventional approach, only one logic style is used, whereas in hybrid approach, two or more logic styles are used. A performance analysis between conventional and hybrid 1-bit full adder circuits is presented in this paper. In conventional design, complementary metal–oxide–semiconductor (CMOS) full adder, complementary pass logic (CPL) full adder, and transmission gate full adder (TGA) are the most popular. In this paper, CMOS full adder and CPL full adder are reported. The hybrid adder reported in this paper is designed using CMOS logic and transmission gate (TG) logic. The circuits are implemented using Cadence virtuoso tools with 180 nm United Microelectronics Company (UMC) technology. From the pre-layout simulation, performance metrics such as power, speed, and power delay products were computed. Performance of each of the circuits in terms of power, speed, power delay product (PDP), and area requirements in terms of transistor counts for the design is then compared.

In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.

We presented a detailed analysis of various properties of Cubic structured TiO2.

In this paper, we have presented an analysis on the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device. Si-NTFET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in better control over the short channel effects (SCEs). Bi-axial strain induced into the device by the inclusion of silicon-–germanium layer in between the channel. Three-dimensional simulations of the structure are carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data. The transfer characteristics, drain induced barrier lowering (DIBL), threshold voltage, Ion and Ioff, subthreshold swing of the Si-NTFET and strained Si-NTFET devices are investigated. It is seen that in strained Si-NTFET, the drive capability and inversion charge density is much higher compared to that of Si-NTFET. Evaluation of electrical performances confirms that the DIBL and other SCEs are either reduced or remains the same. However, the use of strained Si-NTFET is more suited for high speed and low power applications.

Carbon nanotube-based FET devices are getting more and more importance today because of their high channel mobility and improved gate capacitance against gate voltage. This paper compares and analyzes the effect of variation of oxide thickness on gate capacitance for single gate MOSFET, double gate MOSFET, silicon nanowire FET, and CNTFET devices through an exhaustive simulation. It is seen that in nanometer regime quantum capacitance is the deciding factor in calculating the gate capacitance of a FET device. CNTFET and silicon nanowire FET have a favorable characteristics of decreasing gate capacitance with the decrease in oxide thickness in deep nanometer regime, which is not possible to get in a single gate or a double gate MOSFET. This decrease in gate capacitance is observed at a gate voltage of 0.5 V and above which leads to reduced propagation delay and lower leakage compared to MOSFET devices.

This paper demonstrates the significance of histogram processing of an image particu larly the histogram equalization (HE). It is one of the widely used image enhancement technique. It has become a popular technique for contrast enhancement because the method is simple and effect ive. The basic idea of HE is to re-map the gray levels of an image. Here we propose two different techniques of Histogram Equalizat ion namely, the global HE and local HE. The Histogram Equalization has been performed in the MATLA B environ ment. The merits and demerits of both techniques of Histogram Equalization have also been discussed. It is seen after exhaustive experimentation on a nu mber of sample images that the proposed image enhancement techniques can be considered as an imp rovement over the inbuilt MATLAB function histeq.

Ever increasing demand for portable and battery-operated systems has lead to aggressive scaling. While technology scaling facilitates faster and high performance devices, at the same time it causes excessive power dissipation. Leakage power dissipation is now a dominating component of total power consumption in such portable devices. So there is a tremendous need to limit the power dissipation in high density chips which has initiated many innovative techniques to develop in the design of low power circuits and systems. Today's nano-scaled VLSI chips have ultra-thin gate oxide, very low threshold voltage and having short channels. As such leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. This Chapter review and compare the state of the art circuit techniques for leakage minimization. It also conceptually classifies the different techniques of leakage minimization. Moreover, a detailed comparison based on trading-offs with other design parameters is also given along with leakage minimization.

Binary Decision Diagrams (BDDs) can be graphically manipulated to reduce the number of nodes and hence the area. In this context, ordering of BDDs play a major role. Most of the algorithms for input variable ordering of OBDD focus primarily on area minimization. However, suitable input variable ordering helps in minimizing the power consumption also. In this particular work, we have proposed two algorithms namely, a genetic algorithm based technique and a branch and bound algorithm to find an optimal input variable order. Of course, the node reordering is taken care of by the standard BDD package buddy-2.4. Moreover, we have evaluated the performances of the proposed algorithms by running an exhaustive search program. Experi-mental results show a substantial saving in area and power. We have also compared our techniques with other state-of-art techniques of variable ordering for OBDDs and found to give superior results.

Finite State Machines are often used to design control circuitries which need to be highly testable and should consume very low power. FSM decomposition, state encoding and partitioning are the most effective techniques for achieving low power. However, selection of suitable polarity of output and state bits while state assignment is yet another avenue for achieving low power which has been explored in this paper. In first part of the paper, we have included all these key ideas-partitioning, state encoding and output polarity in the synthesis process and applied Genetic Algorithm (GA) to find an optimal solution for low dynamic power FSM synthesis. Next, we have incorporated a unique scheme of partitioning and state assignment for high testability, and formulated another GA, wherein we have minimized the state dependencies in order to reduce the number of feedback paths in the FSM for the ease of testability. After exhaustive experimentation with several benchmark FSM circuits, we find an average power reduction of 28.67% over state assigned by NOVA. Moreover, we have also carried out a power-testability trade-off and have seen superior fault-coverage with the proposed GA based technique over NOVA.

Traditionally, state-encoding strategies targeting minimization of area, dynamic power or a combination of them have been utilized in finite state machine (FSM) synthesis. With drastic scaling down of devices at recent technology level, leakage power has also become an important design parameter to be considered during synthesis. A genetic algorithm-based state encoding, targeting area and power minimized FSM, has been proposed in this paper. A unified technique to reduce both static power (leakage) and dynamic power along with area trade-off has been carried out for FSM synthesis, targeting static CMOS NAND-NAND PLA, dynamic CMOS NOR-NOR PLA and pseudo-NMOS NOR-NOR PLA implementations. Suitable weights for area, leakage power and dynamic power to minimize power density have also been explored. Simulation with MCNC benchmarks shows an average improvement of 31%, 26% and 29% in leakage power consumption, dynamic power consumption and area requirement respectively, over NOVA-based state assignment technique in case of dynamic CMOS PLA implementation. Improvements of 30% in leakage power and 15% in area have been obtained for pseudo-NMOS PLA implementation. For the static CMOS case, the improvements are about 29% in leakage power consumption, 14% in dynamic power consumption and 18% in area requirement.

In this paper, a comparison between Single Gate Fully Depleted SOI (SGSOI) and Double Gate Fully Depleted SOI (DGSOI) MOSFET with Si3N4 Spacer (insulator) around the Gate electrode at various different technology nodes are investigated. Simulations are done in ATLAS package of SIVACO tool. Further in this work, study of SON Devices (structure with air in place of buried oxide is termed as Silicon on Nothing (SON) are carried out. Simulation of Different values of Drive Current (Ion), Leakage Current (Ioff) and Transfer Characteristics (Id/Vg) are analysed in addition to compare and get a suitable conclusion of this study. For comparing the suppressed values of Short Channel Effects, Drain Induced Barrier Lowering (DIBL) with these different structuresarecalculated. All the structures are simulated for Single Gate as well as Double Gate in nanometerregime. Comparative results are given on the basis of the simulated results received by the double gate structure with Vertical Source and Drain (SD). Effect of Channel length reduction on its transfer characteristics and short channel effects are also studied. It has been found that SON structure shows larger threshold voltage value but small drive current as compare to SOI structures. Hence due to its low leakage current, it seems to be better for low power applications. Double gate SOI structure showsa sufficient drive current and less leakage current as compare to single gate SOI. For analysing the performance of the devices, Shockley-Read-Hall (SRH) Recombination, Radiative, Auger, and Surface Recombination models are deployed.

Wavelet transform is one of the most active areas of research in the image processing. This paper gives analysis of a very well known objective image quality metric, so called Structural similarity, MSE and PSNR which measures visual quality between two images. This paper presents the joint scheme of wavelet transform with structural similarity for evaluating the quality of image automatically. In the first part of algorithm, each distorted as well as original image are decomposed into three levels and in second part, these coefficient are used to calculate the structural similarity index, MSE and PSNR. The predictive performance of image quality based on the wavelet families like db5, haar (db1), coif1 with one, two and three level of decomposition is figured out. The algorithm performance includes the correlation measurement like Pearson, Kendall, and Spearman correlation between the objective evaluations with subjective one.

In nano-scaled devices, as the voltage is scaled down in order to achieve low power which further causes the threshold voltage also to be scaled in order to meet the performance requirements. However, reduction in threshold voltage leads to increased leakage power in short channel devices. Nanowire FET (NW-FET) is a possible alternative to minimize short channel effects in traditional MOS structure. In this paper we have justified the advantage of naowire FET over MOSFET by varying oxide thickness. Then we have seen the impact of channel length over characteristics of NW-FET with Si, Ge and GaAs as channel materials. With nanoHUB simulation, we found that, while reducing the channel length from 12 nm to 4 nm, the drain current and subthreshold swing (SS) at a very small Vg increases due to tunnelling effect. In NW-FET, the drain current is normalized by the circumference of the nanowire and the SS is defined as the inverse of the slope of log 10 Id vs Vg curve. We have also simulated and analyzed that the electron density at channel region while reducing the channel length.

This paper presents a comprehensive survey and analysis of various subthreshold leakage power reduction techniques. Moreover, a new technique for low leakage and high speed is also proposed here. As the technology scales down to deep sub micron level, leakage power dissipation increases very rapidly due to the high transistor density, low threshold and ultrathin dielectric. The new proposed circuit technique includes NMOS sleep and helper transistors to reduce leakage current with appropriate W/L ratio. The proposed design gives high speed performance because it includes NMOS transistor in the design which is having higher electron mobility. Post layout simulation of XOR gate using microwind tool with 45nm Berkeley predictive technology model shows that the new circuit technique achieves significant power reduction during a standby mode with lesser delay.

Leakage power dissipation has become a dominating proportion of the total power dissipation. According to international technology roadmap semiconductor (ITRS), this directly affects the portable battery operated device like mobile phones. A detailed analysis of leakage reduction data retention leakage feedback approaches are discussed in this paper. We here propose a new design data retention scheme which consist PMOS helper transistors which reduces leakage current while saving exact logic state. Based on simulation with inverter chain using 32nm Berkeley predictive technology model, the proposed approach demonstrate that PMOS helper transistors leakage feedback technique reduces considerable amount of leakage in CMOS circuits.

Image Processing and analyzing images of the operation is to always ask about their quality, whether the quality is increased or decreased? Image Quality Assessment techniques is required for prediction of quality of the image. Human Visual System (HVS) has been widely incorporated in estimating the quality of the image, as human is the ultimate observer of the image. In this work, Author investigated the SSIM index depends upon correlation based filtering like Gaussian low pass filter, averaging filter, Circular averaging filter and motion filter, also mean square error and peak signal to noise ratio is used.