310 results on '"Rooyackers, R."'
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52. Comparative study of vertical GAA TFETs and GAA MOSFETs in function of the inversion coefficient
53. Intrinsic voltage gain of Line-TFETs and comparison with other TFET and MOSFET architectures
54. Influence of the Ge amount at source on transistor efficiency of vertical gate all around TFET for different conduction regimes
55. Total ionizing dose influence on proton irradiated triple gate SOI Tunnel FETs.
56. Analysis of analog parameters in NW-TFETs with Si and SiGe source composition at high temperatures
57. Staggered band gap n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki diode investigations for TFET device predictions
58. The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices
59. Study of Hysteresis in Vertical Ge-Source Heterojunction Tunnel-FETs at Low Temperature
60. Comparison of Current Mirrors Designed with TFET or FinFET Devices for Different Dimensions and Temperatures
61. Impact of dopants and silicon structure dimensions on {113}‐defect formation during 2 MeV electron irradiation in an UHVEM
62. (Invited) Monolithic Integration of III-V Semiconductors by Selective Area Growth on Si(001) Substrate: Epitaxy Challenges & Applications
63. In situ UHVEM irradiation study of intrinsic point defect behavior in Si nanowire structures
64. Comparison between vertical silicon NW-TFET and NW-MOSFETfrom analog point of view
65. Study of low frequency noise in vertical NW-Tunnel FETs with different source compositions
66. Impact of the diameter of vertical nanowire-tunnel FETs with Si and SiGe source composition on analog parameters
67. Perspective of tunnel-FET for future low-power technology nodes
68. The device architecture dilemma for CMOS technologies
69. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to lOnm and 30nm gate length
70. (Invited) The Impact of a (Si)Ge Heterojunction on the Analog Performance of Vertical Tunnel FETs
71. In0.53Ga0.47As quantum-well MOSFET with source/drain regrowth for low power logic applications
72. Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature
73. Unity gain frequency on FinFET and TFET devices
74. A new complementary hetero-junction vertical Tunnel-FET integration scheme
75. Back bias influence on analog performance of pTFET
76. NW-TFET analog performance for different Ge source compositions
77. Analysis of analog parameters in NW-TFETs with Si and SiGe source composition at high temperatures.
78. The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices.
79. Morphology and defects in shallow trench isolation structures
80. In0.53Ga0.47As Diodes for Band-to-Band Tunneling Calibration and n- and p-LineTFET performance prediction
81. Experimental Comparison between pTFET and pFinFET under Analog Operation
82. Quantitative three-dimensional carrier mapping in nanowire-based transistors using scanning spreading resistance microscopy
83. CMOS-Compatible Dielectric Constant Engineering by Embedding Metallic Particles in Aluminum Oxide
84. Experimental analog performance of pTFETs as a function of temperature
85. Temperature Influence on Nanowire Tunnel Field Effect Transistors
86. Trap-Assisted Tunneling in Vertical Si and SiGe Hetero-Tunnel-FETs
87. Study of ohmic contacts to n-type Ge: Snowplow and laser activation
88. Advancing CMOS beyond the Si roadmap with Ge and III/V devices
89. Novel architecture to boost the vertical tunneling in Tunnel Field Effect Transistors
90. Electrical results of vertical Si N-Tunnel FETs
91. Si-based tunnel field-effect transistors for low-power nano-electronics
92. Observation of diameter dependent carrier distribution in nanowire-based transistors
93. Contact resistivity and Fermi-level pinning in n-type Ge contacts with epitaxial Si-passivation
94. Record low contact resistivity to n-type Ge for CMOS and memory applications
95. Drive Current Improvement in Si Tunnel Field Effect Transistors by means of Silicide Engineering
96. Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions
97. Characteristics and Integration Challenges of FinFET-based Devices for (Sub-)22nm Technology Nodes Circuit Applications
98. Multiple-Gate Tunneling Field Effect Transistors with sub-60mV/dec Subthreshold Slope
99. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?
100. The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET
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