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A per-column, delta-sigma, analog-to-digital converter for use in CMOS image sensors is reported. Two techniques, subtraction and preconditioning, are proposed to compensate for the column-to-column mismatches and the resulting fixed-pattern noise introduced into the image. Equations governing the operation of the proposed topology are developed. Experimental results verify that even in the presence of very large offsets, such as a 200 mV mismatch in the MOSFETs' threshold voltages, the proposed topology operates as desired.

As CMOS technology scales to nanometer dimensions, analog-to-digital converter (ADC) design has become increasingly more challenging. This is mainly due to the increased transistor leakage currents, process variations, and poor matching. The K-Delta-1-Sigma (KD1S) modulator was proposed as a practical solution for designing high-speed ADCs in nanometer CMOS processes. This paper presents an 8-path KD1S modulator with an effective sampling frequency of 2 GHz derived from a 250 MHz input clock. The simulation results confirm the true first-order noise shaping of the modulator. The simulated SNR is 44.95 dB and the simulated SNDR is 44.41 dB corresponding to N eff = 7.17 bits with a conversion bandwidth of 15.625 MHz.

A 4 Gb DRAM architecture utilizing a scalable number of data pins is proposed. The architecture does not impact chip size and does not require additional metal layers. The 4 Gb DRAM measure 68.88 mm2 and achieves an array efficiency of 59.9%. This was accomplished by using a split bank, edge I/O interface, central row, and central column structures. The architecture coincides with the chip size and array efficiency measurements predicted by the ITRS for a 40 nm 2012 production DRAM architecture.

Over the past decade CMOS technology has been continuously scaling which has resulted in sustained improvement in transistor speeds. However, the transistor threshold voltages do not decrease at the same rate as the supply voltage (V DD ). Besides, the open-loop gain available from the transistors is diminishing. This trend renders the traditional techniques, like cascoding and gain boosting, less useful for achieving high DC gain in nano-scale CMOS processes. Thus, horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low-V DD processes. This paper presents a design procedure for op-amp design using split-length compensation. A reversed-nested split-length compensated (RSLC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RSLC topology is then extended to the design of three-stage fully-differential op-amps.

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fully-differential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 µm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load.

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method.

The bandwidth and power consumption of dynamic random access memory (DRAM), used as the main memory of a computer system, impacts computer execution rates. DRAM manufacturers focus on density increases, due to the innate price per bit decline of main memory, while processor manufacturers continually focus on boosting performance. This leads to a performance gap between the two technologies. Proximity communication promises to increase the off/on chip bandwidth of DRAM products while reducing the power consumption of the main memory system. The design of a memory system employing 4 Gb DRAM chips with a 64- bit wide communication bus using proximity communication is proposed. Technological roadblocks are analyzed and novel solutions are proposed. The proposed 4 Gb DRAM architecture can reduce the power consumption of a main memory system by 50% while increasing the bandwidth by 100%. The 4 Gb chip architecture measures 68.88 mm2 and has an array efficiency of 59.9%. The estimates are comparable to 2012 International Technology Roadmap for Semiconductors' (ITRS) estimates of 74 mm2 and 56%, respectively.

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. This includes lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADC is required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset error in its transfer function, which will lead to fix pattern noise. Correcting these gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. Therefore, a technique to minimize the effects of gain error in a delta-sigma modulation ADC for CMOS image sensor is discussed.

A monolithic integrated chip-scale surface plasmon resonance (SPR) sensor is demonstrated. The device consists of a pn photodiode covered with a periodic modified thin metal film whose lattice constant is on the order of the wavelength of light. The device performs real-time measurement of resonant wave-lengths of enhanced optical transmission due to surface plasmon resonance, which are influenced by the presence of chemical or biological materials at the device's surface.

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes the K-Delta-1- Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared opamp and K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance.

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area.

We have demonstrated that back-end-of-line (BEOL) processing can successfully be performed in a university environment on die that have been fabricated at a foundry. This processing option enables universities to integrate state-of-the-art feature sizes with low resolution photolithography capabilities, such as achieved with a contact aligner, typically available at universities. With this capability, new device technologies and materials can be explored at the university level, where the basic research on the technology can occur without the timelines and expectations that are placed on product development in an industrial setting. By incorporating state-of-the-art feature sizes with these research efforts, the research results will be more applicable and more easily transferable to an industrial environment. In our project, we have demonstrated the integration of a foundry processed chip with the BEOL university processing through the fabrication of a small phase-change memory array with CMOS access transistors and addressing circuitry wherein the phase-change memory material was processed BEOL at Boise State University.

This paper presents the design and experimental results of W-2W current mirror binary-weighted current steering digital-to-analog converter (DAC) and its application for programming phase change memory (PCM). This new approach significantly reduces the layout area of current-mode DACs by the virtue of its compact size. The proposed DAC can replace the write driver circuits in phase change memories. Both 6-bit and 12-bit DACs have been fabricated in 0.5 mum CMOS technology. The layout size of the 12-bit and the 6-bit DACs is 0.09 mm 2 and 0.04 mm 2 respectively. Experimental results are presented and the limitations are discussed.