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As energy efficiency becomes a crucial concern in almost every kind of digital application, Approximate Computing gains popularity as a potential answer to this ever-growing energy quest. Approximate Computing is a design paradigm particularly suited for error- resilient applications, where small losses in accuracy do not represent a significant reduction in the quality of the result. In these scenarios, energy consumption and resources employment (such as electric power, or circuit area) can be significantly improved at the expense of a slight reduction in output accuracy. While Approximate Computing can be applied at different levels, my research focuses on the design of approximate hardware. In particular, my work explores Approximate Logic Synthesis, where the hardware functionality is automatically tuned to obtain more efficient counterparts, while always controlling the entailed error. Functional modifications include, among others, removal or substitution of gates and signals. A fundamental prerequisite for the application of these modifications is an \emph{accurate error model} of the circuit under exam. My Ph.D. research work has deeply concentrated on the derivation of accurate error models of a circuit. These can, in turn, guide Approximate Logic Synthesis algorithms to optimal solutions and avoid expensive, time-consuming simulations. A precise error model allows to fully explore the design space and, potentially, adjust the desired level of accuracy even at runtime. I have also contributed to the state of the art in ALS techniques by devising a circuit pruning algorithm that produces efficient approximate circuits for given error constraints. The innovative aspect of my work is that it exploits circuit topology and graph partitioning to identify circuit portions that impact to a smaller extent on the final output. With this information, ALS algorithms can improve their efficiency by acting first on those less-influent portions. Indeed, this error characterisation proves to be very effective in guiding and modeling approximate synthesis.

High Level Synthesis (HLS) is a process which, starting from a high-level description of an application (C/C++), generates the corresponding RTL code describing the hardware implementation of the desired functionality. The HLS process is usually controlled by user-given directives (e.g., directives to set whether or not to unroll a loop) which influence the resulting implementation area and latency. By using HLS, designers are able to rapidly generate different hardware implementations of the same application, without the burden of directly specifying the low level implementation in detail. Nonetheless, the correlation among directives and resulting performance is often difficult to foresee and to quantify, and the high number of available direct- ives leads to an exponential explosion in the number of possible configurations. In addition, sampling the design space involves a time-consuming hardware synthesis, making a brute-force exploration infeasible beyond very simple cases. However, for a given application, only few directive settings result in Pareto- optimal solutions (with respect to metrics such as area, run-time and power), while most are dominated. The design space exploration problem aims at identifying close to Pareto-optimal implementations while synthesising only a small portion of the possible configurations from the design space. In this dissertation I present an overview of the HLS design flow, followed by a discussion about existing strategies in literature. Moreover, I present new exploration methodologies able to automatically generate optimised implementations of hardware accelerators. The proposed approaches are able to retrieve a close approximation of the real Pareto solutions while synthesising only a small fraction of the possible design, either by smartly navigating their design space or by leveraging prior knowledge. Herein, I also present a database of design space explorations whose goal is to help researchers to design new strategies by offering a reliable source of knowledge for machine learning based approaches, and standardise the methodologies evaluation. Lastly, the stepping-stones of a new approach relying on deep learning strategies with graph neural networks is presented, and final remarks about future research directions are discussed.

Performance increase, in terms of faster execution and energy efficiency, is a never-ending research domain and does not come for free. The breakdown of Dennard scaling, along with the seemingly inevitable end of Moore’s law economic aspect, present a new challenge to computer architects striving to achieve better performance in modern computer systems. Heterogeneous computing emerges as one of the solutions to overcome these limitations and keep the performance trend rising. Heterogeneous platforms employ specialized hardware (HW) that can accelerate the execution of a software (SW) application, or a part of that application. However, the design of efficient HW/SW computer architectures is a challenging problem, as it entails integration of a general purpose CPU with a number of specialized HW accelerators. The choice of which parts of an application to be accelerated as well as the optimizations to be applied to the HW accelerated parts, while taking into account the underlying memory system and the platform characteristics that the HW accelerators are implemented onto, are all non-trivial research questions and depend heavily on the characteristics of the SW applications that are going to be accelerated. Therefore, an in-depth SW analysis can be crucial, prior to designing a heterogeneous system, as it can provide valuable information and subsequently highly benefit performance. My research has focused on building automation frameworks that can aid HW engineers in the early stages of the design process. I have extended the capabilities of compiler infrastructures, while addressing these research questions, so that better decisions are made and, in turn, faster execution and improved energy efficiency is achieved. The frameworks I developed are, hence, valuable automation aids for the HW/SW partitioning and optimization phases, driving the designs of effective heterogeneous platforms one step forward.

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