95 results on '"Peng, Chunyu"'
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52. Effect of the Carbon on the Electrochemical Performance of Rechargeable Zn-Air Batteries
53. Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing
54. In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations
55. Novel Radiation-Hardened Latch Design for Space-Radiation Environments
56. Write‐enhanced and radiation‐hardened SRAM for multi‐node upset tolerance in space‐radiation environments.
57. Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports
58. Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing
59. Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption
60. A 17.5–23 GHz high precision phase shifting four‐channel satellite communication receiver with phase calibration technology
61. In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations
62. An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation
63. Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM
64. In-memory Multibit Multiplication Based on Bitline Shifting
65. A new reading mode based on balanced pre-charging and group decoding
66. Challenges and Solutions of the TFET Circuit Design
67. In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands
68. Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
69. Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield
70. In-Memory Multibit Multiplication Based on Bitline Shifting.
71. Current mirror‐based compensation circuit for multi‐row read in‐memory computing
72. Read‐decoupled 8T1R non‐volatile SRAM with dual‐mode option and high restore yield
73. Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application
74. An inverter chain with parallel output nodes for eliminating single-event transient pulse
75. A high performance radiation-hardened SRAM cell based on Quatro
76. A single event upset tolerant latch with parallel nodes
77. Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS
78. Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application
79. Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique
80. A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination
81. Self‐compared bit‐line pairs for eliminating effects of leakage current
82. A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process
83. A radiation harden enhanced Quatro (RHEQ) SRAM cell
84. Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers
85. A Novel Controllable BIST Circuit for embedded SRAM
86. Additive-calibration scheme for leakage compensation of low voltage SRAM
87. Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier
88. Read/write margin enhanced 10T SRAM for low voltage application
89. Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers
90. Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol. 12 (2015) No. 5 pp. 20150102]
91. A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier
92. The Optimization Scheme Of The Leakage Current Reduction Technique For SRAM Design
93. (paper withdrawn) Variation-tolerant Timing Tracking Scheme for SRAM sense amplifier Based on Multi-Stage Dual RBL Delay Technique
94. Electrodeposition of nanoscaled nickel in a reverse microemulsion
95. High‐throughput in‐memory bitwise computing based on a coupled dual‐SRAM array with independent operands.
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