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We investigated the temperature dependence (1200–2100 °C) of morphological features in the growth of epitaxial graphene on 4H-SiC (0 0 0 −1) C-face in ultra high vacuum (UHV). As a SiC initial surface preparation technique prior to the epitaxial graphene growth, Si-vapor etching was conducted to ensure a uniform step-terrace structure at 4H-SiC (0 0 0 −1) consisting of 0.5 nm step height. The epitaxial graphene growth has been performed in our original experimental setup with a TaC container inside an all metal chamber with radiative heating system, which allows to increase the graphitization temperature up to 2100 °C in UHV. The surface morphology of the epitaxially grown multilayer graphene, characterized by atomic force microscopy (AFM), exhibited a drastic change as a function of temperature. Ridge structures of the topmost graphene layer(s) appeared above 1600 °C, where the well-ordered step-terrace initial structure of the SiC vanished. In this high temperature range, the network of the ridges spread over the surface with an increase in temperature. Raman topography mapping for characterizing site dependent 2D-spectrum implies that rotational stacking disorder of graphene layers is accompanied by relatively small ridge network on the surface in a specific temperature range.

As a new graphene functionality applicable to post-implantation high temperature annealing of SiC, a method of in situ formation and removal of large area epitaxial few-layer graphene on 4H-SiC(0001) Si-face is proposed. It is demonstrated that the homogeneous graphene layer formed by Si sublimation can be preserved without the decomposition of the underlying SiC substrate even in the excess of 2000 oC in ultrahigh vacuum. It is due to the existence of the stable (6√3×6√3) buffer layer at the interface. To ensure this cap function, the homogeneity of the interface must be guaranteed. In order to do that, precise control of the initial SiC surface flatness is required. Si-vapor etching is a simple and versatile SiC surface pre/post- treatment method, where thermally decomposed SiC surface is compensated by a Si-vapor flux from Si solid source in the same semi-closed TaC container. While this Si-vapor etching allows precise control of SiC etch depth and surface step-terrace structures, it also provides a “decap” function to remove of the graphene layer. The surface properties after the each process were characterized by AFM and Raman spectroscopy.

Solving the global warming problem is a great challenge before us, and energy conservation with more efficient use of electricity is the definite way to mitigate the problem since it is the most widely used energy source at home and in the industry. Hence, power electronics is now expected to play a vital role in the global energy conservation scenario. Present-day Si power electronics, however, suffer from the performance limitations due to their material properties. Wide band gap semiconductor silicon carbide (SiC) is a possible solution to this problem and has attracted considerable attention in recent years. This paper reviews the present status and future prospects of the SiC single crystal substrate manufacturing technology. Recent developments of the technology include the attainment of crystal diameters up to 100 mm and the significant reduction in densities of crystallographic defects. Owing to the availability of large high-quality substrates, SiC power devices have begun to show performance levels that largely exceed those produced from Si.

Dislocations in highly nitrogen-doped (N > 1×1019 cm-3) low-resistivity ( < 10 mcm) 4H-SiC substrates were investigated by photoluminescence imaging, synchrotron X-ray topography, and defect selective etching using molten KOH. The behavior of dislocations is discussed particularly in terms of their glide motion in the presence of a high concentration of nitrogen. The results indicate that nitrogen impurities up to mid 1019 cm-3 concentration do not show any discernible influence on the glide behavior of basal plane dislocations (BPDs) in 4H-SiC crystals grown by physical vapor transport (PVT) method.

Heavily nitrogen-doped n + 4H–SiC single crystals were grown by the physical vapor transport (PVT) method. The nitrogen incorporation kinetics in a heavily doped regime was studied in terms of growth temperature dependence, and it was revealed that the growth temperature substantially influenced the amount of nitrogen incorporated into the crystals and their surface step structures on the (0 0 0 1¯)C facet plane. The structural quality of heavily nitrogen-doped 4H–SiC crystals was examined by X-ray rocking curve measurements and defect selective etching by molten KOH at around 500 °C. The crystals contained an extremely low density of 3C–SiC inclusions and stacking faults and showed a comparable crystalline quality to conventionally doped 4H–SiC substrates. Furthermore the structural stability of the heavily nitrogen-doped 4H–SiC substrates during high-temperature treatments has been investigated. The substrates with a large {0 0 0 1} surface roughness showed a resistivity increase after annealing at 1100 °C for 2 h, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of substrates, which indicate that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates.

The stacking fault formation in highly nitrogen-doped n+ 4H-SiC single crystal substrates during high temperature treatment has been investigated in terms of the surface preparation conditions of substrates. Substrates with a relatively large surface roughness showed a resistivity increase after annealing at 1100°C, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of the substrates, which indicates that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. In this regard, mechano-chemically polished (MCP) substrates with a minimum surface roughness (< 0.3 nm) exhibited no resistivity increase and very few stacking faults after annealing even when the nitrogen concentration of the substrates exceeded 1×1019 cm-3.

The theromoelastic stress in post-growth SiC crystals has been investigated in order to suppress the cracks which were frequently observed in SiC crystals with larger diameters. Optimizing the temperature distribution in growing crystals lead to reduction of tensile stress components, and thus resulting in crack-free 100mm diameter SiC crystals with micropipe (MP) densities of 0.025/cm2. The concept of process optimization we established is confirmed to be effective to the growth of large diameter SiC crystals with mechanical stability.

The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.

The coefficient of thermal expansion (CTE) of SiC single crystals is important, in particular, for both designing device assembly and controlling stress distributions in heteroepitaxial thin film structures grown onto SiC substrates. We have performed very precise measurements of the CTEs for SiC single crystals comprising of single 4H polytype PVT-grown in NIPPON Steel Corporation for a temperature range from 123 K to 473 K using a laser interferometry method. This method allows us to directly measure the temperature dependent variation in thermal expansion of the crystal volume with much higher accuracy, and enables us to straightforwardly obtain practical information of CTE data. Furthermore in order to discuss the CTE behavior for a wider temperature range the CTEs at higher temperatures up to 1573 K have been also measured using dilatometer method. The CTE obtained for a nitrogen-doped 4H-SiC single crystal increases continuously from 0.8 ppm/K to 3.1 ppm/K for temperatures of 273 K and 423 K respectively, and further increases to 5.4 ppm/K at 1273 K. We conclude from our data that the CTE variations are likely to be almost independent of the crystal axis directions of SiC from 123 K up to 1573 K.

4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.

The behavior of basal plane dislocations in hexagonal silicon carbide (SiC) single crystals grown by physical vapor transport (PVT) was investigated by defect selective etching and transmission electron microscopy (TEM). Oval-shaped etch pits on the etched vicinal (0001)Si surface due to basal plane dislocations were densely distributed around hollow-core threading screw dislocations (micropipes) and formed etch pit arrays perpendicular to the off-cut direction, indicative of the multiplication of basal plane dislocations around micropipes during crystal growth or post-growth cooling. Arrays of oval-shaped etch pits were also observed in the vicinity of small hexagonal etch pit rows due to threading edge dislocation walls, i.e., low angle grain boundaries (LAGBs). They were asymmetrically distributed across LAGBs, and TEM revealed that threading edge dislocations constituting LAGBs trapped basal plane glide dislocations. The interaction between basal plane dislocations and threading screw and edge dislocations extending along the c-axis in SiC crystals was modeled, and the characteristic behavior of basal plane dislocations in hexagonal SiC single crystals was discussed.

The dislocation formation and propagation processes in physical vapor transport (PVT) grown 4H silicon carbide (4H–SiC) single crystals have been investigated using defect selective etching and transmission electron microscopy (TEM). It was found that while the growth initiation process generally increased the density of threading dislocations in the grown crystal, for certain areas of the crystal, threading dislocations were terminated at the growth initiation. Foreign polytype inclusions also introduced a high density of dislocations at the polytype boundary. In the polytype-transformed areas of the crystal, almost no medium size hexagonal etch pits due to threading screw dislocations were observed, indicating that the foreign polytype inclusions had ceased the propagation of threading screw dislocations. Based on these results, we argued the formation and propagation of the threading dislocations in PVT grown SiC crystals, and proposed the dislocation conversion process as a plausible cause of the density reduction of threading dislocations during the PVT growth of SiC single crystals.

Dislocation processes during physical vapor transport (PVT) growth of silicon carbide (SiC) single crystals were investigated by defect selective etching. It was found that foreign polytype inclusions introduced a high density of dislocations at the polytype boundary. In the polytype-transformed areas of the crystal, very few medium size hexagonal etch pits due to threading screw dislocations were observed, indicating that the polytype transformation ceased the propagation of threading screw dislocations. The oval-shaped etch pit arrays observed on the etched vicinal (0001)Si surface, indicative of the dislocation multiplication in the basal plane, showed characteristic distribution around micropipes. Based on the results, we have argued the dislocation behavior in PVT grown SiC crystals, suggesting that dislocation interaction and conversion are relevant processes to understanding the behavior.

The effect of off-orientation growth has been investigated in terms of stacking fault formation during physical vapor transport (PVT) growth of silicon carbide (SiC) single crystals on the (11\(\bar 2\)0) seed crystal surface. Occurrence of stacking fault formation is largely dependent on the direction of off-orientation, and basal plane stacking fault density is significantly reduced by growing the crystals on a (11\(\bar 2\)0) seed crystal off-oriented toward 〈0001〉. The density of the basal plane stacking faults rapidly decreases from 100–150 cm−1 to ∼10 cm−1 as the degree of off-orientation is increased from 0 to 10 deg. The results are interpreted in the framework of microscopic facet formation during PVT growth, and the introduction of off-orientation of seed crystal is assumed to prevent (01\(\bar 1\)0) and (10\(\bar 1\)0) microfacet formation on the (11\(\bar 2\)0) growing surface through modification of the surface growth kinetics and to suppress the stacking fault formation.

Optical communication wavelength emissions from the quantum dots (QDs) structures prepared on (001)-oriented GaAs substrates are discussed. A new growth technique of low-stressed InAs QDs on the AlGaSb layer in a low lattice-mismatched (1.3%) InAs/AlGaSb system is presented. The average height and diameter of the 4-ML InAs QDs on AlGaSb are evaluated to 5.8 nm and 45.2 nm respectively with an average density of 2.18 x 1010 /cm2 using atomic force microscope (AFM) measurements. There is structural selectivity between the QDs layer and the flat hetero-interface under changing growth conditions in the InAs/AlGaSb system. Long-wavelength PL emissions around 1.3 µm and 1.55 µm can be achieved by embedding InAs QDs in AlGaSb layers. Therefore it is expected that low-stressed InAs QDs grown on a AlGaSb layer prepared on a GaAs substrate will be useful in the fabrication of novel QDs devices for optical-communication networks.

Raman microspectroscopy has been applied to the determination of free carrier distributions in modulation-doped 6H-SiC crystals in order to examine the process of the crystal growth. The spatial distribution of the carrier concentration and mobility is extracted from the line shape analysis of LO phonon plasmon coupled modes using a dielectric function which takes into account the LO-phonon damping. The residual time of dopants in a growth furnace after the shut-off of the doping gas is inferred from the carrier density profiles. The growth rate of the crystals and incorporation of the dopants are also studied. The relationship between the carrier mobility and carrier concentration is determined from these quantities at different positions in the sample. It is found that the LO-phonon damping has much influence on the carrier damping and changes linearly with the carrier concentration in a range below ∼2×1018 cm−3.

6H-SiC metal-semiconductor field-effect transistors (MESFETs) were fabricated on epitaxial layers grown on (0001) Si faces by chemical vapor deposition and the influence of screw dislocations in the epitaxial layers on the DC characteristics of the MESFETs was studied. The fabricated MESFETs with a gate length of 1 µm indicated the maximum transconductance of 30–35 mS/mm for the drain-source saturation current of 30–40 mA/mm. The evaluation of small-signal RF characteristics revealed the cutoff frequency of 2.7 GHz and the maximum operation frequency of 6.8 GHz. DC characteristics of the MESFETs with the screw dislocation in the device channel region were compared to those of MESFETs without the dislocation. From the comparison, it was demonstrated for the first time that the drain-source current–voltage characteristics for the MESFETs were negligibly affected by the screw dislocation although it caused some degradation of the gate Schottky characteristics.

The availability of large high-quality silicon carbide (SiC) single crystals is a key issue in the development of the full potential of SiC-based device technology. In this paper, recent achievements in bulk crystal growth of SiC are reviewed. We present results on the physical vapor transport growth of SiC bulk single crystals by highlighting the crystal diameter enlargement and the quality improvement of SiC crystals. The causes and formation mechanisms of crystallographic defects, such as micropipes and low-angle grain boundaries, in SiC crystals are discussed. The results of the growth perpendicular to the c -axis are also reported, where stacking faults are defects of major concern. We present an atomistic surface model for the stacking fault generation and discuss a possible way to circumvent this problem.

The wide (0001) terrace formation due to step bunching on a vicinal 4H-SiC (0001) epitaxial layer surface was investigated using low-energy electron channeling contrast (LE-ECC) imaging and atomic force microscopy. LE-ECC imaging revealed that step bunching resulted in the formation of wide atomically-flat (∼200 nm) (0001) terraces on the surface, and the terraces tended to form in pairs. Terraces in a pair had almost the same width and often showed the same LE-ECC; moreover, the contrast of the two terraces, either bright or dark, appeared to be determined by the orthogonal misorientation of substrates. On the basis of these results, the formation mechanism of the paired terraces with the same LE-ECC on a vicinal 4H-SiC (0001) surface is discussed herein.

Silicon carbide (SiC) single crystals, a promising material for high power and high temperature semiconductor devices, have microscopic hollow defects, so-called “micropipes.” Their formation mechanism is not satisfactorily clarified yet. In this paper, a surface step model for micropipe formation in SiC single crystals is proposed, where the strong repulsive interaction between surface steps on the SiC(0 0 0 1) surface is a major driving force for coalescing unit cell size screw dislocations.

Surface graphitization of 4H-SiC (0001) at high temperature up to 2100 °C in ultra high vacuum (UHV) was observed for the first time in this study. From precisely controlled SiC step-terrace surfaces, uniform graphitized surface morphologies with large terraces appeared at anneal temperatures above 2000 °C. All the high-temperature processes were performed by using a newly constructed all metal chamber which enables to elevate temperature from 800 °C to 2000 °C within a minute in UHV. Initial step-terrace surfaces consisting of 1.0nm step height were achieved on 4H-SiC (0001) by utilizing newly proposed Si-vapor etching in a “semi-closed” TaC container. By estimations of Raman spectra, mainly bilayer graphene was obtained at temperatures from 1600 °C to 2100 °C. Estimation of Raman spectra also indicated that larger domain size graphene grows at higher temperatures, which coincides well with the results of morphological changes observed by AFM measurements. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The structural properties of subgrain boundaries (low-angle grain boundaries) in bulk SiC crystals have been studied using high-resolution X-ray diffraction (HRXRD) and molten KOH defect selective etching. The defect-selective etching revealed that the subgrain boundaries were polygonized into 1 1 0 0 directions and most often occurred at the peripheral parts of crystals. The relative misorientation between adjacent subgrains was examined by HRXRD, and it was found that the tilting of the (0 0 0 1) lattice plane occurred at the subgrain boundaries and had a rotation axis parallel to both the boundary plane and the (0 0 0 1) basal plane. Based on these results, we have discussed the cause and mechanism of the formation of subgrain boundaries in bulk SiC crystals.

Surface topography of the {0 0 0 1} facet plane of as-grown 6H- and 4H-SiC crystals was studied ex situ by Nomarski optical microscopy (NOM) and atomic force microscopy (AFM). The surface polarity and the polytype of grown crystals largely affect the growth surface morphology of SiC{0 0 0 1} via differences in several thermodynamic and kinetic parameters. NOM observations revealed giant steps of a few micrometers in height on the {0 0 0 1} growth facet, and it was found that a morphological transition of the growth facet occurred when the growth conditions were changed. AFM imaging of the stepped structure of SiC{0 0 0 1} detected steps of height equal to the unit c-lattice parameter (c=1.512 nm for 6H-SiC and 1.005 nm for 4H-SiC). They are fairly straight and very regularly arranged, giving rise to equidistant step trains. Upon nitrogen doping, these regular step trains on the 6H-SiC(0 0 0 )C and 4H-SiC(0 0 0 )C surfaces became unstable: the equidistant step trains were transformed into meandering macrosteps of height greater than 10 nm. In this paper, we discuss the mechanism of macrostep formation (step bunching) on the SiC{0 0 0 1} surfaces through the consideration of the interplay between step energetics (repulsive step interaction) and kinetics (asymmetric step kinetics) on the growing crystal surface and elucidate how they affect the growth surface morphology of the SiC{0 0 0 1} facet.

We report on the observation of the impurity-induced morphological instability of step trains during sublimation growth on $6H\ensuremath{-}\mathrm{SiC}(0001).$ $6H\ensuremath{-}\mathrm{SiC}(0001)$ provides a step system suitable for studying the effects of repulsive step interaction. Its large step height and stiffness result in a strong repulsion force between steps, which energetically establishes extremely regular equidistant step trains on the $6H\ensuremath{-}\mathrm{SiC}(0001)$ surface. Upon nitrogen doping, these regular step trains on $6H\ensuremath{-}\mathrm{SiC}(0001)$ become unstable: the equidistant step trains are transformed into meandering macrosteps by nitrogen adsorption on the growing crystal surface. We discuss the effect of nitrogen adsorption through the consideration of asymmetric step kinetics and shed more light on the mechanism of step bunching on the $6H\ensuremath{-}\mathrm{SiC}(0001)$ surface. The competition between the repulsive step-step interaction and the asymmetric step kinetics plays a vital role in the observed morphological transition.

This article reviews the recent development of large single-crystal silicon carbide (SIC) substrates. The technological potential of SiC for high-power, high-temperature, and high-frequency electronic devices has been recognized for several decades; however, such applications have been largely hindered by problems related to bulk crystal growth. The SiC bulk crystal growth technology has recently achieved drastic improvement and enabled the growth of large high-quality single crystals. Due to the availability of large high-quality substrates, progress in SiC thin-film epitaxy and devices has been rapid, and application of SiC to many fields is fast reaching its real potential. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(6): 8–19, 1998

The impurity incorporation kinetics during modified-Lely growth of silicon carbide (SiC) have been studied in terms of several growth parameters. It was found that the nitrogen incorporation is well described by a Langmuir isotherm type equation, implying that dynamic equilibrium between the vapor phase and the adsorbed nitrogen is established. The polytype of grown crystal and the seed orientation influence the impurity incorporation. For growth on (0001)C, 6H-SiC crystals always incorporate more nitrogen and less boron than 4H-SiC crystals, while no clear polytypic dependence of impurity incorporation is observed for growth on (1100) and (1120). Atomic force microscope observations revealed that there is a marked difference in the growth morphology between 6H-SiC(0001)C and 4H-SiC(0001)C. The origin of the polytypic dependence of impurity incorporation during growth on (0001)C is discussed with reference to the growth surface morphology.

The surface topography of the {0001} facet of as-grown 6H and 4H SiC boules was observed ex-situ by atomic force microscopy (AFM). Peculiar stepped structures of SiC{0001} to the growth face polarity and the polytype were detected. Height steps equal to the c-lattice parameter (1.5 nm) were observed to be dominant on the 6H-SiC(0001)Si surface. They were very regularly arranged, i.e. straight and almost equally spaced. On the other hand, meandering macrosteps of height more than 10 nm were observed on the 6H-SiC(000 1 )C and the 4H-SiC(000 1 )C surfaces. Based on the results, the mechanism of formation of these surface morphologies is discussed.

The etching behaviour of {alpha}-SiC single crystals by molten KOH has been investigated. The etching rate is significantly affected by the etching ambience: dry air yields an etching rate eight times larger than nitrogen. This result suggests an essential role of dissolved oxygen in the melt for the molten KOH etching of SiC. The {l_brace}0001{r_brace} surface shows a surface polarity dependence: the etching rate of (000 anti 1)C is about four times larger than that of (0001)Si. The etching rate of (000 anti 1)C exhibits an Arrhenius type temperature dependence with an activation energy of 15-20 kcal/mol. The obtained activation energy and selectivity between (000 anti 1)C and (0001)Si are quite similar to those for thermal oxidation. The carrier concentration hardly influences the etching rate up to 3 x 10{sup 19}cm{sup -3}, while crystal with a larger hexagonality shows a larger etching rate. (orig.) 12 refs.

Sublimation growth of 6H- and 4H-SiC single crystals in the [1 1¯0 0] and [1 1 2¯ 0] directions has been carried out by the modified-Lely method. Transport properties of the crystals in parallel and perpendicular directions to the [0 0 0 1] basal plane were examined by van der Pauw and resistance bar measurements using 5° off-oriented [0 0 0 1] samples. Van der Pauw resistance asymmetry significantly varied (1 to ⩾ 10 3 ) depending on the growth direction and the polytype of grown crystals, and resistivity anomaly along the off-direction was found for 6H [1 1¯ 0 0] grown crystals. The crystals contained a high density (⩾ 10 4 cm −1 ) of stacking faults lying in the basal plane, which largely hinder electron transport, giving rise to the resistivity anomaly. An atomistic surface model for the stacking fault generation is proposed and the influence of the growth direction and polytype is discussed.

Structural characterization of single crystalline α-SiC has been conducted by X-ray topography. Crystals were grown in the [0001¯] and the [11¯00] directions by the modified-Lely method, and wafers perpendicular and parallel to the growth directions sliced from the grown crystals were examined by transmission topographs of the Lang method. The crystals grown in the [0001¯] and the [11¯00] directions showed a significant difference in both types and densities of crystal defects. Each growth direction exhibited a peculiar defect formation, and the topography revealed that most of the defects were formed at the very initial stage of growth.

The formation of basal plane stacking faults in heavily nitrogen-doped 4H-SiC crystals was theoretically investigated. A novel theoretical model based on the so-called quantum well action mechanism was proposed; the model considers several factors, which were overlooked in a previously proposed model, and provides a detailed explanation of the annealing-induced formation of double layer Shockley-type stacking faults in heavily nitrogen-doped 4H-SiC crystals. We further revised the model to consider the carrier distribution in the depletion regions adjacent to the stacking fault and successfully explained the shrinkage of stacking faults during annealing at even higher temperatures. The model also succeeded in accounting for the aluminum co-doping effect in heavily nitrogen-doped 4H-SiC crystals, in that the stacking fault formation is suppressed when aluminum acceptors are co-doped in the crystals.

Stacking fault density was significantly reduced during seeded sublimation growth of silicon carbide (SiC) single crystals in the [110] direction by growing the crystals on a (110) seed crystal several degrees off-oriented toward . The density of the basal plane stacking faults rapidly decreased from 100–150 cm-1 to ~10 cm-1 as the degree of off-orientation was increased. The results indicate that the stacking fault formation is a kinetically induced process, and that the introduction of off-orientation prevents the stacking fault formation through modification of the surface growth kinetics.

The influence of stacking faults (SFs) on the performance of 4H–SiC (1120) Schottky barrier diodes fabricated on the epilayer grown on the substrate which was grown in [1120] direction by the sublimation method was investigated. The number of SFs under the Schottky electrode was determined by KOH etching of (1100) face cross section. SFs were found to have a severe influence on the leakage current of reverse characteristic and Schottky barrier height. The leakage current is increased even though a few SFs exist under the electrode. The Schottky barrier height is also affected by the SF under the electrode.

We discuss three applications of RHEED to the study of semiconductor film growth by MBE. In the first we discuss the extension of the vicinal plane method to the in-situ measurement of step propagation rates and show how they vary with growth parameters. The second concerns some apparent anomalies in the RHEED response to the growth of GaAs on GaAs(110) surfaces. Finally we consider surface chemical processes (reaction and segregation) in the growth of Si and SiGe alloys from molecular beams of Si 2 H 6 and GeH 4 . We demonstrate that the in-situ measurement of the growth rate on a monolayer-by-mono-layer basis can provide quite detailed chemical information.