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In this paper, we study the feasibility of using CMOS circuit blocks for designing future light weight, small in size atmospheric remote sensing receivers. A compact CMOS down-converter is designed which operates from 160 to 188 GHz and includes a sub-harmonically pumped I/Q resistive mixer, two IF amplifiers and a voltage controlled oscillator (VCO) with LO buffer. A measured down-conversion gain of +2.6 dB is achieved with a total dc power consumption of 152 mW using the nominal supply of +1.2 V. The measurement results show a 3 dB IF bandwidth from 1 to 5 GHz and the VCO tuning range is from 85 to 89 GHz. The designed CMOS MMIC down-converter including the probing pads occupies a silicon area of 0.575 mm2.

To improve the performance of G-band equipment for humidity sounding of the atmosphere, a high-gain and low-noise amplifier is needed. Here, the performances of 165 and 183 GHz low-noise amplifier microchips intended for atmospheric water vapor profiling application are reported. The microchips are manufactured in metamorphic high-electron mobility transistor technology having a gate length of 50 nm. The on-wafer measured results show noise figures of 4.4-7.4 dB and 16-25 dB gain at the operating frequencies. In addition, two of the amplifiers were assembled in waveguide packages and the measured results show a gain of 19-20 dB and 7 dB noise figure at both 165 and 183 GHz.

In this letter we report an ultra-low-noise amplifier module chain in the WR4 frequency range. The amplifier chips were fabricated in a 35 nm InP HEMT technology and packaged in waveguide housings utilizing quartz E-plane waveguide probes. When cryogenically cooled to 22 K and measured through a mylar vacuum window, the amplifier module chain achieves a receiver noise temperature of 87 K at 228 GHz and less than a 100 K noise temperature from 217 to 236 GHz. The LNA modules have 21–31 dB gain and the power dissipation is 12.4–15.8 mW. To the best of authors' knowledge, these are the lowest LNA noise temperatures at these frequencies reported to date.

In this work, we describe monolithic millimeter-wave integrated circuit (MMIC) Low Noise Amplifier (LNA) and mixer designs for U-Band, also known as the WR19 waveguide band (40–60 GHz). The LNAs were fabricated in NGC's 35 nm InP HEMT MMIC process. The MMICs were packaged in WR19 waveguide housings and tested for noise, both at room temperature and cryogenically. We present the results, including a comparison to the state-of-the-art, and discuss applications for amplifiers in this frequency range. To date, these are the first cryogenic 35 nm InP MMIC results covering the 40–60 GHz range. We achieved a noise temperature less than 30 K over the 40–60 GHz range, when the amplifiers were cryogenically cooled. These results are comparable with other results in the literature, and we believe are the lowest reported for MMICs in the 50–60 GHz range.

We have developed V-Band (50–75 GHz) monolithic millimeter-wave integrated circuit (MMIC) low noise amplifiers using NGC's 35 nm InP HEMT technology. The MMIC LNAs exhibit noise temperatures of 150–270K over the full waveguide band. Subharmonic MMIC mixers were also developed using United Monolithic Semiconductor's GaAs Schottky diode process, and cover V-band with 15–21 dB conversion loss. These components form the front end of receivers that could be used for radio astronomy. While much of V-Band is opaque to the atmosphere, a future space probe to map the intensity of carbon monoxide (CO) in V-band would help astronomers understand the early universe.

Wideband receivers for the 3-mm band were developed for CARMA, the Combined Array for Research in Millimeter wave Astronomy. Three cryogenic MMIC (monolithic microwave integrated circuit) amplifiers manufactured in InP 35-nm technology are combined in a block with waveguide probes and gain equalizers to cover the 80-116 GHz band. These are followed by a sideband-separating mixer that has two 17 GHZ wide outputs, for upper and lower sidebands. Each receiver has a feed horn followed by a circular-to-linear polarizer and orthomode transducer. The two polarizations are amplified by the cryogenic MMICs, and the outputs downconverted in sideband separating mixers, resulting in four 1-18 GHz channels that can be simultaneously correlated. The first receiver was tested in the lab, and on-sky tests conducted at CARMA. Measured noise temperatures were in the range 40-70 K, with a sideband rejection of about 15 dB.

This paper presents a 0.325-THz single-ended amplifier designed in a 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and utilizes staggered-tuning along with inductive feedback (drain to gate) technique to boost up the gain over a wide frequency band. Having a total power consumption of 28 mW, the amplifier achieves a peak gain of 4.5 dB at 325 GHz. To the best of authors' knowledge, this is the highest operation frequency demonstrated for a silicon amplifier up to date.

Due to copyright restrictions, the access to the full text of this article is only available via subscription. In this paper we discuss the design of low-noise amplifiers (LNAs) for both cryogenic and room-temperature operation in general and take the stability and linearity of the amplifiers into special consideration. Oscillations that can occur within a multi-finger transistor are studied and verified with simulations and measurements. To overcome the stability problem related to the multi-finger transistor design approach a parallel two-finger unit transistor monolithic microwave integrated circuit LNA design technique, which enables the design of wideband and high-linearity LNAs with very stable, predictable, and repeatable operation, is proposed. The feasibility of the proposed design technique is proved by demonstrating a three-stage LNA packaged in a WR10 waveguide housing and fabricated using a 35-nm InP HEMT technology that achieves more than a 20-dB gain from 75 to 116 GHz and 26-33-K noise temperature from 85 to 116 GHz when cryogenically cooled to 27 K. Jet Propulsion Laboratory, California Institute of Technology ; Oak Ridge Associated Universities under NASA Postdoctoral Program (NPP) ; Academy of Finland ; Alfred Kordel Foundation ; National Aeronautics and Space Administration

In this work, we describe new miniaturized low noise amplifier modules which we developed for incorporation in small-scale satellites or Cubesats, and which exhibit similar or better performance compared to previously reported LNAs in the literature. We have targeted the WR4 (170–260 GHz) and WR3 (220–325 GHz) waveguide bands for the module development. The modules include two different methods of E-plane probes which have been developed for low loss, and stability at high frequencies. MMIC LNAs were also developed for these frequency ranges and fabricated in Northrop Grumman Corporation's 35 nm InP HEMT technology, and we have experimentally verified that noise performance is lower than reported in prior work. The best results include a miniature LNA module with 550K noise at 224 GHz, and a wideband LNA module with 15 dB gain from 230–280 GHz.

We report on two-port on-wafer vector network analyzer measurements in the 325-508 GHz frequency band. Measurements are made with prototype GGB Industries Inc. WR2.2 (325-500 GHz) coplanar waveguide probes and OML Inc. WR2.2 frequency extenders. New probe performance data and characteristics of probe tip calibration using a Thru-Reflect-Line procedure are discussed. Probe S-parameter measurements indicate insertion loss per probe of 5.0 to 9.1 dB in the WR2.2 band. Calibrated dynamic range of about 30 dB or better for insertion and return loss measurement across the band is achieved. These new results for the prototype WR2.2 probes, the calibration procedure, observed errors, and results of on-wafer amplifier measurements are presented.

We present two W-band amplifiers, one implemented using conventional coplanar waveguides and unshielded passives and the other using slow-wave shielded waveguides and passives, realized in a 65-nm baseline CMOS technology. The measured results suggest that the slow-wave shielding of the passives is useful in achieving high performance and high frequency of operation. Our custom layout slotted plate capacitor employing slow-wave shield has low parasitic series resistance. Furthermore, as the substrate losses are minimal the modeling becomes more accurate. The measured based amplifier achieves +10 dBm output power at 100 GHz with a 1.2 V supply and 70 mA total DC-current consumption. The noise figure and gain at 100 GHz are 7.5 dB and 13 dB, respectively. The chip size of the implemented slow-wave amplifier is 0.33 mm2.

A three-stage V-band amplifier implemented in 65-nm baseline CMOS technology is presented in this paper. Slow-wave coplanar waveguides are used for matching and interconnects to study the benefits of using this line type in amplifier design. Measured power gain, noise figure and 1 dB output compression point at 60 GHz are 13 dB, 6.3 dB and +4 dBm, respectively. The amplifier has 19.6 GHz of 3 dB bandwidth, thus covering entirely the unlicensed band around 60 GHz. The performance is achieved with a 1.2 V supply and 45 mA DC current consumption.

In this paper we propose a methodology for fast modeling of shielded slow-wave coupled lines in CMOS technology. The simulation problem is divided into four parts with the help of placing a well-defined return current path for the even-mode signal propagation. The modeling technique is verified with measurement results from 10 MHz to 110 GHz of a slow-wave coupled line test structure. Furthermore, circuit design examples are given to support this study.

A compact 129–140 GHz Gilbert-cell mixer for up-conversion and 127–140 GHz image-rejection (IR) resistive mixer for down-conversion are realized for a 140-GHz transceiver in 28 nm bulk CMOS technology. A wide 7.5-GHz intermediate frequency (IF) tuning range is obtained for both mixers. The measurement results show a 6 to 12 dB conversion loss for the Gilbert-cell mixer with a layout size of 0.455mm2 including the probing pads where the core area is only 0.005mm2. The mixer consumes only 8 mW of DC power and exhibits better than 42 dB LO-to-RF isolation. The resistive mixer shows 20 dB image rejection ratio and better than 40 dB LO-to-RF suppression with only 0 dBm LO-power. The layout size of the mixer is 0.543mm2 including the probing pads.

This paper presents a 100-GHz vector-sum differential phase shifter in 28-nm CMOS FDSOI. Gilbert-cell type active switches are used to generate 0° and 180° out of phase signals and a 90° hybrid for obtaining I-Q signals. The hybrid is a compact capacitive loaded slow-wave differential branch-line coupler which is 75% smaller than a conventional 90° hybrid. The design has an area of 0.565 mm2 including RF and DC-bias pads with the total current consumption of 122.9 mA from a 1-V supply. The phase of the RF signal varies from 45° to 315° with a resolution of 90°. Measurements at 100 GHz show that the root-mean-square (RMS) gain and phase error are 1.5 dB and 13°, respectively. The input matching is better than −20 dB and the output matching is around −9 dB at 100 GHz. After redesigning the layout, a minimum RMS phase error of 1.7° is expected by simulations.

In this paper we propose a parallel two-finger unit transistor MMIC low-noise amplifier design technique which enables the design of wideband and high linearity low-noise amplifiers with very stable, predictable, and repeatable operation. We prove the feasibility of the proposed design technique by demonstrating a three-stage LNA packaged in a WR10 waveguide housing and fabricated using a 35-nm InP HEMT technology that achieves more than a 20-dB gain from 75 to 116 GHz and 26–33-K noise temperature from 85 to 116 GHz when cryogenically cooled to 27 K.

We report two resistive mixers, i.e., a balanced and a balanced image-rejection (IR) mixer for the 60-GHz frequency range. A compact and wide-band method for the local-oscillator (LO) power division is presented. The 56-GHz LO signal, which propagates in a coplanar-waveguide mode, is divided in between the lines of two spiral baluns. Consequently, a smooth and compact transition from even-to-odd propagation mode and an in-phase power division for two singly balanced unit mixers is achieved. As a result, the developed IR mixer occupies only 1.41mm/sup 2/ of chip area. The balanced design achieved 11.5 dB of conversion loss from 57 to 67 GHz with a fixed IF of 5.3 GHz. The corresponding LO suppression was better than 34 dB with 8 dBm of LO power. The IR mixer achieved better than 19 dB of IR ratio and better than 36 dB of LO suppression for an RF frequency from 57 to 66 GHz. The corresponding conversion loss varies from 13 to 16 dB. The measured 1-dB compression point of the IR mixer was at a -13-dBm output power level and the third-order intercept point was at a 4-dBm level.

This paper presents the design and corresponding measurement results of a W-Band differential I-Q phase shifter in 28-nm CMOS technology. Design of CMOS active switches and passive components like a 90° hybrid realized for differential I-Q operation are shown. The phase of the RF signal can be varied from 0° to 270° in steps of 90°. The measured input and output matching are better than −10 dB, and the maximum output imbalance is 0.8 dB with a maximum phase error of 19.6° at 100 GHz. Using a 1-V supply voltage, the total power consumption is 39 mW. The die area is 0.458 mm2.

This paper presents the design and characterization of W-band IQ sub-harmonic MMIC mixers based on the UMS BES Schottky diode process. The mixers were characterized at 300 K and 20 K physical temperature. They are a key component for the compact heterodyne multi-chip modules to be used in the 16-element Argus focal plane array, which will be deployed at the Green Bank Telescope in late 2014. The RF signal is split in quadrature using a Lange coupler, LO is split in-phase using a Wilkinson divider, and an antiparallel diode pair is used for the design of two sub-harmonically pumped mixer cells. The resulting IF outputs from the two cells are I and Q, which can be combined using an off-chip 90 degree hybrid to obtain LSB and USB. Three mixer designs are fabricated using this topology. A conversion loss between 12 to 18 dB is obtained over 80 to 120 GHz of RF for a fixed IF frequency, and over 10 GHz of IF for a fixed LO frequency. These mixers are designed to operate with low LO power without a significant loss in performance.

In this paper, we demonstrate non-destructive cryogenic probing of monolithic microwave integrated circuit (MMIC) amplifiers at W-band and discuss the implications for the development of large-format focal plane arrays for radio astronomy. Using a purpose-built cryogenic probe station to measure S-parameters and noise temperature of MMIC low-noise amplifiers (LNAs), an order of magnitude increase in efficiency can be achieved when compared with measurements on individually packaged amplifiers. The amplifiers are tested non-destructively, which enables selection based on cryogenic noise and gain; this is crucial for the development of highly-integrated miniaturized receivers for focal plane arrays, such as those used for the measurement of the cosmic microwave background (CMB) polarization and future arrays aimed at probing the epoch of reionization (EoR).

In this work, we report on developments toward ultra-low noise amplifier modules for the WR4 frequency range, covering 170-260 GHz. The amplifiers in question utilize 35 nm HEMT transistors on a 50 μm thick InP substrate, and were developed at NGC. While recent work in this frequency band has demonstrated the usefulness and advanced technology of utilizing integrated waveguide transitions fabricated on the high dielectric constant MMIC amplifiers themselves, we present evidence here that more standard, cost effective techniques like merging low-loss quartz probes with short wire bonds can provide excellent noise performance, even at these high frequencies. The amplifiers discussed in this paper demonstrate a record 600K noise (4.8 dB) at 220 GHz and 700K (5.2 dB) noise at 240 GHz.

To improve the performance of G-band equipment for humidity sounding of the atmosphere, a high-gain and low-noise amplifier is needed. Here we describe and report the performance of several low-noise amplifier microchips intended for 183-GHz water vapor profiling application. The chips are manufactured in metamorphic high electron mobility transistor technology having a gate length of 50 nanometers. The measured results show a noise figure of 4-7 dB and 15-22 dB gain from 170 to 200 GHz.

A compact and 3-dB bandwidth of 118-145-GHz Gilbert-cell mixer for up-conversion and a 1-dB bandwidth of 106-143-GHz image-rejection (IR) resistive mixer for down-conversion are designed for a 130-GHz transceiver in 28-nm CMOS technology. A wide 10-GHz intermediate frequency (IF) tuning range is obtained for both mixers. The simulated results show a +1.6-dB conversion gain for the Gilbert-cell mixer with a layout size of 720×633 μm2 and 6.1 mW of DC power consumption. An 11-dB conversion loss and 30-dB IR ratio are simulated for the resistive mixer with a layout size of 845×794 μm2. The simulated 1-dB output compression point is -8 dBm for the Gilbert-cell mixer and 1-dB input compression point is +9 dBm for the resistive mixer.

This paper presents the design of a W-Band I-Q phase shifter and the corresponding simulation results in 28-nm CMOS technology. The design of passive components like a 90° hybrid and transformers needed to realize differential I-Q operation is shown. The phase of the RF signal can be varied from 0° to 270° in steps of 90°. The simulated input and output matching are better than -10 dB, and the maximum phase error is roughly 10° with a maximum output imbalance of 0.5 dB at 90 GHz using a 1-V supply voltage. The total power consumption is 41 mW and the die area is 0.46 mm2.

In this paper we present the design and measurement results, both on-wafer and in package, of an ultra-low-noise and wideband monolithic microwave integrated circuit (MMIC) amplifier in the frequency range of 75 to 116 GHz. The three-stage amplifier packaged in a WR10 waveguide housing and fabricated using a 35-nm InP HEMT technology achieves a record noise temperature of 23 K at 108 GHz when cryogenically cooled to 27 K. The measured gain is 22 to 27 dB for frequency range of 75 to 116 GHz. Furthermore, the amplifier utilizes four-finger devices with a total gate width of 60 μm resulting in higher output power. Therefore, we consider that this amplifier achieves state-of-the-art performance in terms of bandwidth, noise temperature, gain, and linearity so far reported for cryogenically cooled amplifiers around W-band.

We present two low-noise amplifiers for the frequency range of 160 to 270 GHz. The amplifiers were fabricated using a 35-nm InP HEMT technology and designed for room temperature and cryogenic operation. A four-stage amplifier in a common-source topology and a three-stage amplifier utilizing a cascode stage at the output achieve 15 to 25-dB on-wafer measured gain from 160 to 270 GHz. When packaged in WR5 waveguide housings the amplifiers exhibit room temperature measured noise of 600 to 760 K from 160 to 220 GHz. When cryogenically cooled the three-stage amplifier shows a noise of 80 to 115 K over the range of 164 to 220 GHz. Furthermore, our initial room temperature measurements show a noise figure of 7-8 dB over the 220 to 252 GHz range for a four-stage amplifier packaged in a WR3 waveguide housing.

We currently achieve 3.4 dB noise figure at 183GHz and 2.1 dB noise figure at 90 GHz with our MMIC low noise amplifiers (LNAs) in room temperature. These amplifiers and the receivers we have built using them made it possible to conduct highly accurate airborne measurement campaigns from the Global Hawk unmanned aerial vehicle, develop millimeter wave internally calibrated radiometers for altimeter radar path delay correction, and build prototypes of large arrays of millimeter receivers for a geostationary interferometric sounder. We use the developed millimeter wave receivers to measure temperature and humidity profiles in the atmosphere and in hurricanes as well as to characterize the path delay error in ocean topography altimetry.

In this paper, we describe two monolithic millimeter-wave integrated circuit (MMIC) low noise amplifiers (LNAs) for W-Band which have a noise temperature of 30K or better over a wide bandwidth when cryogenically cooled. The LNAs were designed and fabricated in NGC's InP HEMT MMIC process having 35 nm gate length and employing an InAs Composite Channel (IACC). A two-stage amplifier exhibits room temperature S21 gain of 15–18 dB, and cryogenic gain of 20 dB with minimum noise temperature of 25K at 95 GHz, and less than 40K noise temperature between 75–105 GHz. A three-stage amplifier exhibits 29 dB of S21 gain, and a cryogenic noise temperature below 30K over the range of 94–109 GHz. We discuss the design of the amplifiers, measured and simulated S-parameters, and cryogenic measurements. To our knowledge, these are the highest frequency and lowest noise temperatures ever reported for InP cryogenic LNAs covering W-Band.

Development of a 120-GHz FMCW radar with a reflectarray as focusing element is described. The reflectarray is realized on a 150-mm silicon wafer and it has 3700 phase-modulating elements on it. The phase shifters have four discrete values to cover full phase modulation with 90° steps. The reflectarray element is realized with a conductor-backed coplanar waveguide patch antenna with a phase shifter coupled to it. The required phase modulation for each reflectarray element is determined with an in-house physical optics simulation combined with genetic-algorithm-based optimization. The reflectarrays are developed in two stages. First, preliminary reflectarrays with static phase shifters have been manufactured and tested at 120-GHz antenna measurement range. The static reflectarrays are found to perform as designed in their capability to steer the beam to a desired direction and to a distance of 3 m. The reflectarrays have -3-dB beam width from 1.1° to 1.3° depending on the beam tilt. After the preliminary verification with the static phase shifters, the reflectarrays will be assembled together with actively controlled MEMS-based phase shifters. The MEMS switches are controlled with dedicated high-voltage CMOS electronics, forming a system-in-a-package (SiP). First, the MEMS phase shifters are modeled, are being fabricated, and will be measured separately to verify their phase-shifting capability.

A power combining power amplifier utilizing cascode topology and transformer-based matching elements is presented in this paper. The amplifier achieves +13 dBm saturated output power at 94 GHz with a standard 1.2 V supply and occupies an active area of only 0.069 mm2. Amplifier is implemented in an industrial 65nm CMOS process taking into account reliability issues at high output power level. The amplifier is also ESD-protected at the input and at the output.

In this paper, 60-GHz receiver and transmitter front-ends implemented in 65-nm baseline CMOS are presented. Both down- and upconversion mixers employ a spiral transmission line balun for the local oscillator input, thus, creating a balanced mixer topology. The receiver has a balanced active mixer and a low noise amplifier on the same chip. The measured results show that the receiver has a 14.5-dB gain and a 9.2-dB double sideband noise figure with 53-GHz local oscillator and 1.5-GHz intermediate frequencies. The transmitter front-end consists of a balanced resistive mixer and a five-stage medium power amplifier. The mixer topology enables wideband LO-suppression as well as IF and RF responses. The measured upconversion gain and 1-dB output compression point at 60 GHz are 12 dB and −3 dBm, respectively. The saturated output power is +2 dBm. The chip sizes are 0.90 and 1.00 mm2 for the receiver and transmitter front-end, respectively.

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is −38.5 dBm.

A three-stage V-band amplifier implemented in 65-nm baseline CMOS technology is presented in this paper. Slow-wave coplanar waveguides are used for matching and interconnects to study the benefits of using this line type in amplifier design. Measured power gain, noise figure and 1 dB output compression point at 60 GHz are 13 dB, 6.3 dB and +4 dBm, respectively. The amplifier has 19.6 GHz of 3 dB bandwidth, thus covering entirely the unlicenced band around 60-GHz. The performance is achieved with a 1.2 V supply and 45 mA DC-current consumption.

We present design aspects and techniques for millimeter-wave circuits implemented in 65-nm CMOS. Different transmission line topologies are discussed and measurement results for a conventional coplanar waveguide and slow-wave coplanar waveguide implemented in 65-nm CMOS are shown. The attenuation of the on-chip transmission lines can be reduced by using slow-wave coplanar waveguides. A 1-stage cascode amplifier in 65-nm CMOS employing inductors as matching elements is presented. On-chip interconnections of the amplifier are implemented and modeled using coplanar waveguides. The ground plane of the coplanar waveguide provides a good ground reference for the entire circuit.

We report four low noise amplifiers for a 94 GHz cloud profiling radar. The LNAs are designed using coplanar waveguides and they were manufactured with a 100-nm metamorphic high electron mobility transistor technology. The chip sizes are 2.00 times 1.00 mm2 and 2.25 times 1.00 mm2. The gate width of the transistor is 4times15 mum. The scattering parameters and the noise figures of the amplifiers were measured at W-band and the results are presented. The measured gain at 94 GHz was 17-23 dB and the measured noise figure 3.0-3.3 dB using a 0.8 V drain-to-source voltage and a drain current of 8-16 mA per stage

We report integrated single-chip up- and downconverters for the 60-GHz frequency range. The size of the up- and downconverter chips is 3 mm times 1.5 mm. The 1-dB output compression point of the upconverter is from +1.0 to +5.5 dBm for an RF frequency from 57 to 63 GHz. The gain varies from 3.6 to 8.1 dB and the image rejection ratio is better than 12.7 dB. The downconverter exhibits a gain from 5.5 to 12 dB and an image rejection ratio from 10.6 to 18.7 dB for an RF frequency from 57 to 62 GHz

An OFDM transmitter with digital IF is demonstrated. The OFDM modulator is designed with an on-chip digital to analog converter. An image frequency mixer and an RF amplifier chain is realized partly with commercial GaAs MMIC circuits and partly with discrete transistors. About 10% power added efficiency in the power stage is achieved with ACPR level of -35 dB applying an A-class amplifier.

This paper describe the small signal properties of four 155 GHz low noise amplifiers (LNAs). The LNAs employs a 100-nm gallium arsenide based metamorphic high electron mobility transistors with gate length of 2times15 mum in coplanar waveguide topology. The scattering parameters and noise figures of the amplifiers are presented. The measured gains at 155 GHz are 14-22 dB with the measured noise figures of 6.7-7.2 dB.

We present a medium power amplifier covering frequency range from 18 GHz to 40 GHz and two low noise amplifiers for 94 GHz cloud profiling radar. These integrated amplifiers were manufactured using a 0.15 μm GaAs based metamorphic high electron mobility transistor (MHEMT) technology. We measured in on-wafer tests for the medium power amplifier, a small-signal gain of 22.5 ± 2.5 dB at K-and Ka-bands. The measured 1 dB output compression point is better than t13 dBm at K-band and better than +9.5 dBm at Ka-band using a 2.5 volts supply. The scattering parameters and the noise figures of the low noise amplifiers were measured at W-band and the results are presented. The best measured gain at 94 GHz was 16 dB and the noise figure 5.7 dB using a supply voltage of 25 V and current of 60 mA.

Four low noise amplifiers for 94 GHz cloud radar are presented. One LNA is designed using coplanar waveguides and the others use microstrip lines. The designed amplifiers were manufactured with a metamorphic high electron mobility transistor (MHEMT) technology and the chip size is 2.1 mm x 1.1 mm. The four stage LNAs have either 2x25 µm or 4x25 µm size MHEMTs. The scattering parameters and the noise figures of the amplifiers were measured at W-band and the results are presented. The best measured gain at 94 GHz was 16 dB and the noise figure 5.7 dB using a 2.5 V supply voltage and a drain current of 15 mA per stage. Furthermore, one of the amplifiers was assembled in a package that has WR-10 waveguide interfaces. The packaged chip exhibited 10.8 dB of gain and the noise figure was 8 dB at 94 GHz.

This paper presents an integrated power amplifier for the 60 GHz frequency range. The amplifier was fabricated with a commercially available 0.15 /spl mu/m gate length pseudomorphic HEMT process. The output stage consists of two 6/spl times/35 /spl mu/m PHEMTs, forming a total output periphery of 420 /spl mu/m. The MMIC amplifier was simulated, fabricated and measured both on-wafer and in a split block package. The amplifier was characterized using linear and nonlinear methods. The odd mode stability was carefully analyzed. Large-signal scattering parameters were measured with on-wafer probes. The measured gain was 13.4 dB and 1 dB output compression point was at +17 dBm power level using 3.0 V supply voltage. The AM/AM and AM/PM characteristics were extracted from the large-signal S-parameter results. Finally, the amplifier chip was mounted in a split block package, which has WR-15 wave guide input and output interface. The measured results show 12.5 dB small-signal gain and better than 8 dB return losses in input and output for the packaged amplifier chip.

This paper presents MMIC power amplifiers for 60 GHz broadband radio applications. These amplifiers have been fabricated using a commercially available 0.15 /spl mu/m GaAs pseudomorphic HEMT technology. The output compression point of the prototype three stage single ended amplifier was +15 dBm and the small signal gain, 12 dB. The improved version achieved 15.5 dB linear gain and +14 dBm compression point using 3 V supply voltage.

This work demonstrates a single-pole double-throw resonator switch designed at 250 GHz in 0.13-µm SiGe BiCMOS technology with ft/fmax of 300/500. The resonator switch demonstrates a minimum measured de-embedded insertion loss of 4.2 dB, maximum isolation of 29 dB and minimum input and output reflection coefficient of 16 dB and 20 dB, respectively. The resonator utilizes reverse saturated HBTs.

According to an example aspect of the present invention, there is provided an apparatus (200) for an antenna, comprising, a first power amplifier (220) and a second power amplifier (225) and a common ground (230) between the first power amplifier (220) and the second power amplifier (225), wherein a Radio Frequency, RF, output of the first power amplifier (220) is coupled to the common ground (230) and a RF output of the second power amplifier (225) is coupled to the common ground (230).Patent family as of 30.12.2022EP3963713 A120220309EP2020072488820200429 FI129952 B20221130FI2019000536620190503 FI20195366 A20201104FI2019000536620190503 US2022216837 AA20220707US2021060677720200429 WO20225476 A120201112WO2020FI50284Link to current patent family on right

This paper presents the design and measurement results of a W-band two-stage differential amplifier using transformers in 28-nm CMOS FDSOI. At 90 GHz, the amplifier achieves 13.8 dB gain, and the input and output return loss are −8.0 dB and −11 dB, repectively. The amplifier obtains +5 dBm saturated output power and 1-dB output compression point of 0 dBm at the centre frequency. From 85 to 95 GHz, the gain is better than 12.3 dB and the average noise figure (NF) is 8 dB. The design consumes 37.5 mW power from a 1-V supply and the active area of the design is 0.017 mm2.

This paper describes results obtained within the MMIC research activity at the Helsinki University of Technology (HUT). These MMICs were developed for a 60 GHz broadband radio front-end. A set of circuits is reported including power, low noise amplifiers, mixers and signal generation circuits. They have been fabricated with a commercially available 0.15 /spl mu/m GaAs pseudomorphic HEMT technology. Finally, the performance of the circuits was measured at 60 GHz frequency: The power amplifier has 14 dBm output compression point and 15.5 dB small signal gain. The low noise amplifier exhibits 24 dB of gain with 3.5 dB noise figure and the up-conversion mixer circuit has 12.7 dB of conversion loss.