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Firmware updates are often termed as a panacea to vulnerable Internet-of-Things (IoT) networks, as firmware updates can fix the exposed bugs and prevent them from being exploited in the future. However, a secure firmware update is a challenging task as IoT devices are often employed in unattended networks. Moreover, malicious updates of firmware in any of the devices of a network, or the non-execution of an update, can create havoc. Although security mechanisms like remote attestation (RA) are quite popular to identify malicious nodes in a network, they are costly in terms of computation/memory usage and communication overhead. To overcome these issues, we propose a “Secure Hardware-enabled Protocol for Firmware Updates (SHeFU)”. The aim of the proposed protocol is two-fold: 1) we obviate the need for remote attestation, and 2) we make sure that malicious nodes are isolated from benign nodes. Assuming a restricted threat model and network constellation, SHeFU ensures secure firmware updates and prevents compromised nodes from communicating with benign nodes in a network.

The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this paper, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.

Cryptographic pairings are important primitives for many advanced cryptosystems. Efficient computation of pairings requires the use of several layers of algorithms as well as optimizations in different algorithm and implementation levels. These makes implementing cryptographic pairings a difficult task particularly in hardware. Many existing hardware implementations fix the parameters of the pairing to improve efficiency but this significantly limits the generality and practicality of the solution. In this paper, we present a compact and programmable yet high-performance architecture for programmable system-onchip platforms designed for efficient computation of different cryptographic pairings. We demonstrate with real hardware that this architecture can compute optimal ate pairings on a Barreto- Naehrig curve with 126-bit security in 2.18 ms in a Xilinx Zynq- 7020 device and occupies only about 3200 slices, 36 DSPs, and 18 BRAMs. We also show that the architecture can support different types of pairings via microcode updates and can be implemented on other reprogrammable devices with very minor modifications.

The IPTV operators often uses set-top boxes as client-side devices. The IPTV middleware and application are integrated into the system firmware. The middleware focuses on processing the client message or error events such as, network, playback, thermal, and memory. To process new rules on those events or meet the business needs, the middleware has to be updated frequently which costs plenty of waiting time. In this research, we proposed a novel IPTV system which uses an event-triggered concept. The event and action can be deployed over the air independently and complete the quick setting proccess via the STB management system.

Recently, massive deployment of Internet of Things (IoT) devices has accelerated digital transformation of modern society in various aspects. Naturally, how to ensure security of deployed IoT devices has become an important and practical issue. Several successful large-scale DDoS attacks were utilized vulnerabilities of firmware on IoT devices in the past couple of years. Therefore, effective and efficient firmware update solution on IoT devices is in demand. In this study, an automatic real-time firmware update framework based on blockchain technology and MQTT protocol is proposed. To support automatic real-time firmware update operation on deployed IoT devices, multiple MQTT servers are installed in corresponding blockchain nodes to execute firmware patch delivery operation by the design of our framework. Blockchain technology is used to record the original manufacturer of a published firmware patch for a dedicated IoT device and smart contract is adopted to discover MQTT service nodes in a blockchain network. Data integrity of a newly generated firmware patch is preserved by distributing the patch with its hashed value. A framework prototype is constructed and experiments are conducted. Based on the experimental results, the proposed framework can efficiently and securely deliver firmware patches to targeted gateways in real-time scale.

This paper introduces a network microscope camera based on Hi3516A chip that uses 5GWi-Fi to transmit video flow. The purpose of this study is to meet the demand for stable and high-bandwidth video streaming transmission over the network. The paper uses 5G wireless network card chips: Broadcom’s BCM43569 chip or Realtek’s RTL8811CU chip on this microscope camera, cross-compiles their Linux drivers, and tests their network performance. For the convenience of firmware updating, this microscope camera also uses Mongoose tools to implement updating firmware via network. This microscope camera adopts the latest 80211AC protocol, through SoftAP (software enabled access point) and STA (station) mode, one camera can transmit video to multiple clients at the same time, which can be used for network teaching and micro imaging analysis.

This paper presents a semi-automatic methodology to create abstract driver models to be used as formal reference when developing the firmware for embedded device drivers. Our methodology extracts the behavior of driver software automatically as an abstract finite state machine. This replaces manually crafting these models from informal specifications, which is error-prone, laborious, and does not account for undocumented behavior. Our approach specifically targets untrusted driver software that is only available as binary code, for example as third-party IP, and for which the source code is unknown. Our extracted model is formally sound with respect to the implementation, while still being understandable by a human developer. Our experiments for industry-size driver software demonstrate that human-readable, sound, abstract driver models can be extracted from binary code in affordable run times and with small manual effort.

Dynamic frequency and voltage scaling features have been introduced to manage ever-growing heat and power consumption in modern processors. Design restrictions ensure frequency and voltage are adjusted as a pair, based on the current load, because for each frequency there is only a certain voltage range where the processor can operate correctly. For this purpose, many processors (including the widespread Intel Core series) expose privileged software interfaces to dynamically regulate processor frequency and operating voltage. In this paper, we demonstrate that these privileged interfaces can be reliably exploited to undermine the system’s security. We present the Plundervolt attack, in which a privileged software adversary abuses an undocumented Intel Core voltage scaling interface to corrupt the integrity of Intel SGX enclave computations. Plundervolt carefully controls the processor’s supply voltage during an enclave computation, inducing predictable faults within the processor package. Consequently, even Intel SGX’s memory encryption/authentication technology cannot protect against Plundervolt. In multiple case studies, we show how the induced faults in enclave computations can be leveraged in real-world attacks to recover keys from cryptographic algorithms (including the AES-NI instruction set extension) or to induce memory safety vulnerabilities into bug-free enclave code. We finally discuss why mitigating Plundervolt is not trivial, requiring trusted computing base recovery through microcode updates or hardware changes.

Microcode is an abstraction layer used by modern x86 processors that interprets user-visible CISC instructions to hardware-internal RISC instructions. The capability to update x86 microcode enables a vendor to modify CPU behavior in-field, and thus patch erroneous microarchitectural processes or even implement new features. Most prominently, the recent Spectre and Meltdown vulnerabilities were mitigated by Intel via microcode updates. Unfortunately, microcode is proprietary and closed source, and there is little publicly available information on its inner workings. In this paper, we present new reverse engineering results that extend and complement the public knowledge of proprietary microcode. Based on these novel insights, we show how modern system defenses and tools can be realized in microcode on a commercial, off-the-shelf AMD x86 CPU. We demonstrate how well-established system security defenses such as timing attack mitigations, hardware-assisted address sanitization, and instruction set randomization can be realized in microcode. We also present a proof-of-concept implementation of a microcode-assisted instrumentation framework. Finally, we show how a secure microcode update mechanism and enclave functionality can be implemented in microcode to realize a small trusted execution environment. All microcode programs and the whole infrastructure needed to reproduce and extend our results are publicly available., Published in ACM SIGSAC Conference on Computer and Communications Security (CCS'18)

Developing and implementing a remote lab based on FPGA can improve the teaching of Digital Electronics, giving students a web application to remotely test the designs proposed in practical sessions on real hardware. A server connected to the development system configures the programmable digital device with the proposed designs and allows the remote user to interact with the input and output peripherals. The server can manage connections and their time of use in order to avoid congestion of resources, and also allows usage statistics to be drafted.

This paper applies Model-Based Design methodologies to develop a high-performance device driver model suitable for advanced smart solutions. These modeling techniques are mandatory to use when designing advanced smart applications based on embedded devices. The paper proposes an innovative approach to accurately models the operations of the STM32 analog converter peripheral for both simulation purpose and to generate an optimized code that integrates on the Low-Level STM32 firmware driver. A new Simulink toolbox has been developed to replicate the ADC functions. Finally, an example has been presented to show the effectiveness of this new modeling approach.

Directional communication systems based on millimeter-wave phased arrays have reached a significant level of maturity and have entered the commercial space for 5G networks. In order to realize their full potential, Si -based phased arrays must be integrated efficiently at the system level with digital control electronics, firmware, and software. This paper describes key architecture approaches for such vertical integration from digital-RF co-integration in the IC to API definition in software. The important benefits of low-latency and versatile control of beam forming and radio functions from high-level APIs is illustrated with application examples at 28 GHz including directional channel sounding, spatio-temporal beamforming, and 3D imaging.

This poster introduces the Crypto Terminal, a new open device for securing blockchain wallets. This device includes a processor, a touch screen, a removable smartcard, and a Bluetooth Low Energy (BLE) module. Smartcard is the core security, it manages cryptographic procedures and keys. The terminal is bare metal, i.e. its firmware and the BLE firmware can be erased and uploaded at anytime. The software integrity of the programmer that performs these operations is checked by an innovative integrity probe. A use case is illustrated with a smartphone.

The recent Spectre attack first showed how to inject incorrect branch targets into a victim domain by poisoning microarchitectural branch prediction history. In this paper, we generalize injection-based methodologies to the memory hierarchy by directly injecting incorrect, attacker-controlled values into a victim’s transient execution. We propose Load Value Injection (LVI) as an innovative technique to reversely exploit Meltdown-type microarchitectural data leakage. LVI abuses that faulting or assisted loads, executed by a legitimate victim program, may transiently use dummy values or poisoned data from various microarchitectural buffers, before eventually being re-issued by the processor. We show how LVI gadgets allow to expose victim secrets and hijack transient control flow. We practically demonstrate LVI in several proof-of-concept attacks against Intel SGX enclaves, and we discuss implications for traditional user process and kernel isolation. State-of-the-art Meltdown and Spectre defenses, including widespread silicon-level and microcode mitigations, are orthogonal to our novel LVI techniques. LVI drastically widens the spectrum of incorrect transient paths. Fully mitigating our attacks requires serializing the processor pipeline with lfence instructions after possibly every memory load. Additionally and even worse, due to implicit loads, certain instructions have to be blacklisted, including the ubiquitous x86 ret instruction. Intel plans compiler and assembler-based full mitigations that will allow at least SGX enclave programs to remain secure on LVI-vulnerable systems. Depending on the application and optimization strategy, we observe extensive overheads of factor 2 to 19 for prototype implementations of the full mitigation.

This work introduces the CHEx86 processor architecture for securing applications, including legacy binaries, against a wide array of security exploits that target temporal and spatial memory safety vulnerabilities such as out-of-bounds accesses, use-after-free, double-free, and uninitialized reads, by instrumenting the code at the microcode-level, completely under-the-hood, with only limited access to source-level symbol information. In addition, this work presents a novel scheme for speculatively tracking pointer arithmetic and pointer movement, including the detection of pointer aliases in memory, at the machine code-level using a configurable set of automatically constructed rules. This architecture outperforms the address sanitizer, a state-of-the-art software-based mitigation by 59%, while eliminating porting, deployment, and verification costs that are invariably associated with recompilation.

Heterogeneous computing systems that integrate general-purpose processors with various types of application-specific accelerators are becoming mainstream. However, designing an efficient and flexible instruction set architecture (ISA) for a new accelerator is challenging. In this paper, we design a deep learning processing unit (DPU) as an example in order to explore a microcode-based control unit approach for application-specific accelerators. By removing the conventional ISA-based control logic and directly exposing the necessary control signals of the hardware blocks through a sequencer-based microprogrammed control unit, the functional capability of the accelerator is no longer limited by the ISA. Moreover, the design cycle can be shortened because the control logics are moved from hardware to firmware.

The work presented in this paper is on reconfigurable accelerators for the implementation of iterative computations and loops that form the core computations of applications like those in digital signal processing and machine learning. The accelerators become computation engines of an embedded system that can be reconfigured by an embedded processor for handling various kernels of embedded applications. This paper presents our MicroProgramed Configurable Accelerator (iMPAC) architecture and compares implementing a kernel (here a matrix multiplication) on this architecture with a) a program running of an embedded processor and b) with a hardwired controller accelerator. Our prototyping on an FPGA shows very little penalty in terms of energy consumption and required clock cycles when compared with the latter, and significant improvement of both energy and timing when compared with the former. At the same time, we have the programming flexibility of the former.

In applications where firmware updates are frequent, such as edge devices in the Internet of Things (IoT) networks with embedded systems, the update process is considered a significant role in improving device performance. This paper proposed a user insensible sliding firmware update technique based on a function block that reduces flash memory usage by handling only part of function blocks instead of the entire firmware, and device’s pause time by allowing the user to use the device between function block updates. The proposed technique was evaluated using the target board with the actual ARM core. As a result, the flash memory usage overhead was reduced by 63.64%, paused minimum time was reduced by 79.98% at once update process, and energy consumption reduced by 78.78%. We show that user insensible sliding firmware update has great potential for implementing IoT networks that change behavior quickly by being aware of the environment.

Nowadays, micro-programming of machines becomes more common. It is a technique used in several fields such as Computer Engineering. Here it is worth mentioning that micro-programming is employed throughout the design process. As well, designing the control unit of digital computers needs micro-programming, which is more complex than assembly languages. In this field, micro-programs can be written as sequences of micro-instructions. In this context, distinguished teaching of micro-programming of machines requires a suitable and carefully chosen Computer Simulation Tool (CST). This research designs a computer hardware project that introduces a special simulator achieving an easy-to-use microprogramming environment and a user-friendly simulation tool. This tool presents a visualization environment in order to display the execution behaviour of microprograms. It is a model/tool designed as a java program to ensure platform independence. This paper presents the Minimax simulator, which is used in the Minimax project. This project is a part of a hardware practical course. Therefore, it is a simulator for microprogramming and hardware simulation. As a result, this simulator facilitates the process of micro-programming significantly enabling students to understand easily how a computer works. Here, two formal measures and metrics were presented to assess the implemented program, the execution time and the program length. Other results of this study showed how self-organized group work and project management can be accomplished.

Today, embedded systems have taken a leading role in our world. Whether for communication, travel, work or entertainment, their use is preponderant. Together, research and industry efforts are constantly developing various parts that make up these systems: processor, FPGA, memory, operating system.From an architectural point of view, the contribution of a generalist architecture coupled with a reconfigurable architecture positions SoC FPGA as popular targets for use in embedded systems. However, their implementation's complexity makes their adoption difficult. The abstraction of low-level layers seems to be an investigation's axis that would tend to reverse this trend. The use of an operating system seems suitable at first glance because they deliver an ecosystem of drivers and services for access to hardware resources, native scheduling capacities and libraries for security. However, this solution brings constraints and lead to evaluate other approaches.This manuscript evaluates the ability of a high-level language, Lua, to provide an execution environment in such a case that the implementation does not provide operating system. It gives, through an ecosystem named Lynq, the necessary building blocks for the management and allocation of resources present on the SoC FPGA as well as a method for isolation between applications. Besides the adoption of this execution environment, our work explores the capacity of generalist architectures such as CPUs to become specialized when implemented on a FPGA. This is done through a contribution allowing the generation of a RISC-V CPU and its associated microcode.; Aujourd'hui, les systèmes embarqués ont pris une part hégémonique dans notre monde. Leurs utilisation est prépondérante, que ce soit pour communiquer, se déplacer, travailler ou se divertir. Des efforts dans le domaine de la recherche et de l'industrie n'ont de cesse de faire évoluer les parties qui composent ces systèmes dont le processeur, le FPGA, la mémoire et le système d'exploitation.D'un point de vue architectural, l'apport d'une architecture généraliste couplée à une architecture reconfigurable positionne le SoC FPGA comme une cible préférentielle pour une utilisation dans les systèmes embarqués. Leurs adoption est cependant difficile du fait de leur complexité d'implémentation. L'abstraction des couches de bas niveau semble un axe d'investigation qui tend à inverser cette tendance. Au premier abord, l'utilisation d'un système d'exploitation paraît idoine. En effet, il possède l'écosystème de drivers et services disponibles pour l'accès aux ressources matérielles, la capacité d'ordonnancement natif ainsi que des bibliothèques pour la sécurité. Toutefois, cette solution engendre des contraintes qui poussent à évaluer d'autres approches. Ce manuscrit évalue la capacité d'un langage de haut niveau tel que Lua à fournir un environnement d'exécution dans le cas d'une implémentation sans système d'exploitation.À travers un écosystème nommé Lynq, cet environnement d'exécution procure les briques nécessaires à la gestion et l'allocation des ressources présentes sur le SoC FPGA, ainsi qu'une méthode proposant une isolation entre applicatifs.La capacité des architectures généralistes que sont les CPUs à devenir spécialisés lorsqu'ils sont implémentés sur un FPGA a été exploré par la suite. Ceci au travers d'une contribution permettant la génération d'un CPU RISC-V ainsi que son microcode associé.

Transient execution is one of the most critical features used in CPUs to achieve high performance. Recent Spectre attacks demonstrated how this feature can be manipulated to force applications to reveal sensitive data. The industry quickly responded with a series of software and hardware mitigations among which microcode patches are the most prevalent and trusted. In this paper, we argue that currently deployed protections still leave room for constructing attacks. We do so by presenting transient trojans, software modules that conceal their malicious activity within transient execution mode. They appear completely benign, pass static and dynamic analysis checks, but reveal sensitive data when triggered. To construct these trojans, we perform a detailed analysis of the attack surface currently present in today's systems with respect to the recommended mitigation techniques. We reverse engineer branch predictors in several recent x86_64 processors which allows us to uncover previously unknown exploitation techniques. Using these techniques, we construct three types of transient trojans and demonstrate their stealthiness and practicality.

To offer protected and secure support to the clients and to do exchanges without going to bank. Each record holder has an exceptional ATM card, each having a unique account number. To abstain from compromising in ATM machines, this paper gives safe arrangements, for example, biometric authentication. ATM cards has the data about unique mark. The primary target of the venture work is to guarantee better security in ATM exchanges. Right now, use RFID tag rather than ATM card. If there should be an occurrence of three wrong endeavors in a day, the client can't play out the exchange.

This paper deals with firmware updates for embedded systems, more precisely with the update processing on target devices. It presents a new lightweight yet efficient patch module for differential updates. It also provides analysis and comparison of two update strategies, single-bank and dual-bank approach. Differential updates use delta files that encode only differences between firmware images and require different processing than standard full firmware image transfer. The designed module is written to be easily portable to different hardware platforms. It reduces the amount of memory pages that must be erased during an update to preserve durability of the memories. The paper describes the patch module, its take on the single and dual-bank approaches, discusses advantages and disadvantages of each approach and shows experimental results from its implementation for the nRF52840 system on a chip from Nordic Semiconductor. Contact authors of this paper for source code of the patch module.

Recent transient-execution attacks, such as RIDL, Fallout, and ZombieLoad, demonstrated that attackers can leak information while it transits through microarchitectural buffers. Named Microarchitectural Data Sampling (MDS) by Intel, these attacks are likened to "drinking from the firehose", as the attacker has little control over what data is observed and from what origin. Unable to prevent the buffers from leaking, Intel issued countermeasures via microcode updates that overwrite the buffers when the CPU changes security domains. In this work we present CacheOut, a new microarchitectural attack that is capable of bypassing Intel's buffer overwrite countermeasures. We observe that as data is being evicted from the CPU's L1 cache, it is often transferred back to the leaky CPU buffers where it can be recovered by the attacker. CacheOut improves over previous MDS attacks by allowing the attacker to choose which data to leak from the CPU's L1 cache, as well as which part of a cache line to leak. We demonstrate that CacheOut can leak information across multiple security boundaries, including those between processes, virtual machines, user and kernel space, and from SGX enclaves.

Today, embedded systems have taken a leading role in our world. Whether for communication, travel, work or entertainment, their use is preponderant. Together, research and industry efforts are constantly developing various parts that make up these systems: processor, FPGA, memory, operating system.From an architectural point of view, the contribution of a generalist architecture coupled with a reconfigurable architecture positions SoC FPGA as popular targets for use in embedded systems. However, their implementation's complexity makes their adoption difficult. The abstraction of low-level layers seems to be an investigation's axis that would tend to reverse this trend. The use of an operating system seems suitable at first glance because they deliver an ecosystem of drivers and services for access to hardware resources, native scheduling capacities and libraries for security. However, this solution brings constraints and lead to evaluate other approaches.This manuscript evaluates the ability of a high-level language, Lua, to provide an execution environment in such a case that the implementation does not provide operating system. It gives, through an ecosystem named Lynq, the necessary building blocks for the management and allocation of resources present on the SoC FPGA as well as a method for isolation between applications. Besides the adoption of this execution environment, our work explores the capacity of generalist architectures such as CPUs to become specialized when implemented on a FPGA. This is done through a contribution allowing the generation of a RISC-V CPU and its associated microcode., Aujourd'hui, les systèmes embarqués ont pris une part hégémonique dans notre monde. Leurs utilisation est prépondérante, que ce soit pour communiquer, se déplacer, travailler ou se divertir. Des efforts dans le domaine de la recherche et de l'industrie n'ont de cesse de faire évoluer les parties qui composent ces systèmes dont le processeur, le FPGA, la mémoire et le système d'exploitation.D'un point de vue architectural, l'apport d'une architecture généraliste couplée à une architecture reconfigurable positionne le SoC FPGA comme une cible préférentielle pour une utilisation dans les systèmes embarqués. Leurs adoption est cependant difficile du fait de leur complexité d'implémentation. L'abstraction des couches de bas niveau semble un axe d'investigation qui tend à inverser cette tendance. Au premier abord, l'utilisation d'un système d'exploitation paraît idoine. En effet, il possède l'écosystème de drivers et services disponibles pour l'accès aux ressources matérielles, la capacité d'ordonnancement natif ainsi que des bibliothèques pour la sécurité. Toutefois, cette solution engendre des contraintes qui poussent à évaluer d'autres approches. Ce manuscrit évalue la capacité d'un langage de haut niveau tel que Lua à fournir un environnement d'exécution dans le cas d'une implémentation sans système d'exploitation.À travers un écosystème nommé Lynq, cet environnement d'exécution procure les briques nécessaires à la gestion et l'allocation des ressources présentes sur le SoC FPGA, ainsi qu'une méthode proposant une isolation entre applicatifs.La capacité des architectures généralistes que sont les CPUs à devenir spécialisés lorsqu'ils sont implémentés sur un FPGA a été exploré par la suite. Ceci au travers d'une contribution permettant la génération d'un CPU RISC-V ainsi que son microcode associé.

An Unmanned Aerial System (UAS) Flight Control System (FCS) is an example of a Cyber Physical System (CPS), in that it integrates computation, networking, and the control of a physical system, i.e., the aircraft. An FCS contains a Central Processing Unit (CPU), typically in the form of a microcontroller, referred to as the autopilot, connected to many subsystems to measure its environment, including accelerations, angular rates, dynamic and absolute pressures, and position. The autopilot periodically extracts data from the on-board sensors and processes those using navigational algorithms. The results of these computations are used to position actuators connected to the control surfaces of the UASs, causing it to fly in a correct way to perform the required mission. This process is performed in real-time, typically at the rate of 50 Hz or more. Any interruption or corruption of this process can cause the UAS to fail to perform its mission, or ultimately crash and be destroyed. This can result in significant loss of property, or even loss of life. A security compromised UAS can pose a serious threat, and the security vulnerabilities in their control system need to be minimized, if not completely eliminated [1].

Modern system-on-chip (SoC) designs comprise programmable cores, application-specific accelerators, and I/O devices. Accelerators are controlled by software/firmware and functionality is implemented by this combination of programmable cores, firmware, and accelerators. Verification of such SoCs is challenging, especially for system-level properties maintained by a combination of firmware and hardware. Attempting to formally verify the full SoC design with both firmware and hardware is not scalable, while separate verification can miss bugs. A general technique for scalable system-level verification is to construct an abstraction of SoC hardware and verify firmware/software using it. There are two challenges in applying this technique in practice. Constructing the abstraction to capture required details and interactions is error-prone and time-consuming. The second is ensuring abstraction correctness so that properties proven with it are valid. This paper introduces a methodology for SoC design and verification based on the synthesis of instruction-level abstractions (ILAs). The ILA is an abstraction of SoC hardware which models updates to firmware-visible state at the granularity of instructions. For hardware accelerators, the ILA is analogous to the instruction-set architecture definition for programmable processors and enables scalable verification of firmware interacting with hardware accelerators. To alleviate the disadvantages of manual construction of abstractions, we introduce two algorithms for synthesis of ILAs from partial description called templates. We then show how the ILA can be verified to be correct. We evaluate the methodology using a small SoC design consisting of the 8051 microcontroller and two cryptographic accelerators. The methodology uncovered 15 bugs.

Function recognition is the preliminary step of the reverse analysis. It is the premise of binary reuse, generating control flow graphs, and performing semantic analysis. There are still many shortcomings in the application of current function identification tools, including cross-platform support, efficiency, and resource usage. To improve the accuracy and efficiency of function recognition in embedded system firmware, this paper proposes a new function recognition algorithm FRwithMBA based on the structure information. With the help of function call resolve, FRwithMBA identifies functions by determining the termination position of the function based on branches instruction and termination signatures of the function. In the experiment, we evaluated FRwithMBA against IDA Pro, radare2, and angr with the router binary Cisco IOS and found that FRwithMBA is more effective in identifying functions in the stripped binary under PPC and MIPS than the other tools. In terms of recognition effectiveness, FRwithMBA performs a little better than IDA Pro, but the results of radare2 and angr are poor. For a 14-MB binary, the parsing time of IDA Pro is 178 s, radare2 uses 376 s, angr uses 1896 s, and FRwithMBA uses 25 s. When processing 220-MB Executable and Linkable Format files, FRwithMBA can identify nearly 420 000 functions in about 240 s, IDA takes 2754 s, and both radare2 and angr get a fault. In the experiment, the recall of FRwithMBA reached 99.99% and the precision reached 99.7%. It is better than the other tools. In other words, FRwithMBA has more speed, higher accuracy, and less resource occupation.

Always-on Internet-connected devices [the so-called Internet of Things (IoT)] have become common tools deployed throughout the cement industry. As plant managers employ more automation technologies, the implementation of more connected devices can lead to information security and personnel safety concerns. IoT devices provide significant value in cost reduction, increased efficiency, and greater visibility for all aspects of the business. Along with the benefits of the IoT infrastructure, there are significant security concerns and challenges present in the deployment of this new technology. Recent implementations of IoT devices have shown a significant gap between actual application and best practices, exposing an organization to risks such as sensitive data exfiltration, malicious attackers, and potential safety issues (including the loss of life). An awareness of these concerns and challenges provides guidance to plant managers for mitigating the security weaknesses contained within connected devices while still reaping the benefits of the IoT infrastructure.

Anti-counterfeiting tags are a simple and easy way to avoid duplication/forgery of valuable products; however, counterfeiting has evolved over time, with the help of newer technologies to clone and reproduce exact signatures, tags, barcodes, etc that are difficult to identify. To prevent such counterfeiting, it is imperative to obtain advanced and encoded anti-counterfeiting technologies with constant research and innovation. With this motivation, we have designed a sub-micron-scale patterned, fluorescent anti-counterfeiting tag based on an emissive layer embedded in a non-emissive polymer layer. The fabrication of the embedded structure is achieved using step-by-step writing of emissive and non-emissive layers using two-photon lithography. Interestingly, the encoded message is visible under ultraviolet illumination, and the structure is invisible under white light illumination. The proposed method can be extended for multilayer patterning with spatial positioning of different encoded messages along the height of the structure to incorporate layered security.

Solid-state drives (SSDs) based on NAND flash are making deep inroads into data centers as well as the consumer market. In 2016, manufacturers shipped more than 130 million units totaling around 50 Exabytes of storage capacity. As the amount of data stored on solid state drives keeps increasing, it is important to understand the reliability characteristics of these devices. For a long time, our knowledge about flash reliability was derived from controlled experiments in lab environments under synthetic workloads, often using methods for accelerated testing. However, within the last two years, three large-scale field studies have been published that report on the failure behavior of flash devices in production environments subjected to real workloads and operating conditions. The goal of this paper is to provide an overview of what we have learned about flash reliability in production, and where appropriate contrasting it with prior studies performing controlled experiments.

For the formation of a professional in engineering, it is necessary that the knowledge gained in the classroom can be applied in practice. Based on this issue, this paper reports the study and development of a prototype that uses prototyping tools and creating an Android application capable of performing reading analog variables and hardware control via Bluetooth communication to be used in laboratory teaching . The study on the theoretical foundation involves the review of concepts from the application of practical teaching labs to the technology areas related to the project, such as Arduino and Android platforms. The work continues with the prototype development methodology, which are detailed all stages of development of the proposed system, the components that constitute the programming tools used and the final results of the prototype already in operation. Throughout the article, we report the tests to validate the prototype and the results obtained. Finally, we observe them design features and the feasibility of its application in academia.

Verification of modern microprocessors is a complex task that requires a substantial allocation of resources. Despite significant progress in formal verification, the goal of complete verification of an industrial design has not been achieved. In this paper, we describe a current contribution of formal methods to the validation of modern x86 microprocessors at Centaur Technology. We focus on proving correctness of instruction implementations, which includes the decoding of an instruction, its translation into a sequence of micro-operations, any subsequent execution of traps to microcode ROM, and the implementation of these micro-operations in execution units. All these tasks are performed within one verification framework, which includes a theorem prover, a verified symbolic simulator, and SAT solvers. We describe the work of defining the needed formal models for both the architecture and micro-architecture in this framework, as well as tools for decomposing the requisite properties into smaller lemmas which can be automatically checked. We additionally cover the advantages and limitations of our approach. To our knowledge, there are no similar results in the verification of implementations of an x86 microprocessor., Pre-Print of CPP2020 Paper

Speculative-execution attacks, such as SgxSpectre, Foreshadow, and MDS attacks, leverage recently disclosed CPU hardware vulnerabilities and micro-architectural side channels to breach the confidentiality and integrity of Intel Software Guard eXtensions (SGX). Unlike traditional micro-architectural side-channel attacks, speculative-execution attacks extract any data in the enclave memory, which makes them very challenging to defeat purely from the software. However, to date, Intel has not completely mitigated the threats of speculative-execution attacks from the hardware. Hence, future attack variants may emerge. This paper proposes a software-based solution to speculative-execution attacks, even with the strong assumption that confidentiality of enclave memory is compromised. Our solution extends an existing work called HyperRace, which is a compiler-assisted tool for detecting Hyper-Threading based side-channel attacks against SGX enclaves, to thwart speculative-execution attacks from within SGX enclaves. It requires supports from the untrusted operating system, e.g., for temporarily disabling interrupts, but verifies the OS's behaviors. Additional microcode upgrades are required from Intel to secure the attestation flow.

The advent of Ultra High Definition (UHD) and Super Hi-Vision (SHV) videos has motivated the development of advanced video coding standard in these years. Integer motion estimation (IME) is the most computationally expensive process of High Efficiency Video Coding (HEVC), which is one of the most widespread video coding standards. Many previous works related to IME put emphasis on enlarging search range and improving computation complexity. However, the fact that the IME algorithm should be adaptive to different scenarios was neglected. In view of this, a configurable IME engine and its micro-code-based hardware design are proposed in this paper. Three different search schemes based on our IME engine are evaluated using the HEVC test model (HM) 16.9, achieving an average BD-rate increase of 0.55/-0.07/-0.14%. The hardware design is implemented with 225. 7K gates at 500MHz using TSMC 65nm CMOS standard-cell libraries.

An implementation of an adapter that bridges the Wi-Fi network to a standard UART interface is shown in this paper. A network processor could be attached to any existing microcontroller and could expose any UART-based bootloader to the rest of the world. The motivation behind this research is the Internet-of-Things (IoT) trend and targets firmware development.

The work presented in this paper focuses on a port development of a software driver for flashing MSP430 microcontrollers. The bootloader data stream is channeled over the wi-fi. To do this, one must have a proper bridge device that will connect a UART interface to the Internet and a high-level flashing application.

Internet of Things (IoT) is one of the key enabling technologies for an always-connected world and also a main enabler for generating information of interest in various application domains. A growing problem in recent years in this technology is security, as power-constrained devices that are typical of IoT applications may not always provide these implementations properly. These conditions can compromise entire environments and allow malicious agents to take control and perform malicious activities. In this article, we provide a summary of the principal vulnerabilities reported for IoT devices based on the OWASP Internet of Things Project, classified by test routine groups. Using models based on standard architectures to define and detail reproducible verification routines for each test, a selection of independent analyzes of each identified category was performed to ensure more comprehensive and accurate testing. Finally, the proposed routines are performed in a test environment to exemplify and ensure their operation, thus contributing to meeting the demand in the area for more accurate information and to assist in understanding the most common vulnerabilities.

With the continuous improvement of automobile electronization, the number of on-board ECU and the amount of software code in Car also increase greatly. The numerous and geographically dispersed on-board ECU and the increasing amount of code make on-board ECU firmware upgrades a huge challenge in terms of staffing, time and geographical management. This paper designs a communication protocol EVUGP that supports remote firmware upgrade, and introduces the protocol model, communication mechanism and frame structure of EVUGP, and provides a reliable and effective implementation mechanism for remote upgrade operation of on-board EUC firmware and related data.

Traditional display protocols have limitations in terms of fixed refresh-rates, high bandwidth requirements, and control over the display of frames. This paper demonstrates the performance results of an alternative approach utilizing a packetized display protocol architecture incorporating dynamic refresh-rates, high-speed capabilities, to bridge performance gaps.

In this paper, a new method of usage forensics memory analysis for compromising the carrier-lock algorithm was proposed. The firmware of one popular 3G modem for security issues is investigated. A binary file is reverse engineered using IDA Pro Disassembler and the carrier-lock code algorithm is found. The reproduction of arithmetic and bitwise ARM commands under the IMEI to obtain the unlock code by way of just reverse engineering become impossible because of the algorithm complexity. Therefore the existed ARM code was used to generate the unlock codes on the fly via memory forensics technique and JTAG debugger. A new method was successfully tested on a set of different modem versions.

As Internet of Things (IoT) applications are getting attention these days, the importance of firmware security is also growing. However, it is not straightforward to analyze the bugs or vulnerabilities that reside in firmware. One of the major challenges is to detect information about hardware architectures of compressed firmware. Traditional analysis tools make use of static signatures embedded in the compressed binary code of firmware. However, signature extraction needs the careful elaboration of experts, and it is not always even possible. In this paper, we introduce our experience in analyzing the hardware information of compressed firmware. Since it is not possible to use the semantic information of compressed binary code, we adopt machine learning technologies for this purpose. Despite various difficulties, we have positive experimental results.

This paper describes context-sensitive fencing (CSF), a microcode-level defense against multiple variants of Spectre. CSF leverages the ability to dynamically alter the decoding of the instruction stream, to seamlessly inject new micro-ops, including fences, only when dynamic conditions indicate they are needed. This enables the processor to protect against the attack, but with minimal impact on the efficacy of key performance features such as speculative execution. This research also examines several alternative fence implementations, and introduces three new types of fences which allow most dynamic reorderings of loads and stores, but in a way that prevents speculative accesses from changing visible cache state. These optimizations reduce the performance overhead of the defense mechanism, compared to state-of-the-art software-based fencing mechanisms by a factor of six.

The paper introduces a method of efficient partial firmware update with several advantages compared to common methods. The amount of data to transfer for an update is reduced, the energetic efficiency is increased and as the method is designed for over the air update, the radio spectrum occupancy is decreased. Herein described approach uses Lua scripting interface to introduce updatable fragments of invokable native code. This requires a dedicated memory layout, which is herein introduced. This method allows not only to distribute patches for deployed systems, but also on demand add-ons. At the end, the security aspects of proposed firmware update system is discussed and its limitations are presented.

A distributed energy resource prototype is used to show cybersecurity best practices. These best practices include straightforward security techniques, such as encrypted serial communication. The best practices include more sophisticated security techniques, such as a method to evaluate and respond to firmware integrity at run-time. The prototype uses embedded Linux, a hardware-assisted monitor, one or more digital signal processors, and grid-connected power electronics. Security features to protect communication, firmware, power flow, and hardware are developed. The firmware run-time integrity security is presently evaluated, and shown to maintain power electronics uptime during firmware updating. The firmware run-time security feature can be extended to allow software rejuvenation, multi-mission controls, and greater flexibility and security in controls.

In this paper, a novel system-on-chip (SoC) based software defined radio (SDR) platform is presented. This platform addresses the challenges of software defined processing and rapid prototyping in the micro- and millimeter wave frequency region. After presenting the mentioned challenges and system requirements as well as an overview of the SDR platform, the interface between the processing system and the programmable logic is discussed in detail. Application references for ultra-high data rate 60 GHz communication systems, 120 GHz pseudo-noise MIMO radar as well as high resolution ranging and localization systems are given.