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International audience; This paper is a review of recent progress of RD53 Collaboration. Results obtained onthe study of the radiation effects on 65 nm CMOS have matured enough to define first strategies toadopt in the design of analog and digital circuits. Critical building blocks and analog very frontend chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64 64pixels with complex digital architectures have been produced, and point to address the main issuesof dealing with extremely high pixel rates, while operating at very small in-time thresholds in theanalog front end. The collaboration is now proceeding at full speed towards the design of a largescale prototype, called RD53A, in 65 nm CMOS technology

This work is concerned with the experimental characterization of a Charge Sensitive Amplifier featuring dynamic signal compression, fast recovery time, low noise and reduced area occupancy. The device takes advantage of the non-linear features of an inversion-mode MOS capacitor to fit a wide input dynamic range into the available output swing. It can be operated in synchronous mode at high frame rates, of the order of few MHz, thanks to a wide bandwidth, an improved output stage and a fast reset network. The reduced area occupancy makes the amplifier suitable for integration in a 100x 100 μm2 pixel area. All these features make the device a good candidate for applications where a fast front-end with a non-linear response is required, such as in imaging instrumentation for Free Electron Laser experiments. The aim of the paper is to show the experimental results coming from the characterization of the first prototype of the circuit which has been designed in a 65 nm CMOS technology. within the PixFEL Project funded by the INFN, Italy.

This work presents the characterization results of the first prototype of a readout channel for silicon pixel detectors, developed by the PixFEL collaboration in view of future X-ray Free Electron Laser (FEL) applications. The circuit, fabricated in a 65 nm CMOS technology by TSMC, has been designed to deal with a maximum input signal of 104 photons with energy from 1 keV to 10 keV, by exploiting a non-linear technique implemented at front-end level. Moreover, it has been envisioned for operation with the demanding frame rates of next generation FEL facilities, which can reach a few MHz. This paper presents results from measurements performed on the building blocks of the readout processor, along with a summary of the overall performance of the complete readout channel.

A readout chip, consisting of 32×32 square cells, has been designed in a 65 nm CMOS technology. The circuit will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager, envisaged for applications to experiments at the next generation X-ray FELs. The pixel pitch is 110 μm, for a total area of about 16 mm2. Different solutions for the readout channel, which includes a charge preamplifier, a time-variant filter and a 10 bit ADC, have been integrated in the chip. In particular, a couple of different versions for the time-variant processor have been implemented. The charge preamplifier is provided with four different gain settings, therefore improving the system capability to comply with photon energies in the 1 keV to 10 keV interval. This work, besides discussing in detail the readout channel and array architecture, will present the first results from the chip characterization.

The objective of this work is to design a high performance bandgap voltage reference circuit in a standard commercial 65 nm CMOS technology capable of operating in harsh radiation environments. A prototype circuit based on three different devices (diode, bipolar transistor and MOSFET) was fabricated and tested. Measurement results show a temperature variation as low as ±3.4 mV over a temperature range of 170 ° C (−30 °C to 140 °C) and a line regulation at room temperature of 5.2%/V. Measured V REF is 690 mV±15 mV (3 σ ) for 26 samples on the same wafer. Circuits correctly operate with supply voltages in the range from 1.32 V down to 0.78 V. A reference voltage shift of only 7.6 mV (around 1.1%) was measured after irradiation with 10 keV X-rays up to an integrated dose of 225 Mrad (SiO 2 ).

Three-dimensional monolithic pixel sensors have been designed following the same approach that was exploited for the development of the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous layers fabricated in a 130 nm CMOS technology. One of the two tiers, which are face-to-face bonded, has to be thinned down to about View the MathML source to expose the through silicon vias connecting the circuits to the back-metal bond pads. As a consequence of the way the two parts of each single chip are designed and fabricated, the prototypes of the 3D monolithic Detector will include both samples with a thick substrate underneath the collecting DNW electrode, suitable for charged particle tracking, and samples with a very thin (about View the MathML source) sensitive volume, which may be used to detect low energy particles in biomedical imaging applications. Device physics simulations have been performed to evaluate the collection properties and detection efficiency of the proposed vertically integrated structures.

In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60 Co γ -rays . A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers. Results from static and noise measurements are used to collect further evidence for a static and noise degradation model involving charge buildup in shallow trench isolations and lateral parasitic transistor activation. Comparison between two CMOS processes both belonging to the 90 nm node but coming from different foundries makes it possible to shed some light on the process-dependent features of the device response to ionizing radiation.

Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

The large scale of integration provided by CMOS processes with minimum feature size in the 100 nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, processes with 130 nm minimum channel length are widely available for Application Specific Integrated Circuits (ASICs) design, nonetheless designers are considering more scaled technologies following the trend of commercial silicon foundries. This work provides an extensive analysis of the noise performance which can be attained by detector front-end circuits in a 65 nm CMOS process. The behavior of the 1/f and white noise terms in this technology node is studied as a function of the device polarity, of the gate length and width and of the bias conditions. A comparison with data from previous CMOS generations is also carried out to evaluate the impact of scaling down to the 65 nm node.

A low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12 GeV/ c protons at the PS-T9 beam line at CERN. Two devices were placed inside a reference telescope and their characteristics were measured. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS technology, providing digital sparsified readout. The other one was a high resistivity double-sided silicon detector, with short strips at a 45 ∘ angle to the detector's edge, read out by the FSSR2 chip. In this paper we describe the main features of both sensors. The primary goal of the test was to measure the efficiency and the resolution of the DUTs under different conditions of threshold setting and incident angle of the impinging particles. The data-driven approach of the readout chips has been fully exploited by the DAQ system to take data with a track-based level-1 trigger provided by a pattern matching algorithm with very low latency.

This paper is devoted to the study of total ionizing dose effects in deep N-well (DNW) CMOS monolithic active pixel sensors (MAPS) for particle tracking fabricated in a STMicroelectronics 130 nm process. DNW-MAPS samples were exposed to gamma-rays up to a final dose of 1100 krad(SiO2) and then subjected to a 100degC annealing cycle. Ionizing radiation tolerance was tested by monitoring the device noise properties and its response to charge injection through an external pulse generator throughout the irradiation and annealing campaign. The origins of performance degradation are discussed based on the results from radiation hardness characterization of single transistors belonging to the same CMOS technology and of test diodes reproducing the MAPS collecting electrode structure. Also circuit simulations have been performed to supply further evidence for the proposed degradation mechanisms.

Low noise design of charge sensitive amplifiers in deep submicron CMOS technologies is discussed based on the experimental characterization of transistors belonging to a 130 nm and a 90 nm minimum channel length processes. After briefly examining the main preamplifier noise sources, residing in the input element, achievable resolution limits in charge measuring systems employing such technologies are discussed under different detector capacitance, processing time and power dissipation constraints. The equivalent noise charge (ENC) model adopted in this work takes into account the behavior of series 1/f noise as a function of the overdrive voltage in PMOS devices. Moreover, noise in the gate current, whose effects could be neglected in past CMOS technologies featuring larger gate oxide thickness, is shown to play a role in the optimization process, significantly affecting the preamplifier performance at long shaping times. The extent of this contribution, besides depending on the drain current in the input device, is also determined by its drain voltage, which therefore may become a critical parameter in the design of low noise analog blocks.

130 nm and 90 nm CMOS processes are going to be used in the design of mixed-signal integrated circuits for the readout of detectors in the future generation of HEP experiments. In applications such as inner SLHC detectors, these ultra-deep submicron systems will have to stand total doses of ionizing radiation of the order of 100 Mrad and beyond. While the scaling of the gate oxide thickness to about 2 nm gives a high degree of radiation tolerance, issues such as the gate tunneling current and the sidewall leakage associated to lateral isolation oxides must be investigated. This paper provides an analysis of an extensive set of irradiation tests carried out on 130 and 90 nm CMOS transistors belonging to commercial technologies. With special focus on the design of analog front-end circuits for silicon pixel and strip detectors, the impact of ionizing radiation on the noise performance is evaluated and the underlying physical degradation mechanisms are pointed out to provide criteria for improving radiation hardness properties.

In future charged particle tracking systems, readout integrated circuits will be based on CMOS processes with minimum feature size in the 100 nm range. In nanoscale technologies, the reduction of the gate oxide thickness may lead to a non-negligible gate current due to direct tunneling phenomena. This leakage current, which is caused by discrete charges randomly crossing a potential barrier, yields an increase of the static power consumption for the digital section of the readout circuits and might degrade the noise performances of the analog front-end. As a consequence, in these advanced CMOS processes, an accurate characterization of the gate current noise is necessary in order to establish design criteria for detector analog front-end applications. This work presents the results of static and noise characterization of the gate-leakage current of NMOS devices belonging to a 90 nm commercial process. Data extracted from the measurements have been used to validate an analytical model for the gate current noise, which provides a useful tool for evaluating the impact of this noise source on the resolution limits achievable by low-noise charge amplifiers.

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

This paper is intended to discuss the features of a novel kind of monolithic active pixel sensors (MAPS) in deep submicron CMOS technology (130 nm minimum feature size) for use in charged particle trackers and vertex detectors. As compared to conventional MAPS with 3-transistor readout scheme, the design approach proposed here, where a deep N-well (DNW) is used as the collecting electrode, lends itself to pixel-level sparsified processing and is expected to provide the ability to manage the large data flow of information anticipated for future, high luminosity colliders. Lately, the applicability of the DNW-MAPS concept to the design of the vertex detector for future high luminosity colliders, like the International Linear Collider (ILC), has been investigated. This paper will discuss the design and performance of a recently submitted DNW monolithic sensor, the SDR0 (Sparsified Digital Readout) chip, including different test structures, where both analog (charge amplification and threshold discrimination) and digital (sparsification, time stamping) functions have been integrated inside the elementary sensor, as large as 25 μ m × 25 μ m .

We developed monolithic active pixel detectors, by exploiting the triple well option available in a deep-submicron CMOS process. The novel features are the full analog signal processing and digital functionality implemented at the pixel level. The charge collecting element is realized using the deep N-well (DNW), the full in-pixel signal processing chain includes charge preamplifier, shaper, discriminator and latch. We report on the characterization of the two prototype chips, the first (APSEL0) containing single-channel sensors, with different collecting electrode area, and the latter (APSEL1) with several single pixel structures with improved noise figure implementing also an 8 × 8 matrix of 50 × 50 μm 2 pixel area. So far, the pixel matrix has a simple row by row readout, successfully tested with clock frequency up to 30 MHz. The response of the sensors to infra-red laser, β -rays and soft X-rays (from radioactive sources, 90 Sr and 55 Fe respectively) will be presented. The results achieved so far demonstrate the viability of the technology and suggest new design improvements implemented in the next prototype chips submission (APSEL2).

By exploiting the triple-well option available in a deep-submicron CMOS process, we developed monolithic active pixel sensors (MAPS) with the unique features of full analog signal processing and digital functionality implemented at the pixel level. After briefly reviewing the results achieved with the first prototype chip, we report on the extensive measurements on the second prototype, containing both single-channel sensors, with an improved noise figure, and an 8 × 8 pixel array. For the pixel having a collecting electrode area of 900 μ m 2 we measured an equivalent noise charge of about 40 electrons. Using the Fe 55 5.9 keV line, we obtained a Signal-to-noise (S/N) ratio of about 30. The pixel matrix ( 50 × 50 μ m 2 ) has been successfully readout up to 30 MHz. Through noise scans, an expected significant threshold dispersion has been measured. The measurements presented in this paper confirm the capability of our MAPS, based on the deep n-well concept, to be operated as ionizing radiation detectors and suggest a series of improvements we are already implementing in the design of the next prototype chip.

A front-end channel prototype for pixel detectors has been designed for the upgrades of the HL-LHC experiments. The circuit is based on a Krummenacher feedback network to continuously reset the charge sensitive amplifier and on a fast threshold discriminator to implement a time-over-threshold (ToT) method and perform amplitude measurement. The circuit was developed in a 65 nm CMOS technology and takes an overall area not exceeding 25 μm×50 μm. The power dissipation per channel, not including dynamic consumption, is around 5 μW. This paper is in particular concerned with the characterization of the charge sensitive amplifier, whose gain and recovery time can be adjusted to comply with changes in the experiment parameters. A very small gain dispersion was detected in the set of characterized samples. An equivalent noise charge of 120 electrons was found for a detector emulating capacitance of 100 fF. The response of the amplifier is compatible with the speed requirements for the foreseen application.

The PixFEL project aims to develop an advanced X-ray camera for imaging suited for the demanding requirements of next generation free electron laser (FEL) facilities. New technologies can be deployed to boost the performance of imaging detectors as well as future pixel devices for tracking. In the first phase of the PixFEL project, approved by the INFN, the focus will be on the development of the microelectronic building blocks, carried out with a 65 nm CMOS technology, implementing a low noise analog front-end channel with high dynamic range and compression features, a low power ADC and high density memory. At the same time PixFEL will investigate and implement some of the enabling technologies to assembly a seamless large area X-ray camera composed by a matrix of multilayer four-side buttable tiles. A pixel matrix with active edge will be developed to minimize the dead area of the sensor layer. Vertical interconnection of two CMOS tiers will be explored to build a four-side buttable readout chip with small pixel pitch and all the on-board required functionalities. The ambitious target requirements of the new pixel device are: single photon resolution, 1 to 104 photons @ 1 keV to 10 keV input dynamic range, 10-bit analog to digital conversion up to 5 MHz, 1 kevent in-pixel memory and 100 μm pixel pitch. The long term goal of PixFEL will be the development of a versatile X-ray camera to be operated either in burst mode (European XFEL), or in continuous mode to cope with the high frame rates foreseen for the upgrade phase of the LCLS-II at SLAC.

Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed, based on standard supply voltage and on auxiliary, reduced supply. Circuit performance, in terms of power consumption and speed, is evaluated for each of the proposed solutions and compared with that relevant to standard CMOS drivers.

This work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2 V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65 nm CMOS technology. Together with a conventional structure which exploits bipolar devices, a smaller solution based on pn diodes and a version with MOS transistors biased in weak inversion region are included. This paper intends to describe and compare the features of the different circuits designed.

The PixFEL project is conceived as the first stage of a long term research program aiming at the development of advanced X-ray imaging instrumentation for applications at the free electron laser (FEL) facilities. The project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging by exploring cutting-edge solutions for sensor development, for integration processes and for readout channel architectures. The main focus is on the development of the fundamental microelectronic building blocks for detector readout and on the technologies for the assembly of a multilayer module with minimum dead area. This work serves the purpose of introducing the main features of the project, together with the simulation results leading to the first prototyping run.

We report on the design and TCAD simulations of planar p-on-n sensors with active edge aimed at a four-side buttable X-ray detector module for future FEL applications. Edge terminations with different number of guard rings were designed to find the best trade-off between breakdown voltage and border gap size. The methodology of the sensor design, the optimization of the most relevant parameters to maximize the breakdown voltage and the final layout are described.

Under a Creative Commons license., The Tracker Group of the CMS Collaboration.-- et al., The response of n+p silicon strip sensors to electrons from a 90Sr source was measured using a multi-channel read-out system with 25 ns sampling time. The measurements were performed over a period of several weeks, during which the operating conditions were varied. The sensors were fabricated by Hamamatsu Photonics on 200 μm thick float-zone and magnetic-Czochralski silicon. Their pitch was 80 μm, and both p-stop and p-spray isolation of the n+ strips were studied. The electrons from the 90Sr source were collimated to a spot with a full-width-at-half-maximum of 2 mm at the sensor surface, and the dose rate in the SiO2 at the maximum was about 50 Gy(SiO2)/d. After only a few hours of making measurements, significant changes in charge collection and charge sharing were observed. Annealing studies, with temperatures up to 80 °C and annealing times of 18 h showed that the changes can only be partially annealed. The observations can be qualitatively explained by the increase of the positive oxide-charge density due to the ionization of the SiO2 by the radiation from the β source. TCAD simulations of the electric field in the sensor for different oxide-charge densities and different boundary conditions at the sensor surface support this explanation. The relevance of the measurements for the design of n+p strip sensors is discussed., The research leading to these results has received funding from the European Commission under the FP7 Research Infrastructures project AIDA, grant agreement no. 262025. We are also grateful to the HGF Alliance Physics at the Terascale, which has partially funded the setup used for the measurements, and to the BMBF, the Ministry of Research and Education of the German Federal Republic, for funding the Ph.D. position of J. Erfle within the Forschungsschwerpunkt FSP-102, Elementarteilchenphysik mit dem CMS-Experiment., Open Access funded by CERN.

We present a new approach to the design of monolithic active pixel sensors (MAPS) in CMOS technology. By exploiting the triple well option, available in modern deep-submicron processes, it was possible to implement at the pixel level a full analog signal processor and to increase the area of the sensing electrode. These two new features aim to address some limiting aspects of conventional MAPS, such as the read-out speed and the charge collection efficiency. We report on the characterization of the first prototype chip, in particular the calibration with soft X-rays and the response to β -rays, demonstrating the capability of the sensor in detecting ionizing radiation.

The goal of this work is to provide an extensive analysis of the noise performances which can be attained by detector front-end integrated circuits in the 0.13 μm CMOS node. To estimate the noise limits of a front-end system in this CMOS generation, the paper presents the results of measurements carried out on NMOS and PMOS devices fabricated in a commercial process. Parameters extracted from experimental data are used to define design criteria for noise optimization in the perspective of future experimental environments (SLHC, ILC, Super B-Factory).

This work studies the feasibility of a new implementation of CMOS monolithic active pixel sensors (MAPS) for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is readout by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, available as a shielding frame for n-channel devices in deep submicron, triple well CMOS technologies. Based on the above concept, a chip, which includes several test structures differing in the sensitive element area, has been fabricated in a 0.13 μ m CMOS process. In this paper, the criteria underlying the design of the pixel level analog processor will be presented, together with some preliminary experimental results demonstrating the feasibility of the proposed approach.

We designed and fabricated a novel monolithic active pixel sensor (MAPS), in STMicrolectronics 0.13 µ m CMOS technology, exploiting the triple well option to implement, at the pixel level, a more complex signal processor and to increase the size of the charge collecting electrode with respect to previously developed CMOS MAPS. This was possible using the deep n-well, available in triple well technology, as a sensing electrode and placing, in the same physical area, part of the readout electronics. The signal processing chain, implemented in the elementary cell, includes a low noise charge preamplifier, a shaper, a discriminator and a latch. The first prototype chips have been successfully tested with very encouraging results. In this work we present the performance of the front-end electronics and the response of the sensor to ionizing radiation.

Six layers of microstrip detectors are foreseen in the present baseline design of the SuperB Silicon Vertex Tracker. Different strip pitches and lengths will be used in the various SVT layers; however, the capability of standing a high background rate and of operating with high hit detection efficiency will be a common feature of the innermost layers. These requirements set the need for a readout chip with analog channels with a short signal shaping time (25–200 ns in layers 0–3) to achieve an adequate time stamp resolution and a small pulse overlap. These channels are also required to provide a 4-bit hit amplitude resolution for dE / dx measurements. A new chip is being designed in a 130 nm CMOS process to comply with these specifications. This paper discusses the solutions that are adopted in this chip for the various blocks of the analog channels, and will present the simulation results for the current design along with the expected performance in terms of parameters such as signal-to-noise ratio, dynamic range, linearity, power dissipation.

The results discussed in this paper are relevant to junction field effect transistors (JFETs) and JFET-based charge sensitive amplifiers fabricated in a detector compatible process. Such structures were irradiated with 27 MeV protons to evaluate the suitability of the technology for space applications and high-energy physics experiments from the standpoint of radiation tolerance. The process investigated in this work, originally designed for the fabrication of silicon detectors to be operated in a fully depleted condition, has been tuned to embed N-channel JFETs, NMOS devices and bipolar transistors in the same high resistivity substrate. The most significant electrical parameters have been monitored after exposing the test structures to different proton fluences in order to characterize their total dose and bulk damage response. Comparison with the results from previous irradiations with /spl gamma/-rays might be helpful in shedding light on the fundamental mechanisms underlying radiation damage in JFET silicon devices.

The LHC beam luminosity monitor is based on the following principle. The neutrals that originate in LHC at every PP interaction develop showers of minimum ionizing particles in the absorbers placed in front of the separation dipoles. The shower energy, measured by suitable detectors in the absorbers is proportional to the number of neutral particles and, therefore, to the luminosity. The principle lends itself to a luminosity measurement on a bunch-by-bunch basis. However, to make such a measurement feasible, the system must comply with extremely stringent requirements. Its speed of operation must match the 40 MHz bunch repetition rate of LHC. Besides, the detector must stand extremely high radiation doses. This paper discusses the solutions adopted to comply with these requirements.

This work is concerned with the effects of /spl gamma/-rays on the static, signal and noise characteristics of JFET-based circuits belonging to a fabrication technology made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy. Such a process has been tuned with the aim of monolithically integrating the readout electronics on the same highly resistive substrate as multielectrode silicon detectors. The radiation tolerance of some test structures, including single devices and charge sensitive amplifiers, was studied in view of low-noise applications in industrial and medical imaging, X- and /spl gamma/-ray astronomy and high energy physics experiments. This paper intends to fill the gap in the study of gamma radiation effects on JFET devices and circuits belonging to detector-compatible technologies.

During the past 15 years, the CMOS technologies have provided the most widely followed approach to signal processing with microstrip detectors. In more recent times, CMOS front-end systems have been developed to acquire and process signals from pixel detectors. During the past few years, the favor toward CMOS processes in their applications in the broad area of detector signal processing has been enhanced by the technological advancement known as device scaling and by two aspects connected to it. One is the shrinking in channel length L into the deep submicron region. The second one is the related reduction in the gate-oxide thickness t ox to a few nm. The reduction in t ox has, as a consequence of primary importance, a decreased 1/ f -noise contribution to the equivalent noise charge (ENC). The thinner gate-oxide and the shrinking in gate length, in some regions of operations, concur to increase the transconductance of the device, which results in a smaller ENC contribution from channel thermal noise. The goal of the present paper is to address the question of whether or not the most advanced CMOS processes may meet the requirements set by high resolution, high dynamic range applications like the energy-dispersive photon analysis with solid-state detectors of comparatively large capacitance.

This paper presents the experimental results relevant to JFET charge preamplifiers fabricated in a detector-compatible technology. This fabrication process, developed at the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy, is being tuned with the aim of integrating a multichannel mixed analog-digital circuit together with semiconductor detectors in a high-resistivity substrate. Possible applications are in the field of medical and industrial imaging, in space and high energy physics experiments. An all-NJFET charge sensitive amplifier, which can use either a resistive or a nonresistive reset in the feedback network, has been tested. The two configurations have been studied, paying particular attention to noise performances, in view of the design of the complete readout channel.

A novel segmented multigap pressurized gas ionization chamber is being developed for optimization of the luminosity of the Large Hadron Collider (LHC). The ionization chambers are to be installed in the front quadrupole and 0/spl deg/ neutral particle absorbers in the high luminosity interaction regions (IRs) and sample the energy deposited near the maxima of the hadronic/electromagnetic showers in these absorbers. The ionization chambers are instrumented with low noise, fast pulse-shaping electronics to be capable of resolving individual bunch crossings at 40 MHz. In this paper, we report the initial results of our second test of this instrumentation in a super proton synchrotron (SPS) external proton beam. Single 300 GeV protons are used to simulate the hadronic/electromagnetic showers produced by the forward collision products from the interaction regions of the LHC. The capability of instrumentation to measure the luminosity of individual bunches in a 40 MHz bunch train is demonstrated.

This paper presents a study of the noise behavior of deep submicron CMOS transistors, in view of applications to analog front-end systems for high granularity detectors. The white component of the noise voltage spectrum, which is most important for fast signal processing, and the 1/ f noise contribution are investigated to find low-noise design criteria concerning the choice of the polarity and of the channel length of the preamplifier input device in low-power operating conditions. This analysis is supported by experimental data from noise measurements on CMOS devices belonging to a 0.35 μm process.

We describe our experience on design and fabrication, on high-resistivity silicon substrates, of microstrip detectors and integrated electronics, devoted to high-energy physics experiments and medical/industrial imaging applications. We report on the full program of our collaboration, with particular regards to the tuning of a new fabrication process, allowing for the production of good quality transistors, while keeping under control the basic detector parameters, such as leakage current. Experimental results on JFET and bipolar transistors are presented, and a microstrip detector with an integrated JFET in source–follower configuration is introduced.

The PixFEL project is conceived as the first stage of a long term research program aiming at the development of advanced instrumentation for coherent X-ray diffractive imaging applications at the next generation free electron laser (FEL) facilities. The project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging through the adoption of cutting-edge microelectronic technologies and innovative design and architectural solutions. For this purpose, the collaboration is developing the fundamental microelectronic building blocks (low noise analog front-end with dynamic compression feature, high resolution, low power ADC, high density memories) and investigating and implementing the enabling technologies (active edge pixel sensors, high density and low density through silicon vias) for the assembly of a multilayer four side buttable tile. The building block design is being carried out in a 65 nm CMOS technology. The ambitious goal of the research program is the fabrication of an X-ray camera with single photon resolution, 1 to 104 photons @ 1 keV to 10 keV input dynamic range, 1 kevent in-pixel memory, 100 µm pixel pitch, and the capability to be operated at the fast (1 MHz or larger) rates foreseen for the future X-ray FEL machines.

This work presents the design of a read-out channel suitable for application to silicon pixel detectors for the next generation Free Electron Laser (FEL) experiments. The readout architecture, which has been carried out in a 65 nm CMOS technology, consists of a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaping stage and a low-power analog-to-digital converter (ADC), hosted in a 100 µm-pitch pixel. The blocks will be operated in such a way to cope with the high frame rates (exceeding 1 MHz) foreseen for future X-ray FEL machines. The paper describes in detail the architecture and the performance of the CSA and provides an overview about the analog readout channel.

We report on the design and TCAD simulations of planar active-edge pixel sensors within the INFN PixFEL project. These devices are intended as one of the building blocks for the assembly of a multilayer, four-side buttable tile for X-ray imaging applications in future Free Electron Laser facilities. The requirements in terms of very wide dynamic range and tolerance to extremely high ionizing radiation doses call for high operation voltages. A comprehensive TCAD simulation study is presented, aimed at the best trade-offs between the minimization of the edge region size and the sensor breakdown voltage.

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

This work presents the characterization of deep n-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm homogeneous, vertically integrated technology. An evaluation of the 3D MAPS device performance, designed for application of the experiments at the future high luminosity colliders, is provided through the characterization of the prototypes, including tests with infrared (IR) laser, 55Fe and 90Sr sources. The radiation hardness study of the technology will also be presented together with its impact on 3D DNW MAPS performance.

This paper describes a quantitative method for the selection of P- and N-channel junction field-effect transistors as input elements in low-noise charge-sensitive preamplifiers for applications requiring high radiation tolerance. The method is based upon a thorough analysis of ionizing radiation effects on the noise spectral density of such devices. It can be used to predict whether a P- or an N-type transistor is preferable as the front-end element of a preamplifier once the radiation doses and the electronic system readout times are known. Such criteria can he useful in the design of low-noise radiation-resistant electronics suitable for applications where high levels of total radiation dose are expected during the circuit lifetime.

This paper discusses the criteria that underlie the design of front-end systems for pixel sensors of different types in a highly diversified fields of application. In the pixel front-end systems, low level analog signals coexist with digital activities and the design must comply with severe limitations in the area and in the power allotted to the single pixel cell. Noise and radiation hardness issues are of utmost importance in several applications. Some ways to arrive at a design which suits specific application requirements are discussed and the impact of the most advanced monolithic processes is evaluated.

A fluorescence detector, consisting in a PhotoMultiplier Tube (PMT) pixel camera, will be used in the AUGER experiment to study cosmic-ray sources with energies exceeding 10 18 eV. The front-end electronics transmits the PMT signals to the ADCs, retaining the timing and amplitude information carried by signals which span a wide (15–16 bits) dynamic range. The analog processing channel consists of a low-noise linear section, including an antialiasing filter, followed by a circuit of original conception, performing a high-accuracy bilinear compression of the signal dynamic range. This allows operation with a 12-bit ADC. Quantization errors can be minimized by correctly choosing the compression parameters. The paper presents the concepts the compressor is based upon, and the experimental behavior of a prototype version.

This work presents the features of a new kind of deep n-well monolithic active pixel sensor (DNW-MAPS), called SDR1 (Sparsified Data Readout), which exploits the capabilities of vertical integration (3D) processing in view of the design of a high granularity detector for vertexing applications at the International Linear Collider (ILC). SDR1 inherits and extends the functional capabilities of DNW-MAPS fabricated in planar (2D) CMOS technology and is expected to show better collection efficiency with respect to 2D versions. The aim of the paper is to outline the features of analog and digital architecture of the SDR1 chip, together with circuit simulations data. Also some device simulation results concerning detection efficiency will be discussed.

In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source ( 55 Fe ) tests, will be presented.