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A fourth-order continuous-time RF bandpass \Delta\Sigma ADC has been fabricated in 40 nm CMOS for f_s/4 operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the fractional-N PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers of the ADC are six times interleaved enabling a polyphase structure for the DFD and relaxing clock frequency requirements. This quantization scheme realizes a sampling rate of 8.88 GS/s which is the highest sampling speed for RF bandpass \Delta\Sigma ADCs reported in standard CMOS to date enabling high oversampling ratios for RF digitization without compromising power-efficient implementation of the DFD. Measurements show that the ADC achieves a dynamic range of 48 dB in a band of 80 MHz with an IIP3 of 1 dBm. [ABSTRACT FROM PUBLISHER]

In a generic behavioral model of an analog or mixed-signal electronic system, the internal and external signals and their interactions are formulated by more general descriptions than in commonly used behavioral models. This allows a more flexible design methodology. Whereas a behavioral model models an architecture of a system at a specific abstraction level, a generic behavioral model is built up out of generic functions that by specialization of these functions allows the modeling of a wide range of system architectures with different degrees of modeling accuracy. This enhanced abstraction level makes the approach suited for systematic analysis through refinement and architectural exploration of analog and mixed-signal building blocks and systems using computer- aided-design tools. As an application of this methodology, a generic behavioral model has been developed for continuous-time (CT) ΔΣ analog-to-digital converters (ADCs) together with the specialization functions to take into account all major nonidealities at different levels of detail, including effects like jitter, saturation, and weakly nonlinear distortion. The results of experiments of a SystemC implementation of the model are presented. Compared to other models for analysis, the proposed method enables high accuracy even at low abstraction levels, whereas the event-driven character of the model results in short simulation times compared to time-marching simulations of behavioral models, written for example in very-high-speed-integrated- circuit (VHSIC) Hardware Description Language Analog and Mixed Signal (VHDL-AMS) or Matlab/Simulink. The flexibility of the model is demonstrated. [ABSTRACT FROM AUTHOR]

Circuit-level simulation of ΔΣ modulators is a time- consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the stimulations for discrete-time ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in today's low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time ΔΣ topologies. In this paper, we present a method for the high-level simulation of continuous-time ΔΣ modulators as needed In top-down design and high-level modulator optimization. The method is based on analytics) integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented In a user-friendly tool. Nonidealities such as finite gain, finite GPW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level. [ABSTRACT FROM AUTHOR]