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This paper reports the hot carrier reliability of n-MISFET with HfSiON gate dielectrics and n/sup +/ polysilicon gate electrode. It is found that generation of electron traps is the main cause of device degradation. The worst hot carrier stress condition is found to be V/sub d/=V/sub g/ condition rather than the well-known condition of V/sub g/ giving maximum substrate current (I/sub sub//sup max/), which is the worst condition for n-MOSFET with conventional SiO/sub 2/. It is revealed that this difference originates from the difference in degradation mechanism.

Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVD Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm/sup 2//Vs@0.8 MV/cm (85% of SiO/sub 2/) and hole mobility of 73 cm/sup 2//Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.

Characteristics of sub-100 nm CMOSFETs with HfSiON gate dielectrics with various Hf concentrations (/spl Cscr/;/sub Hf/) have been investigated, and the design guideline to obtain the superior device performance is presented for the first time. It is found that MOSFETs with lower /spl Cscr/;/sub Hf/ results in higher drive current due to lower parasitic resistance (R/sub para/) for the same effective oxide thickness (EOT). Therefore, /spl Cscr/;/sub Hf/ should be kept low in so far as it meets the /spl Iscr/;/sub g/ target in order to obtain good MOSFET performance. It is demonstrated that 50 nm gate CMOSFETs with optimized HfSiON show high drive current of 650 /spl mu/A//spl mu/m and 250 /spl mu/A//spl mu/m for n-and p-MOSFET, respectively, with low gate leakage current (/spl Iscr/;/sub g/) of 0.3 A/cm/sup 2/ while maintaining the thermal stability up to 1050/spl deg/C. This performance exceeds reported value of sub-100 nm CMOSFET with high-k materials.

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.

This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um/sup 2/ trench capacitor DRAM and 0.247um/sup 2/ 6Tr.SRAM embedded memories.

We achieved 0.73 nm EOT, 88 A/cm/sup 2/ J/sub g/, and 92% G/sub m/ of that for SiO/sub 2/ by just oxidation of SiN films. In addition, we achieved further improvement of EOT-J/sub g/ characteristics by re-nitridation process with minimum degradation of G/sub m/. EOT of 0.70 nm and J/sub g/ as 95 A/cm/sup 2/ is realized with superior suppression of boron penetration (/spl Delta/V/sub th/=0.04 V).

Dielectric breakdown mechanisms in HfSiON were thoroughly investigated by utilizing the substrate hot carrier injection. It was found that the total hole fluence (Q/sub p/) dose not dominate the breakdown in HfSiON. Furthermore, it was experimentally clarified that the injected electrons into HfSiON have the significant role for the breakdown, irrespective of their potential energy. This result strongly suggests that the roles of injected cold electrons in HfSiON are remarkably different from those in SiO/sub 2/ and SiON.

This paper describes how thin film capacitance measurements below 2 nm are affected by an anomalous "negative capacitance effect" induced by parasitic components that originate from the wafer chuck. This inductive effect is observed even though appropriate calibration is executed at the tips of the probe needle to remove the residual inductance from the measurement system. We explain the mechanism of the "negative capacitance effect" theoretically and demonstrate it experimentally. We also propose a new methodology for on-wafer C-V measurements that can reduce this inductive effect that originates from system parasitics while at the same time expanding the practical frequency range of measurement to 100 MHz.

High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.

In this paper, the physical and electrical characteristics of ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impact of plasma nitridation conditions on DC characteristics was investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. NBTI has been also investigated and the lifetime at 105/spl deg/C and 0.85 V operation is estimated to be about 10 years. The final current drives of 690 /spl mu/A//spl mu/m for nFET and 301 /spl mu/A//spl mu/m for pFET at Vdd = 0.85 V (Ioff = 100 nA//spl mu/m) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT

The effects of the nitrogen in the HfSiON gate dielectric on the electrical and thermal properties of the dielectric were investigated. It is clearly demonstrated that nitrogen enhances the dielectric constant of silicates. High dielectric constants of the HfSiON are maintained and boron penetration is substantially suppressed in the HfSiON during high temperature annealing. These properties are ascribed to the homogeneity of the bond structure in the film containing nitrogen through high temperature annealing.

In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.

Physical mechanism of direct tunneling in unstressed and stressed gate oxides thinner than 5 nm is experimentally investigated. It is revealed that the direct tunneling current in an unstressed MOS (n/sup +/-poly Si/SiO/sub 2//Si substrates) structure has a strong bias polarity dependence, which is determined through the competing effects of tunneling probability and the number of tunneling carriers. It is also found that a leakage path allowing the flow of holes dominates SILC and leakage current after soft breakdown in stressed oxides less than 5 nm. This leakage path has the asymmetric carrier conduction property that current from the Si substrate is much larger than that from the n/sup +/-poly gate.

The authors propose a novel model for band-to-band tunneling caused by a nonuniform electric field, which is expressed in terms of the local field and its spatial variation rate and gives tunneling probabilities in magnitude and electric field dependence that are different from those given by conventional models. The proposed model can be incorporated into device simulators, and the results show the reasonable coincidence with experimental findings without any fitting parameter. >

Systematic experiments are carried out in this paper for quantitative understanding of gate voltage scaling for TDDB under the direct tunneling regime. It is found that the slope of ln T/sub BD/ has a nonlinear relationship to V/sub ox/. A simple model to explain the experimental voltage acceleration factor is proposed based on the anode hole injection (AHI) concept. It is shown, according to model prediction, that the 1.8 nm gate oxide is still reliable under real operational voltage conditions.

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.

Recently, heavily nitrided NO oxynitride has been proposed as an alternative to pure oxide in order to realize high drivability and suppress a large gate leakage current (Fujiwara et al, Digest of IEDM 2000, pp. 227-30, 2000). However, in general, oxynitride has higher interface state density than that of pure oxide, and brings low frequency noise (or 1/f noise) degradation (Kimijima et al., 1999). Thus, analog characteristics under such aggressive doping conditions should be observed carefully for realization of high performance mixed analog and digital LSIs. In this paper, we report analysis of the 1/f noise degradation due to heavily nitrided NO oxynitrides and predict the interface state density value to satisfy 1999 ITRS Roadmap requirements. Additionally, a buried channel type MOSFET is proposed for suppression of the 1/f noise and f/sub T/ degradation.

Systematic experiments of time-to-breakdown (T/sub BD/) of thin gate oxides are carried out in this paper for quantitative understanding of gate voltage scaling for TDDB under the direct tunneling regime. It is found that the slope of ln T/sub BD/ has a nonlinear relationship to gate oxide voltage, V/sub ox/, and thus, the conventional constant voltage acceleration model is not applicable for lifetime prediction. A simple model to explain the experimental voltage acceleration factor is proposed based on the anode hole injection (AHI) concept. It is shown that the significant decrease in hole generation due to lowering of the electron energy injected to the anode greatly helps the TDDB reliability.

This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced logic process is compatible with 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 /spl mu/m/sup 2/ 6 transistor SRAM. Two kinds of high V/sub dd/ devices can be prepared by the triple gate oxide process. Moreover, for mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors are introduced into Cu and low-k interconnects.

A new model of the roughness correlation function S(r) has been proposed in order to explain the different behavior of high field mobility limited by surface roughness scattering, µSR, between electrons and holes in metal oxide semiconductor field effect transistors (MOSFETs) with oxynitrides. It has been shown, for the first time, that the change in electron and hole µSR associated with NO oxynitridation can be reasonably well explained by the appropriate choice of the form of S(r).

This document will communicate that the Au/TiOx photocatalyst shows a high activity with tremendous efficiency for the degradation of volatile organic compounds, such as formaldehyde, acetaldehyde,...

We have reported that TiO 2 particles prepared in reverse micelles showed high photocatalytic activity in an amorphous rather than anatase state and that the amorphous state changes easily into the anatase state just by irradiating visible light. So we prepared Au/TiO 2 complex particles which included Au colloids in TiO 2 by the reverse micelle method. We found that Au colloids exhibited the sustaining effect of amorphous TiO 2 particles. Moreover, Au/TiO 2 complex particles showed higher photocatalytic activity than single TiO 2 particles and also could be used repeatedly.

Amorphous TiO2 particles were prepared by the various reverse systems such as reverse micelle, reverse microemulsion, reverse emulsion, and by the sol–gel method, and investigated on their photocat...

The roles of electrons and holes in the dielectric breakdown of HfSiON have been investigated by controlling the numbers of injected hot electrons and hot holes separately by the substrate hot-carrier injection technique. It has been clarified that carrier flux has the strongest effect on the dielectric breakdown of HfSiON rather than carrier energy and the electric field across dielectrics. The amount of electron flux leading to the dielectric breakdown of HfSiON is about twice as large as that of hole flux.

We have investigated the electron mobility limited by the remote charge scattering, µRCS, in the thin silicon body (≤8 nm) double-gated metal–oxide–semiconductor field-effect transistors (MOSFETs), focusing on its dependency on the body thickness and the silicon surface orientation. In order to predict the µRCS in such an unprecedented MOSFET system, the adequacy of physical models used in the computation was verified by comparing the computational results with the experimentally determined µRCS from the actual bulk MOSFETs with high-k dielectric fabricated on the (100) and (110) silicon substrates. It has been discovered for the first time that the µRCS is dropped to less than half of the bulk device's µRCS when the body thickness is 5 nm and that the µRCS lowering derived from the body thickness reduction is more serious in the (110)-oriented surface than in the (100)-oriented surface. These mobility trends have been quantitatively explained by the effective mass difference between the two surfaces as well as by the carrier confinement in the metallurgically defined narrow silicon body. These observations indicate the great importance of the systematic reduction of charged traps in high-k gate dielectrics in the advanced devices.

We extensively investigated the physical origin of the threshold voltage V TH modulation by the Ge channel ion implantation (I/I) in HfO2/TiN/polycrystalline Si gate stack systems. The possible V TH modulation factors were carefully distinguished from each other by changing the channel dopant concentration and the thickness of the gate dielectric films. It was found that the changes in energy-band offset and dopant concentration in the channel region are minor factors of the V TH modulation. However, it was also found that ΔV TH is sensitive to the oxidation condition of the interfacial oxide layer; a longer oxidation induces a larger ΔV TH. From the X-ray spectroscopy, we found that a Ge pile-up at the interfacial layer/channel interface occurs, and that the V TH modulation range correlates well with the amount of piled-up Ge.

A detailed comparison of high-k/metal gate stacks fabricated on the (100)- and (110)-oriented substrates has been made. We have verified that there is no structural difference between the gate stacks on the two substrates. The orientation independence of our gate stacks with the high-quality high-k/silicon interface for both substrates reveals the intrinsic effects of the crystal orientation on the high-k/metal gate devices. This is the first direct evidence that the inversion carrier quantization dependency on the crystal orientations dominates the total gate capacitance in the high-k/metal gate system. The analysis of the electron and hole mobilities highlights the fact that the scattering mechanisms inherent in the high-k/meta gate stacks limit the mobility enhancement and reduction driven by the effective mass change. No significant difference in the threshold voltage instability under the positive or negative gate bias stress is observed for the two substrates. Therefore, the optimized high-k/metal gate stacks enable us to gain certain benefits from the limited modulation of the mobility without sacrificing the stability of the threshold voltage.

The influence of the crystal orientation difference between (100) and (110) silicon substrates on characteristics of La2O3- and Al2O3-capped HfO2 dielectric metal–oxide–semiconductor field-effect transistors has been investigated. We observed that the equivalent oxide thickness of the capped devices varies according to the crystal orientation, indicating that the two substrates are not equal in the gate stack scalability within a sub-nanometer regime. We found that the mobility dependency on the crystal orientation is reduced by additional scattering associated with the capping films, suggesting the difficulty to derive maximum benefit from an inherent difference in the mobility depending on the crystal orientation.

The spatial resolution of scanning spreading resistance microscopy has been limited by using conventional probes when measuring in air. Sufficient electric contact of a probe-sample has been difficult to obtain in air due to the existence of moisture/contamination. Two-dimensional carrier profiling of nanoscale silicon devices is performed in a vacuum with conventional probes, and a high spatial resolution is obtained. Ultrashallow junctions down to 10nm are measured accurately with high reproducibility. Experimental results show that a good electric contact between probe and sample is important for obtaining high spatial resolution.

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A MOSFET dimension is continuously scaled down to improve its performance. Gate insulator thickness reaches, however, almost its physical limitation in the case of SiON film. Recently, fabrication process of SiON film for less than 1nm EOT was presented. This technology can extend applicability of SiON film beyond 65 nm node. High-k film is a promising candidate to replace SiON film with lower leakage current. HfSiON is one of the candidates for high-k materials. Despite the intensive studies by many researchers, pMOS Vth shift caused by Fermi-level pinning is still the biggest problem when combined with poly-Si gate electrode. This paper addresses issues for scaled CMOS with SiON and high- k. Process optimization method with device characteristics is demonstrated for 45 nm node and beyond.

65 nm gate length HfSiON-CMOSFET was fabricated with various Hf concentrations and gate spacers in view of device performance and reliability. The negative charges are generated in HfSiON/Si-substrate interface at the gate edge region for HfSiON with high Hf concentration. SiN offset spacer suppresses the charge generation and the degradation of drive current. Even so, HfSiON with low Hf concentration is higher at performance and reliability than that with high one. Moreover, the optimized HfSiON shows scalability of up to hp45 nm low standby power (LSTP).

Impact of implementation of HfSiON as a gate dielectric on sub-100 nm generation CMOSFET is reviewed. It is revealed that most parameters are affected when HfSiON with high Hf concentration is used, and thus, careful re-engineering is indispensable. We demonstrate HfSiON-CMOSFET for hp 65 nm LSTP application which meets the specification of ITRS roadmap by an adequate re-engineering

In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 /spl mu/m/sup 2/. Embedded DRAM cell size is 0.11 /spl mu/m/sup 2/. MOSFET's in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current. Furthermore poly-SiGe gate electrode and Ni Salicide were adopted to control high gate electrode activation and USJ (ultra shallow junctions) under low thermal budget. Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with non-slimming trim mask process were employed to achieve a small SRAM cell. Cu interconnects; using low-k dielectrics has an 180 nm pitch.