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Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit’s performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and $2.5\times $ reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.

High and unevenly spread 3D chip temperatures can be reduced when appropriate thermal-aware design is incorporated in early floorplanning. We developed a fast approach to evaluate thermal goodness of 3D floorplans. The proposed algorithm uses a power-based measure calculated using the impact of the heat from adjacent intra- and inter-layer modules. This approach significantly reduces runtime compared to temperature distribution simulation when thermal optimization is included in non-deterministic 3D-floorplanners. Usually, the goal is to minimize peak temperature and generate thermally-optimized 3D floorplans. Our results show that thermal quality factors generated by our model closely agree with factors generated by more accurate simulation-based thermal models, like HotSpot [1]. We achieve a correlation coefficient of 0.96 with HotSpot results and an average speed up of 29X on evaluation grid size of 64x64x4 for GSRC benchmarks. The sensitivity of the proposed algorithm to temperature difference between the 3D floorplans being compared and the success rate is also analyzed.

Correlation of carbon nanotube FETs (CNFETs) due to aligned CNT growth was shown to improve functional yield of CNFET-based circuits under diameter and the number of CNTs variations. Circuits with correlated CNFETs were investigated based on the assumption that all transistors in correlated sets were identical, due to sharing the same sets of tubes. Therefore, all transistors in the correlated sets have the same failure probability and the same drive current. Though CNTs reach long lengths, not all grow to be equally long. CNTs grown on the substrate will reach various lengths due to early catalyst precipitation and varying CNT diameter. Thus, assuming 100% correlation in correlated-CNFETs is too optimistic. In this work we analyze the impact of variation in CNT length on functional yield and performance of CNFETs. Our results show that variation in tube length can increase failure probability of rows of correlated transistors by 85%. and increase variation in total delay by 1.51X when compared to correlated CNFETs without variation in CNT length. The impact of CNT length variation on gate delay with and without tube diameter and tube count variations is analyzed.

Due to limited controllability over the tube growth process, Carbon Nanotube Field-Effect Transistors (CNFET) show large variations in their behavior. These variations are primarily caused by variation in CNT diameter and the presence of metallic tubes (m-CNT) in, what it should be, purely semi-conducting (s-CNT) arrays. For proper operation of a CNFET metallic tubes have to be removed, unintentionally reducing transistor strength. This work proposes to use a calculated minimum CNT redundancy at the transistor level to improve functional yield for a given failure rate. We focus our evaluation on a critical path that in reality, due to metallic tube presence, could be a different path in each circuit. We limit the redundancy to a minimum required, to avoid unnecessary increase in the channel area. The calculated minimum number of redundant CNTs are added to each CNFET to achieve only slightly increased statistical critical path delay after m-CNT removal, compared to the ideal critical path delay. We use a statistical approach to improve prediction accuracy for both critical path delay and functional yield. With proposed minimum redundancy we are able to reduce the allowed delay degradation (tolerance) by 15-25% and still have a good functional yield. Results show a reduction of 7-10% in critical path delay variation of ISCAS’85 logic benchmark circuits with >99% functional yield (Yf).

We propose a novel floorplanning algorithm for 3D ICs with through-silicon vias (TSVs) that directly optimizes delay due to wires and TSVs. We include the non-negligible impact of area occupied by TSVs, perform nets-to-TSVs assignment, and use physical dimensions of TSVs and wires for delay calculations. Our floorplanning is based on co-placement of TSV islands with circuit blocks and is performed under fixed-outline constraints. The total delay is a direct optimization goal in the presented delay-aware 3D floorplanning and accounts for the RC delay impact of TSVs on the delay of each individual net during the nets-to-TSVs assignment. Therefore, compared to traditional wirelength-aware floorplanning, which separately minimize wirelength and the number of TSVs, the proposed approach results in more effective delay minimization. Our experimental results show improved solution quality with up to 9 % shorter wirelength and an average 40 % reduction in the number of TSVs as compared to most recent publications. Total delay reduces between 10 and 12 % when the delay, instead of wirelength and the number of TSVs separately, is minimized.

We analyze the impact of through-silicon vias (TSVs) downsizing and future CMOS nanotechnology scaling on interconnect delay and power in 3-dimensional integrated circuits (3DICs). We study three different TSV sizes of $3\mu, 1.5\mu$ and $0.5\mu$ at three diverse technology nodes of 45nm, 32nm and $22\text{nm}$ . These technology variations are considered to investigate the impact on interconnect performance and power in 3D ICs. Our discussion also includes the impact of TSV cluster size variation on TSV capacitance which is important for early performance optimization in any given technology. A delay-aware 3D floorplanning tool with dynamic TSV clustering is used to simultaneously optimize TSV footprint and TSV cluster distribution. Our results show with scaling from 45nm to 22 nm., delay, for all TSV sizes increases by `41 %, while power reduces by `46%.

With a high thermal conductivity of 3000–5000 W/m -K, Graphene outstands almost all materials in effective lateral heat spreading. Will introduction of 2D monolayer graphene in 3D-IC help in vertical heat conduction too? In this work, we investigate the impact of Graphene- and Graphite- -based inter-die thermal interface material (TIM) on the peak temperature of the 3D-IC. We compare configurations of additional intermediate layer (IL) of monolayer graphene, graphite and copper materials along with TIM. Simulations show a peak temperature reduction of up to 50°C in GSRC benchmarks. Role of thermal conductivity and the additional IL critical thickness in peak temperature reduction is also investigated. Our discussion encompasses the vertical thermal profile impact on TSV delay and peak temperature dependence on TIM material, thermal-conductivity and thickness. Lastly, of all configurations, we suggest to further investigate a very promising cost-effective graphite-based inter-die TIM along with graphite-based heat spreaders, to compensate the poor heat dissipation problem in 3D ICs.

CNFET is one of the most promising candidates for a building block of post silicon era integrated circuits due to its excellent electronic properties. The presence of unwanted metallic tubes is identified as a major challenge towards building robust CNT based circuits. Metallic tubes negatively impact the performance, power and yield of CNFET-based circuits. Current CNT growth techniques described in the literature show a wide range, from close to 4% to almost 40%, of metallic tubes being initially present in CNFETs. We used Monte Carlo simulation to analyze yield improvement techniques in both cases; (1) when metallic tubes are present in CNFETs, and (2) when they are removed with extra processing techniques proposed by researches. We proposed design-based promising methods for yield improvement. Suggested and analyzed yield-improvement techniques include transistor, gate and circuit level approaches.

The presence of metallic tubes and CNT diameter variation impacts delay of critical paths in CNFET circuits. Consequently, variations in critical path delays impact functional yield. We propose to predict circuit performance and yield using a statistical approach, rather than the worst-case method, to the critical path delay evaluation. We consider the CNT diameter variation and the number of tubes per transistor variation caused by the removal of unwanted metallic tubes. For the set of ISCAS'85 combinational benchmark circuits, we tested with initial presence of 10% and 20% metallic tubes, that are all being removed, we are able to show a functional yield between 92.04% and 99.95%, and between 20.95% and 94.05%, respectively. We assumed delay degradation not larger than 1.3x as compared to the initial 0% of metallic tubes. The algorithm proposed to statistically evaluate path delay in the presence of variations has a time complexity of O(V log V +VE), where E is the number of gates and V is the number of nodes in the circuit. The results show the reduction of statistically calculated critical path delay as compared to the worst-case calculations. This indicates that it would be possible to manufacture a CNFET-based circuit with acceptable delay and functional yield, even in the presence of fabrication imperfections. To predict the behavior of these circuits and to design them efficiently it is necessary to use a statistical approach to the design process.

We present a new scheme of buffer implementation in through-silicon via (TSV) based 3D circuits at early layout design stage for total delay minimization. For optimal buffer insertion at floorplanning level, it is important to incorporate more accurate and realistic estimation of interconnect delay and power. Early prediction of delay and power leads to better design decisions, overall timing closure and design convergence. The proposed buffer insertion scheme is integrated within the nets-to-TSVs assignment process, therefore considers the actual TSV position during buffer planning around TSVs. This method significantly minimizes signal degradation across TSVs while also avoiding excessive usage of buffers. We demonstrate that the choice of nominal wire length, which is a fixed interval between adjacent buffers, plays a critical role in the delay and power prediction of buffered interconnects. The nominal wirelength in our approach is represented by a multiplicity of the TSV equivalent wire length, which effectively models the TSV RC delay contribution to delay of a net. We compare the efficiency of our proposed scheme with existing buffer insertion techniques in 3D circuits. The power efficiency achieved by 3D circuit incorporating the proposed buffer insertion scheme is shown to be 38% higher than in 2D implementation of the same circuit.

The carbon nanotube field-effect transistor (CNFET) is a potential candidate to replace MOSFET due to advantages offered by CNFET such as its superior electrical, thermal, and mechanical properties. When designing circuits made of CNFETs, additional features such as the CNT number, positions and pitch in the array of tubes creating a transistor channel must be considered for performance evaluation. These features create additional challenges during simulation. In this paper, we analyze the effectiveness of CNFET Logical Effort (LE) model, to be used in place of simulation, for circuits with different topologies and CNFET technology (pitch) ranging from 2nm–30nm. We show that our delay evaluation tool using expanded LE model predicts delay for analyzed circuits with a very small average error of 2.15% as compared to SPICE simulations, and runs about 30 times faster. We have also evaluated our model in the presence of tube variations created by removal of unwanted metallic tubes. Our model closely correlated with Stanford SPICE model, developed for CNFET circuits, within 3%.

A very important challenge in designing through-silicon via (TSV)-based 3D ICs is to accurately estimate, through all stages of the physical design, the interconnect delay which is strongly dependent on the layout of 3D IC. The earlier in the design process and more accurate it can be done; the better design decisions can be made. Incorporating an optimal buffer insertion approach in the early layout design stage can significantly minimize delay and power in 3D circuits. Unlike 2D ICs, buffer insertion in 3D ICs needs careful consideration of additional design constraints in interconnects spanning multiple device layers. In this paper, we propose a novel buffer insertion scheme for delay optimization during 3D floorplanning. For individual 3D nets, the algorithm efficiently computes the desired distance between consecutive buffers (buffer insertion length), which depends on the non-negligible TSV RC delay contribution of the net. This technique of variable buffer insertion length, used during floorplanning, allows optimizing buffers for individual 3D interconnects and reduces overall buffer count by up to 25% and total power consumption by up to 12%. The proposed approach also includes a method for buffer insertion around a TSV, based on the TSV location and its RC delay. Our experiments suggest that the proposed method of buffer planning around TSVs avoids delay violation and reduces delay across TSVs up to 11%, minimizing buffer usage. The paper also analyzes the impact of key parameters such as buffer size and TSV contact resistance on the delay and power dissipation in 3D interconnects.

We present a placement-aware 3-D floorplanning algorithm that considers 3-D-placement of logic gates inside modules for wirelength minimization. It allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. A set of vertical constraints is derived on sequence pairs of different device layers that reduces the solution space, and a fast packing algorithm with vertical constraints enables quick floorplan evaluation. Experimental results on MCNC and GSRC benchmarks show that our algorithm can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3-D floorplanning algorithms, our tool reduces the system level total wirelength by 9.8%.

Carbon nanotube field-effect transistor (CNFET) is one of the most promising candidates for a building block of post silicon era integrated circuits. One of the major challenges faced by the CNFET is the presence of unwanted metallic tubes that adversely impacts the delay, power, and functional yield of carbon nanotube (CNT) based circuits. In this paper, we present tradeoff between these parameters with the help of Monte Carlo simulations for basic logic gates designed using four different configurations of CNFET including two stacking configurations that we originally proposed in 2008. We present newly developed analytical models to estimate the functional yield of logic gates designed using four different configurations of CNFET. The absolute difference in functional yield magnitudes between the Monte Carlo simulations and analytical models for different percentage of metallic tubes and different drive strength of logic gates is 0% to 0.9% for inverter and 0% to 2.5% for NAND/NOR gates. Results indicate that the proposed stacking configurations have the potential to increase the functional yield by as much as 2X for inverter and 10X for NAND gate. This increase in functional yield was observed for 10X lower static power and for 4.1X-4AX delay penalty under iso-input capacitance.

The aggressive scaling of CMOS circuits is approaching the atomic and quantum physical limits [1], and therefore extensive research is being conducted on devices made with III-V and II-VI semiconductors, and with more exotic materials like grapheme, and various nanotubes.

One of the major challenges faced by CNFET technology is unwanted growth of metallic tubes that adversely affect the performance, power, and yield of circuits designed with CNFETs. Selective Chemical Etching (SCE) and VLSI-Compatible Metallic-Carbon-Nanotube Removal (VMR) techniques have been proposed to remove the unwanted metallic tubes. Unfortunately, both of these techniques also remove a large fraction of semiconducting tubes. Tube removal can result in degradation of circuit performance and non-functioning open-circuit logic gates. We have developed analytical models to quickly estimate the functional yield of CNFET-based circuits, in the presence of metallic tubes, and after their removal. The absolute difference in functional yield magnitudes between Monte Carlo simulations and our analytical models differ between 0.4% and 2.6% for an inverter, and between 0.2% and 3.4% for NAND/NOR gates.

Carbon Nano-Tube Field Effect Transistors (CNFETs) offer promising solutions beyond conventional CMOS FETs. CNFETs have higher current drive capability, ballistic transport, lesser power delay product and higher thermal stability. The delay evaluation in CNFETs may not be trivial due to additional CNFET specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs that determines current driving capability. Moreover, the initial presence of metallic tubes and their desired removal may result in non-uniform pitch distribution. This random pitch behavior depends on the percentage of metallic tubes and the removal technique deployed. The necessary removal of the metallic tube may have significant impact on the performance of the circuit. In this paper, we propose a closed-form model to capture the impact of metallic tubes and the removal techniques on the gate and circuit delay. The influence of CNT position in the tube array of the gate on the gate-delay is captured in Logical Effort (LE) model. Our model results in fairly accurate delay estimation with an average error 2% – 5% for set of tested CNFET circuits.

Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (SS 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications.

CNFETs have potentials to replace CMOS devices due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. The presence of metallic Carbon Nanotubes (m-CNTs) is one of the major fabrication challenges as it negatively impacts the performance, power and yield of CNFET-based circuits. We verified on larger circuit a newly developed capacitance-based Logical Effort (LE) model for ideal CNFETs, and adopted it to estimate the delay of CNFET-based circuits with the variation of the number of tubes in the channel. The variation results from the initial presence of metallic tubes, which are next removed by one of the known removal techniques. Our model results in fairly accurate delay estimation with maximum error less than 5% for a set of tested CNFET circuits.

We propose a new floorplanning approach for TSV-based 3D ICs. A non-negligible area occupied by TSVs, TSVs physical locations and nets-to-TSVs assignment considerably influence chip area, wirelength and delay. TSVs also induce significant thermo-mechanical stress in nearby silicon. The proposed approach addresses the above issues by co-placement of TSVs with circuit blocks, and concurrent nets-to-TSVs assignment for total delay minimization. During the floorplanning process we consider appropriate TSV pitch, Keep-Out-Zone (KOZ) around TSVs and the contribution of TSVs to interconnect delay. Our experimental results show improved solution quality with up to 7% shorter wirelength and an average 8% reduction in the number of TSVs as compared to most recent publications. The total delay reduces between 8% and 36% when delay-aware, instead of wirelength-aware, cost function is used.

A new approach to the interconnect-driven floorplanning problem integrates bus planning and is intended for bus-based designs where each bus consists of a large number of wires. The floorplanner optimizes the timing and ensures routability by generating the exact location and shape of interconnects above and between the circuit blocks. Experiments with Microelectronics Center of North Carolina benchmarks clearly show the advantage of integrated floorplanning over the classical floorplan-analysis-and-then-refloorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12%-13% smaller in area as compared to traditional floorplanning algorithms.