173 results on '"Malgorzata Chrzanowska-Jeske"'
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52. Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs.
53. Generalized symmetric and generalized pseudo-symmetric functions.
54. Regular symmetric arrays for non-symmetric functions.
55. Variable ordering for regular layout representation.
56. Supply current spectrum estimation of digital cores at early design.
57. A novel net-degree distribution model and its application to floorplanning benchmark generation.
58. Synthesis approach to multi-level regular representation for combinational circuits.
59. Using simulation and satisfiability to compute flexibilities in Boolean networks.
60. Linear cofactor relationships in Boolean functions.
61. Layout synthesis for datapath designs.
62. Tree restructuring approach to mapping problem in cellular-architecture FPGAs.
63. Output Column Folding for Cellular-Architecture FPGAs.
64. Multiple-Valued-Input TANT Networks.
65. A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays.
66. Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device.
67. An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD.
68. Integrated floorplanning with buffer/channel insertion for bus-based designs.
69. Board-level multiterminal net assignment for the partial cross-bar architecture.
70. Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts.
71. Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs.
72. Minimization of multioutput TANT networks for unlimited fan-in network model.
73. Logic Synthesis for a Regular Layout.
74. Estimation of supply current spectrum for early noise evaluation.
75. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization
76. Fast Thermal Goodness Evaluation of a 3D-IC Floorplan
77. Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions.
78. A New Design Methodology for Two-Dimensional Logic Arrays.
79. An Exact Solution to the Fitting Problem in the Application Specific State Machine Device.
80. Carbon Nanotube Length Variation in Correlated CNFETs
81. Tube Redundancy in Statistical Evaluation of Critical Path Delay of CNFET Circuits in the Presence of Tube variations
82. TSV- and delay-aware 3D-IC floorplanning
83. Through Silicon Via-Aware Layout Design and Power Estimation in Sub-45 Nanometer 3D CMOS IC Technologies
84. Thermal Management in 3D IC Designs for Nano-CMOS Technologies: Analysis on Graphene- vs. Graphite-based TIM
85. Analysis of Yield Improvement Techniques for CNFET-Based Logic Gates
86. Statistical evaluation of critical path delay in CNFET-based circuits in the presence of CNT fabrication imperfections
87. Semiconductor Devices in Harsh Conditions
88. Semiconductor Devices in Harsh Conditions
89. Performance optimization and power efficiency in 3D IC with buffer insertion scheme
90. Fast and accurate evaluation of delay in CNFET circuits
91. Buffered Interconnects in 3D IC Layout Design
92. Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs
93. Functional Yield Estimation of Carbon Nanotube-Based Logic Gates in the Presence of Defects
94. Delay and yield of CNFET-based circuits in the presence of variations
95. Yield estimation of CNFET-based circuits with imperfections
96. Logical Effort model for CNFET circuits with CNTs variations
97. Using simulation and satisfiability to compute flexibilities in Boolean networks
98. Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes
99. 3D floorplanning with nets-to-TSVs assignment
100. Integrated floorplanning with buffer/channel insertion for bus-based designs
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