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The sampling noise cancellation (SNC) technique has been applied to different discrete-time circuits in recent literature, but the cost of this technique has not been well studied. This paper gives a detailed analysis of the SNC approach in a track-and-hold amplifier (THA). Closed-form expressions are derived for each noise source in the THA during the sampling phase and are verified by simulations. The analysis shows that while the sampling noise can be cancelled, the noise from the extra amplifier and switches can become dominant and even outweigh the benefits from SNC. Therefore, the SNC technique should be used with attention to the trade-offs, as described in this paper.

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison techniques. A pre-comparison technique is proposed to solve the over-range problem caused by MES. With MES and pre-comparison, the digital-to-analog converter (DAC) mismatch error can be first-order shaped, while a full input range is maintained. Besides, data-driven noise reduction and chopping techniques are combined to reduce the comparator noise efficiently. The prototype in 65-nm CMOS achieves 84.5-dB signal-to-noise-and-distortion ratio (SNDR) and 103-dB spurious-free dynamic range (SFDR) in a 4-kHz bandwidth, with a power consumption of 0.98 mu {W} from a single 0.8-V supply and an area of 0.033 mm2, resulting in a Schreier figure of merit (FoM) of 180.6 dB and a Walden FoM of 8.9 fJ/conversion-step, respectively. Among ADCs with above 100-dB SFDR, this is the smallest design without calibration and the only sub- mu {W} and sub-1-V design. These features make it suitable for high-resolution and low-cost applications.

This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy 20times 21,,mu text{m} , 20times 36,,mu text{m} , 36times 36,,mu text{m} and 36times 36,,mu text{m} , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs.

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of 32 mu mathrm{W}. The estimated area is 0.002 mm2 including decoupling capacitors.

This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 W, and it provides 15 dB anti-aliasing in the alias band.

This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.

This paper presents a dynamic temperature sensor in 65nm CMOS with on-chip analog gain and offset correction for low power systems. By shifting the reset phase of the N-bit ADC, offset correction with a range of \pm 2^{(N-1)} LSB is realized. Fine tuning capacitors are introduced to improve the offset correction accuracy to 0.5LSB. By adding programmable parasitic capacitors, gain errors up to 6.3% can be compensated. Thanks to the proposed analog correction techniques, the gain errors are reduced to 0.73% and the offsets are reduced to 0.5LSB. This sensor consumes 2.74pJ per conversion and only occupies an area of 0.0018 mm2 including the extra correction techniques. It has an RMS resolution of 0.47K, leading to a FoM of 0.6 pJ.K2.

This brief presents a 10.5-bit 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) with 1.5times input range (IR). By pre-setting and resetting the most significant bit (MSB) of the digital-to-analog converter (DAC) to shift the input signal accordingly, the input range of the ADC is enhanced by a factor of 1.5. This effectively relaxes the noise requirement and thus improves the power efficiency of the ADC. The prototype implemented in 65-nm CMOS technology achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.37 dB and a spurious-free dynamic range (SFDR) of 82.2 dB. It consumes 18.65~mu text{W} at 10 MS/s with a 0.8V supply and only occupies an area of 0.0013 mm2. The resulting Walden figure of merit (FoM _{W} ) is 2.2 fJ/conversion-step.

This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.