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TaSiO"x thin films with Si/(Ta+Si) mole fractions between 0 and 0.6 have been deposited using atomic-layer deposition on Si and InGaAs at 250^oC. Interface defects on InGaAs were on the order of 10^1^2cm^-^2eV^-^1, which is comparable to state-of-the-art Al"2O"3 deposited by atomic-layer deposition using Al(CH"3)"3 and H"2O while the dielectric permittivity of TaSiO"x is considerably higher.

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, L g of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-? deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

The physical and electrical properties of the gate stack high-k/Al2O3/GeO2/p-Ge were studied in detail, where the high-k is either HfO2 or alloyed HfO2 (HfZrOy, HfGdOx, or HfAlOx). Electrical measurements combined with x-ray photoelectron spectroscopy chemical bonding analysis and band alignment determination were conducted in order to assess the suitability of hafnium-based high-k for this kind of gate stacks, with emphasis on low density of interface states and border traps. HfAlOx was found to be the most promising high-k from those studied. The authors have also found that the current- voltage trends for the various systems studied can be explained by the band alignment of the samples obtained by our x-ray photoelectron spectroscopy analysis. Fil: Fadida, Sivan. Technion - Israel Institute of Technology; Israel Fil: Palumbo, Félix Roberto Mario. Technion - Israel Institute of Technology; Israel. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina Fil: Nyns, Laura. Imec; Bélgica Fil: Lin, Dennis. Imec; Bélgica Fil: Van Elshocht, Sven. Imec; Bélgica Fil: Caymax, Matty. Imec; Bélgica Fil: Eizenberg, Moshe. Technion - Israel Institute of Technology; Israel

High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. In these new material systems and devices various electrically active defects are present at or close to the interface between the high-k dielectric and the alternative channel material which are a major concern for both the performance and the reliability of these new devices.

Over the last years there has been lots of interest in the use of germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility has attracted lots of attention for its application in advanced pMOS devices. Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS devices beyond 14 nm node technology.

Atomic layer deposition is a promising technique to deposit conformal, nm-thin metal barriers in high aspect ratio trenches. However, exactly because of its excellent conformality, the deposition can also occur inside the nanopores of the most advanced low-k materials. In this work, the mechanisms of atomic layer deposition on and in low-k, porous dielectric films were studied, using HfO 2 as a test material. Exhaustive analyses showed firstly that the HfCl 4 precursor penetrated uniformly in the pores throughout a 44 nm low-k film. Secondly it is shown that the pores were sealed as function of precursor size, i.e. there are conditions where the pores became inaccessible for HfCl 4 , while the - smaller - H 2 O molecules could still penetrate the pores. From these analyses a deposition model was proposed.

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Atomic layer deposition (ALD) has been successfully used over the years for the deposition of conformal dielectric layers with precise thickness down to the nanometer scale. Therefore, optimization of the growth behaviour of the dielectric is mandatory. Since ALD is a surface sensitive growth technique, determined by the amount of available reaction sites at the starting surface, the impact of various wet chemical and thermal Si treatments on the HfO2 growth was evaluated. Thin SiO2 starting layers, based on wet chemical processing, were prepared by using a diluted peroxide mixture and an ozone/DI-water treatment. The thermally grown oxides were gradually etched by slowly immersing the oxidized Si substrate into a diluted HF solution, creating a thickness range on a single wafer. Our results demonstrate that the HfO2 deposition is more dependent on the thickness of the SiO2 layer than on the chemistry used to grow the oxide layer. For all studied oxides, two regions can clearly be distinguished. First, a linear relationship between the oxide thickness and the amount of deposited HfO2 is seen. Because chemical oxides tend to grow in islands, this trend can be explained by an increase in density of surface OH groups when the oxide grows thicker. When an ellipsometric thickness of ~0.8 nm is reached, saturation of the HfO2 growth is obtained. We believe that, from this thickness on, the starting surface is completely covered with hydroxyl groups, leaving the HfO2 growth only dependent on the ALD process itself. Since both the wet chemical as the thermal oxides are showing the same trend in HfO2 deposition, it can be stated that surface preparations can be selected solely based on their ease of processing. However, the electrical results show that there may be a difference between the ozone based wet chemical oxides and the etched thermal oxides, since the latter seems to possess slightly more leakage current. The electrical results will be discussed in more detail during the presentation.

In the path to incorporating Ge based metal-oxide-semiconductor into modern nano-electronics, one of the main issues is the oxide-semiconductor interface quality. Here, the reactivity of Ti on Ge stacks and the scavenging effect of Ti were studied using synchrotron X-ray photoelectron spectroscopy measurements, with an in-situ metal deposition and high resolution transmission electron microscopy imaging. Oxygen removal from the Ge surface was observed both in direct contact as well as remotely through an Al2O3 layer. The scavenging effect was studied in situ at room temperature and after annealing. We find that the reactivity of Ti can be utilized for improved scaling of Ge based devices. (C) 2014 AIP Publishing LLC.

The passivation of the interface between the IIIV substrate and the high-k is key in order to bring these materials into the 7nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons resulting in a reduced mobility and degraded subtreshold slope[1]. Additional defects present in the oxide near the IIIV interface will generate device instabilities[2]. The goal should be to reduce the amount of oxide traps below 1.5E10/cm2at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values ( TMA prepulsing, H2S exposure as well as the incorporation of a thin ALD rare earth (RE) oxide layer have been studied as a way to reduce the Dit level at the In0.53Ga0.47As/high-k interface. In addition, we present the oxide trap behavior for these different pretreatment/high-k combinations. TMA prepulsing has been reported to improve the interface quality of the In0.53Ga0.47As/ high-k interface[3]. We have studied the influence of the TMA pulse length in combination with ALD Al2O3 (TMA/H2O), HfO2 (HfCl4/H2O) and AlSiOx (TMA based and C-free process). For a 4nm Al2O3 layer, an optimal Dit is obtained when the TMA pulse length is increased from the standard 0.1 s up to 5 s during the first 5 ALD cycles (Figure 1). For a higher number of cycles with long TMA pulses, the Dit level increases again. This could be attributed to the increase of unreacted –CH3 groups as the H2O pulses were kept the same as compared to the standard TMA pulse length. Similar behavior can be found with a 4nm HfO2 stack: pretreatment of the interface with 5 cycles (TMA/H2O purge) with a 5s TMA pulse lowers the Dit by a factor ~2 compared to no pretreatment. The idea of using AlSiOx is to slow down the oxide trap response because of a possible higher Ec offset to the InGaAs channel. The incorporation of Si into the Al2O3 stack is accompanied with a Dit reduction, but at the expense of a CET increase. Again, prepulsing with TMA lowers the Dit level as seen with the Al2O3 process down to a midgap Dit of ~8E11 /cm2eV (see Figure 2). However, in the case of a C-free AlSiOx process, a Dit increase is accompanied when prepulsing with TMA. For this process, a S-terminated InGaAs surface lowers the Dit of the formed gate stack and a similar level of ~8E11 /cm2eV can be reached. Finally, the incorporation of RE-oxides as an interfacial passivation layer was studied for both Al2O3 (4nm) and HfO2 (4nm). Both Sc2O3 ((MeCp)3Sc/H2O) and Gd2O3 (i(PrCp)3Gd)/H2O) were studied and in each case, the insertion of 4 ALD cycles reduces the Dit. The lowest Dit level was observed for Gd2O3 (~2E12/cm2eV independent of the cap layer). The oxide trap behavior for several of these gate stacks was also studied. An H2S treatment improves the oxide trap behavior slightly (~2% reduction of oxide traps). Shifting from a TMA based AlSiOx process to a C-free AlSiOx process yields a reduction of a factor ~1.5. However, the range of oxide traps for all these stacks is higher than 5e11/cm2 at the target field, which is still 1 order of magnitude too high. We demonstrate that the final gate stack passivation is dependent on the interaction between the In0.53Ga0.47As surface termination and the ALD precursors. A long TMA prepulse seems to be beneficial for most of the gate stacks but the improvement cannot be generalized. We demonstrate that the pretreatments used for Dit optimization of the Al2O3 stack, can also be applied in combination with HfO2. This means that we can reach similar Dit levels with a HfO2 based stack using the right pretreatment with large reduction in CET. Despite this improvement on interface traps, the improvement on oxide traps is not substantial. A further reduction of interface traps, will not yield a proportional device improvement 1. However, a further reduction of oxide traps is a prerequisite in order to introduce the IIIV channel materials into the 7nm technology node. [1] G. Hellings et al, IEEE Transactions on Electron Devices, 58(4), (2011), 938-944. [2] D. Lin et al., IEDM, (2012), p645-648. [3] J.B. Clemens et al., J. Chem. Phys., 133, (2010), 154702.

Transition metal compounds showing a metal-insulator transition (MIT) show complex behavior due to strongly correlated electron effects and offer attractive properties for nano-electronics applications, which cannot be obtained with regular semiconductors. MIT based nano-electronics, however, remains unproven, and MIT devices are poorly understood. We point out and single out one of the major hurdles preventing MIT-electronics: obtaining a high Off resistance and high On-Off resistance ratio in an MIT switch. We show a path toward an MIT switch fulfilling strict Off and On resistance criteria by: (1) Obtaining understanding of the VO2-interface, a protoypical MIT material interface. (2) Introducing a MIT tunnel junction concept to tune switch resistances. In this junction, the metal or insulating phase of the MIT material controls how much current flows through. Adapting the junction's parameters allows tuning the MIT switch's Off and On resistance. (3) Providing proof of principle of the junction and its...

The passivation of the interface between Ge and the gate dielectric is a critical issue for the integration of Ge into next generation CMOS devices. GeO2 has recently garnered a lot of interest, but there is always a trade-off between low interface state densities and a low equivalent oxide thickness. In this paper we investigate the S-passivation of the Ge gate stack in which only 1 monolayer of S is needed in order to improve the interface properties of the gate stack. S-passivation is achieved via exposure of the clean Ge(100) surface to H2S. The high-k dielectric is deposited via atomic layer deposition. We show that the oxidant precursor type (H2O versus O3) will result not only in different growth behavior but also in different interface properties. The H2O based process results in low defect densities at the valence bandedge, whereas the O3 based process results in low defect densities at the conduction bandedge.

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Hafnium aluminates have been investigated as high-κ dielectrics for implementation in sub-45 nm nonvolatile memory technologies. The growth behavior and quality of these dielectrics strongly depend on the applied deposition technique. We examine the surface reactions that occur during the atomic layer deposition (ALD) of hafnium aluminates from HfCl 4 , Al(CH 3 ) 3 , and H 2 O. When grown in the ALD sequence (HfCl 4 /H 2 O) a [Al(CH 3 ) 3 )/H 2 O] b , HfCl 4 chemisorption is enhanced while that of Al(CH 3 ) 3 is inhibited compared to the reaction during ALD of the respective binary oxides. Density functional theory simulations suggest that this observation is related to the more efficient hydrolysis of the Al-C bond compared to Hf―Cl. However, earlier works on ALD of HfCl 4 /H 2 O suggest that the low growth per cycle of this process is not caused by a limited hydrolysis of the Hf―Cl bond but by dehydroxylation of the generated Hf-OH surface sites into less reactive Hf―O―Hf surface sites. Hence, we propose that the enhanced HfCl 4 and inhibited Al(CH 3 ) 3 chemisorption during ALD of hafnium aluminates results from a difference in dehydroxylation behavior between both binary oxides.

The continuous downscaling of complementary metal oxide semiconductor devices has required the integration of Hf-based high-k materials as gate dielectrics deposited by atomic layer deposition (ALD). When tetrakisethylmethylamino hafnium (TEMAH) is used as the metallic precursor to deposit such Hf-based materials, its limited thermal stability can result in precursor decomposition. This paper shows to what extent precursor decomposition affects the growth behavior of the TEMAH/H 2 O ALD in the temperature range 285-365 °C as well as the properties of the deposited HfO 2 layer. In this temperature range, the TEMAH pulse does not saturate up to pulse lengths of 10 s due to parasitic growth. Parasitic growth occurs when chemisorbed TEMAH ligands decompose and newly introduced precursor molecules react with these decomposed surface sites. The existence of such uncontrolled growth was proven by the repetition of TEMAH/N 2 reaction cycles, resulting in the deposition of a poor-quality Hf-based layer, while its contribution depends on both the reaction temperature and the TEMAH pulse length. Finally, also the H 2 0 pulse needs to be strictly controlled because too long pulses result in temperature-induced dehydroxylation of the surface, lowering the GPC of the TEMAH/H 2 O process with up to ~ 12% at 285°C.

The 0 2 /N 2 flow ratio during O 3 generation by dielectric barrier discharge has a large impact on the atomic layer deposition (ALD) of metal oxides in a hot wall ALD reactor. For HfO 2 ALD using HfCl 4 as a metal precursor, a higher growth per cycle and a broader ALD temperature window are obtained when N 2 is added to the O 2 supply of the O 3 generation. A positive impact of N 2 in the 0 3 generation is also observed for ZrO 2 and La 2 O 3 ALD. A negative impact is observed for Al 2 O 3 ALD: The Al 2 O 3 thickness is reduced for those conditions for O 3 where Hf0 2 ALD is enhanced.

The downscaling of high-k/metal gate transistor devices requires thin-film deposition processes that deliver not only an outstanding high-k oxide quality, but also a strict interfacial oxide thickness control in the sub-1 nm thickness range. To study the impact of atomic layer deposition (ALD) process conditions and chemistry on the HfO 2 quality and interfacial oxide thickness, we have used tetrakis[ethylmethylamino]hafnium (TEMAH) as a metal precursor and H 2 O and 0 3 as oxidants. The deposition temperature ranged from 285 up to 365 °C, where TEMAH decomposition plays a role in the growth mechanism. Physical characterization and Pt dot capacitor devices have been used to study the impact of the oxidant and process conditions on the equivalent oxide thickness and gate leakage current of 2-4 nm thin HfO 2 films. By combining X-ray reflectometry and ellipsometry, we evaluated the Si/high-k interfacial oxide layer thickness. Time-of-flight secondary-ion mass spectroscopy was used to determine the C impurity levels. Both the interfacial oxide layer thickness and the C impurity level in the Si/SiO 2 /HfO 2 stacks are strongly dependent on the oxidant. The temperature dependence of the C impurity level is opposite for O 3 and H 2 O. Furthermore, SiO 2 regrowth was found for the 0 3 process.

Hafnium titanate (HTO) films were deposited within a large Hf-Ti compositional range by atomic layer deposition using HfCl4/TiCl4/H2O precursors. The Hf content of the layers is well controlled by the precursor pulse ratio, as indicated by Rutherford backscattering. The saturation conditions of ternary HTOs are different compared to those of the binary oxides, First-principles simulation confirmed the enhancement of the Hf precursor reactivity in the presence of Ti-OH. Growth curves of HTOs showed a good linearity with the number of reaction cycles. A linear correlation between density, quantified by X-ray reflectometry, and composition was observed. X-ray diffraction indicated that the as-deposited films are amorphous up to 500-700 degrees C, depending on the Hf/Ti ratio. The orthorhombic HfTiO4 diffraction lines in the samples (30-64% Hf) annealed at 850 degrees C were observed. For a Hf content higher than 82%, a monoclinic HfO2-Iike structure was reported. The dielectric constant and leakage current depend on the Ti content, the film crystallinity, and the anneal atmosphere. The posideposition anneal in O-2, is found to have a drastic effect in leakage Current density reduction and could be a key for further improvements of HTO electrical properties.

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The continuous downscaling of complementary metal oxide semiconductor devices demands the introduction of dielectric layers with a high permittivity K. Three-dimensional (3D) transistor structures, such as FinFET devices, require excellent step coverage by the high-K material as provided by atomic layer deposition (ALD). In addition, because of the 3D structure, surfaces with different crystallographic orientation need to be covered. Because the initial HfO 2 deposition using ALD HfCl 4 /H 2 O is governed by the OH surface density, we investigated its dependence on the crystallographic orientation of the silicon substrate. For oxidations in O 3 /H 2 O, a (110) orientated substrate oxidizes faster than silicon (100) up to a thickness of ∼0.7 nm as measured by X-ray photoelectron spectroscopy. Also, irrespective of the substrate orientation, the HfO 2 deposition is found to increase with increasing SiO 2 thickness and thus OH coverage of the surface. This implies that, for oxide thicknesses below0.7 nm, the oxidation of silicon (100) results in a thinner oxide and, hence, less HfO 2 deposition in comparison to silicon (110). However, these differences are marginal after implementation in transistor devices as is shown by their capacitance and mobility. As a result, for FinFET applications, a conformally deposited HfO 2 layer will be independent of the crystallographic substrate orientation.

The growth behavior and film quality of HfO 2 deposited by atomic layer deposition (ALD) using HfCl 4 /H 2 O depends on the hydroxylation of the exposed surface. In this work, we investigate the dependence of the first HfCl 4 chemisorption reaction at 300°C on the OH density of the silicon surface. We observe that the hydroxyl density, and hence the Hf deposition, on O 3 /H 2 O wet oxides depends on the initial preparation as well as on the stabilization time in the ALD reactor. A good understanding of the initial nucleation behavior is necessary because wet oxides are used in complementary metal-oxide-semiconductor transistors as surface pretreatment for aggressively scaled HfO 2 gate dielectrics. Moreover, the HfCl 4 chemisorption reaction is used to estimate the hydroxylated fraction of these surfaces by means of theoretical models. Finally, the temperature dependence of the OH density, as available in the literature, is applied to gain insight into the stoichiometry of the HfCl 4 chemisorption reaction.

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Growing nanometer-thin HfO 2 films by atomic layer deposition (ALD) for implementation in advanced transistor structures is controlled by the density of reactive OH sites on the surface. The impact of thin SiO 2 starting surfaces, grown by wet chemical processes and by wetting a thermal oxide, on the nucleation and growth of ALD HfO 2 has therefore been evaluated. Our results demonstrate that both surface pretreatments display the same dependence of the initial HfO 2 growth on the interfacial layer thickness. This correlation is first characterized by a linear increase, which can be interpreted in terms of increasing OH surface concentration. Once an ellipsometric oxide thickness of approximately 0.8 nm is reached, saturation of the HfO 2 deposition occurs. Maximal OH coverage of the surface or steric hindrance of the adsorbed precursor molecules could explain this observation. However, the increased growth-per-cycle at lower deposition temperatures can be attributed to an improved hydroxylation of the surface, excluding steric hindrance as the primary factor causing saturation. Furthermore, electrical characterization revealed that both interfacial oxides show identical leakage scaling behavior down to an equivalent oxide thickness of 0.8 nm.